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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
told dc to look in synth directory for hdl and WORK
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2dc074ea93
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@ -26,11 +26,11 @@ set saifpower $::env(SAIFPOWER)
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set maxopt $::env(MAXOPT)
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set drive $::env(DRIVE)
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eval file copy -force ${cfg} {hdl/}
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eval file copy -force ${cfg} {$outputDir/hdl/}
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eval file copy -force ${cfg} $outputDir
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eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
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eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
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eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
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eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/}
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eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
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eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/}
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# Only for FMA class project; comment out when done
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# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
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@ -41,7 +41,7 @@ if { $saifpower == 1 } {
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}
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# Verilog files
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set my_verilog_files [glob hdl/*]
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set my_verilog_files [glob $outputDir/hdl/*]
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# Set toplevel
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set my_toplevel $::env(DESIGN)
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@ -56,7 +56,7 @@ set vhdlout_show_unconnected_pins "true"
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# Due to parameterized Verilog must use analyze/elaborate and not
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# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
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#
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define_design_lib WORK -path ./WORK
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define_design_lib WORK -path ./$outputDir/WORK
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analyze -f sverilog -lib WORK $my_verilog_files
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elaborate $my_toplevel -lib WORK
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@ -183,9 +183,9 @@ set_fix_multiple_port_nets -all -buffer_constants
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# group_path -name INPUTS -from [all_inputs]
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# group_path -name COMBO -from [all_inputs] -to [all_outputs]
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# Save Unmapped Design
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#set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"]
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#write_file -format ddc -hierarchy -o $filename
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Save Unmapped Design
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set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"]
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write_file -format ddc -hierarchy -o $filename
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# Compile statements
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if { $maxopt == 1 } {
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