1073 Commits

Author	SHA1	Message	Date
Katherine Parry	1bd6351e1f	re-added FStore2 in Cache	2022-07-29 22:54:49 +00:00
David Harris	93d7d7179e	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
David Harris	75a265159b	Increased timeout threshold to avoid timeout building riscof tests on slow machine	2022-07-27 04:05:21 +00:00
David Harris	9ecef0c4cd	fixed testbench merge comflict	2022-07-26 06:21:46 -07:00
David Harris	2d7f4b133c	More work toward riscof tests	2022-07-26 06:19:13 -07:00
David Harris	766252db1b	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-25 23:29:08 +00:00
David Harris	5c54c5b521	Added rv32f tests to RV64gc	2022-07-25 23:29:05 +00:00
David Harris	c6a58eb5b6	Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd	2022-07-25 16:23:10 -07:00
David Harris	416f5edfe0	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
David Harris	7f7b3359b0	Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings	2022-07-25 20:50:38 +00:00
Ross Thompson	8193946996	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-23 08:41:59 -05:00
Ross Thompson	05484c4c05	signal name cleanup.	2022-07-22 23:36:27 -05:00
Ross Thompson	27e32980ad	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	17ae1a1b1b	cache fsm cleanup after removal of replay.	2022-07-22 23:25:09 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Katherine Parry	655e2d3810	merged radix-2 sqrt into divider - doesnt work yet	2022-07-23 00:41:18 +00:00
slmnemo	bfced6bfe8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-22 17:13:38 -07:00
slmnemo	ca4511b6dc	Fixed UART FIFO bugs and added FIFO tests	2022-07-22 17:13:19 -07:00
Daniel Torres	d0aaae26fe	fixed wally rv32e tests, updated regression makefile to new testflow	2022-07-22 17:09:46 -07:00
Katherine Parry	b3d932cd61	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
Daniel Torres	24828db612	changes to test.vh for compatability	2022-07-22 15:00:48 -07:00
Daniel Torres	4198145ce2	added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail	2022-07-22 14:58:55 -07:00
slmnemo	ba2dcf6da4	fixed error in tests.vh	2022-07-22 14:55:55 -07:00
slmnemo	ec1ed5bd94	Added UART test to peripheral test	2022-07-22 14:55:34 -07:00
Daniel Torres	574e603d69	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 13:52:19 -07:00
Daniel Torres	139e657fcc	commented out embench test that should be commented out	2022-07-22 13:52:13 -07:00
slmnemo	df411497e0	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-22 12:36:06 -07:00
slmnemo	cb16a75119	Added PLIC test to regression	2022-07-22 12:35:37 -07:00
Daniel Torres	0e75142ef4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 11:16:09 -07:00
Daniel Torres	95fdd408ee	commiting current changes to riscof wally tests	2022-07-22 11:14:04 -07:00
cturek	e2691c02b7	Square root negative exponent handling	2022-07-22 16:45:19 +00:00
slmnemo	df568fd202	Added PLIC and UART tests and new functions to the test library	2022-07-22 07:10:39 -07:00
David Harris	d22587090b	Reset MSR on read	2022-07-22 04:29:27 +00:00
Daniel Torres	ae0f8de2b5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 20:59:01 -07:00
Daniel Torres	8dcb794bbb	added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64	2022-07-21 20:58:58 -07:00
slmnemo	95822b77f0	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-21 20:35:52 -07:00
slmnemo	3d2c6683d8	Fixed UART bug related to parity and MSR/LSR	2022-07-21 20:35:46 -07:00
cturek	8bfb233204	Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder	2022-07-22 01:27:08 +00:00
cturek	c7e84f8e40	Renamed variables, moved output handling to postprocessor, added remainder handling	2022-07-21 20:45:08 +00:00
Daniel Torres	9421b77613	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 12:50:04 -07:00
Daniel Torres	a8faddf81f	removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes	2022-07-21 12:47:51 -07:00
Katherine Parry	0630e2a9a2	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-21 19:38:15 +00:00
Katherine Parry	fbe8bb2298	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
cturek	86ebdd05f0	Division working too	2022-07-21 17:59:10 +00:00
cturek	4793267bd7	Updated Radix2 Sqrt to follow new algorithm	2022-07-21 17:36:21 +00:00
Katherine Parry	7950a675ea	added input enables and improved forwarding	2022-07-21 01:20:06 +00:00
Katherine Parry	a30d9c6bd8	turn off 2 word store durring non-fp instructions	2022-07-20 21:57:23 +00:00
Ross Thompson	1cad05fef9	Minor cleanup of cache.	2022-07-19 23:04:23 -05:00
Ross Thompson	8698799077	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Katherine Parry	b26297e874	moved ctrl signal registers into fctrl, also a lot of code cleaning	2022-07-20 02:27:39 +00:00