Ross Thompson
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5ca7dc619c
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Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
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2021-07-16 11:12:57 -05:00 |
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bbracker
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f7092c60d1
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incremental linux config de-bloating
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2021-07-16 12:08:58 -04:00 |
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bbracker
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629d48f20f
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incremental linux config de-bloating
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2021-07-16 11:33:11 -04:00 |
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bbracker
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0f1060ceb7
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incremental linux config de-bloating
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2021-07-16 11:15:25 -04:00 |
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bbracker
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fcb63a409a
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incremental linux config de-bloating
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2021-07-16 01:58:21 -04:00 |
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bbracker
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0a1aa821b8
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incremental linux config de-bloating
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2021-07-16 01:54:36 -04:00 |
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bbracker
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149be959e0
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incremental linux config de-bloating
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2021-07-16 01:43:16 -04:00 |
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bbracker
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e5e3a60574
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incremental linux config de-bloating
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2021-07-16 01:33:51 -04:00 |
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bbracker
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7266b29656
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incremental linux config de-bloating
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2021-07-16 01:25:41 -04:00 |
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bbracker
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09de4ded87
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incremental linux config de-bloating
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2021-07-16 01:00:12 -04:00 |
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bbracker
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f7b43211ac
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incremental linux config de-bloating
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2021-07-16 00:46:22 -04:00 |
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bbracker
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c5e9734851
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incremental linux config de-bloating
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2021-07-16 00:41:18 -04:00 |
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bbracker
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d6a4b8ccfa
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incremental linux config de-bloating
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2021-07-16 00:34:41 -04:00 |
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bbracker
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285e5941e2
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incremental linux config de-bloating
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2021-07-16 00:16:12 -04:00 |
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bbracker
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a6071f3fb0
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incremental linux config de-bloating
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2021-07-16 00:10:31 -04:00 |
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bbracker
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226474051d
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incremental linux config de-bloating
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2021-07-15 23:53:15 -04:00 |
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bbracker
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0a15468fd5
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incremental linux config de-bloating
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2021-07-15 23:30:24 -04:00 |
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bbracker
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588a7d0341
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incremental linux config de-bloating
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2021-07-15 23:12:21 -04:00 |
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bbracker
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703b72fb89
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incremental linux config de-bloating
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2021-07-15 23:00:20 -04:00 |
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bbracker
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847edccbd7
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incremental linux config de-bloating
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2021-07-15 21:33:52 -04:00 |
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bbracker
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2091a7104e
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incremental linux config de-bloating
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2021-07-15 20:54:36 -04:00 |
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Kip Macsai-Goren
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f01be12162
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fixed output file to match sv48 test again
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2021-07-15 18:55:00 -04:00 |
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bbracker
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a4f9d7a6e5
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working linux config
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2021-07-15 18:49:54 -04:00 |
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Kip Macsai-Goren
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cc8a28e884
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fixed another address to be in tim range
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2021-07-15 18:31:53 -04:00 |
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Kip Macsai-Goren
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ba5bb12e26
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Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
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2021-07-15 18:30:29 -04:00 |
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bbracker
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58cbce940a
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stripped down busybox a bit
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2021-07-15 16:07:56 -04:00 |
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Kip Macsai-Goren
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53072d55f3
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modified sv48 test to only read or write from physical addresses located in the dtim range from 0x80000000 to 0x87FFFFFF
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2021-07-15 14:01:29 -04:00 |
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Ross Thompson
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96aa106852
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Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
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2021-07-15 11:56:35 -05:00 |
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Ross Thompson
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4549a9f1c9
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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5fb5ac3d5a
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Updated wave file.
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2021-07-15 11:04:49 -05:00 |
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Ross Thompson
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c39a228266
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Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
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2021-07-15 11:00:42 -05:00 |
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Ross Thompson
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c954fb510b
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Renamed DCacheStall to LSUStall in hart and hazard.
Added missing logic in lsu.
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2021-07-15 10:16:16 -05:00 |
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Kip Macsai-Goren
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09078ea8ab
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-15 10:52:39 -04:00 |
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Ross Thompson
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f234875779
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dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
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2021-07-14 23:08:07 -05:00 |
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Ross Thompson
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6163629204
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Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
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2021-07-14 22:26:07 -05:00 |
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Katherine Parry
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701ea38964
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Fixed lint warning
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2021-07-14 21:24:48 -04:00 |
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Ross Thompson
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d41c9d5ad9
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Added d cache StallW checks for any time the cache wants to go to STATE_READY.
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2021-07-14 17:25:50 -05:00 |
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Ross Thompson
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d3a1a2c90a
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Fixed d cache not honoring StallW for uncache writes and reads.
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2021-07-14 17:23:28 -05:00 |
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Katherine Parry
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f8b76082e4
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fpu unpacking unit created
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2021-07-14 17:56:49 -04:00 |
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Kip Macsai-Goren
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723f921f2d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-14 17:30:45 -04:00 |
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Ross Thompson
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771c7ff130
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Routed CommittedM and PendingInterruptM through the lsu arb.
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2021-07-14 16:18:09 -05:00 |
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Ross Thompson
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1d7aa27316
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Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled.
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2021-07-14 15:47:38 -05:00 |
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Ross Thompson
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3092e5acdf
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Forgot to include one hot decoder.
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2021-07-14 15:46:52 -05:00 |
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Ross Thompson
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e17de4eb11
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Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
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2021-07-14 15:00:33 -05:00 |
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bbracker
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04ce2f7256
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testvector unlinker for dev purposes
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2021-07-14 11:05:34 -04:00 |
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James Stine
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a2c0753edb
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put back for now to test fdiv
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2021-07-14 06:48:29 -05:00 |
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Abe
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853e1167a2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-14 04:47:31 -04:00 |
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Abe
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a823190ce4
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Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use
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2021-07-14 04:46:11 -04:00 |
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bbracker
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9b6d45ead9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-14 00:21:39 -04:00 |
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bbracker
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61e6ebd4d3
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make testvector scripts agree with new file structure; use symbols to determine end of linux boot
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2021-07-14 00:21:29 -04:00 |
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