Ross Thompson
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fc2b4453ec
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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de2672231d
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Ross Thompson
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d8947fa616
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cleanup of ram.sv
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2022-03-11 18:09:22 -06:00 |
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Ross Thompson
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bdfca503fa
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Name cleanup.
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2022-03-10 18:44:50 -06:00 |
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Ross Thompson
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5c16b65a16
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simplified uncore's name for HWDATA.
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2022-03-10 18:17:44 -06:00 |
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Ross Thompson
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543e10ab32
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Moved subwordwrite to lsu directory.
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2022-03-10 18:15:25 -06:00 |
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Ross Thompson
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54abd944e2
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Simplified byte write enable logic.
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2022-03-10 18:13:35 -06:00 |
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Ross Thompson
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50789f9ddd
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Byte write enables are passing all configs now.
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2022-03-10 17:26:32 -06:00 |
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Ross Thompson
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f7df3a0666
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Progress on the path to getting all configs working with byte write enables.
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2022-03-10 17:02:52 -06:00 |
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Ross Thompson
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83133f8c47
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Partially working byte write enables. Works for cache, but not dtim or bus only.
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2022-03-10 16:11:39 -06:00 |
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Ross Thompson
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d5f524a15e
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Added byte write enables to cache SRAMs.
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2022-03-10 15:48:31 -06:00 |
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bbracker
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b8fd06576c
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fix lint bugs in PLIC and UART
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2022-02-22 05:04:18 +00:00 |
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bbracker
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e7934c585a
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change RX side of UART to aslo be LSB-first
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2022-02-22 03:34:08 +00:00 |
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Ross Thompson
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27042f028e
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Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
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2022-02-16 15:22:19 -06:00 |
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David Harris
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15fb7fee60
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Cleaned up synthesis warnings
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2022-02-11 01:15:16 +00:00 |
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Ross Thompson
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99bb281944
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Updated fpga's bootloader to reflect the changes to the gpio address change.
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2022-02-01 10:43:24 -06:00 |
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David Harris
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62e5c7fd13
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Comments in LSU code about restructuring
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2022-01-27 15:53:59 +00:00 |
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David Harris
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ca1f7ce5d3
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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Ross Thompson
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9f7e3f147b
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Partial local dtim in lsu configuration.
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2022-01-13 17:50:31 -06:00 |
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Ross Thompson
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654a33bf92
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Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
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2022-01-12 17:41:39 -06:00 |
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David Harris
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3d2671a8b0
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Reformatted MIT license to 95 characters
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2022-01-07 12:58:40 +00:00 |
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David Harris
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913a78323c
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moved proposed-sdc
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2022-01-07 12:44:21 +00:00 |
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David Harris
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07932ad0aa
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Replaced exe2memfile with SiFive elf2hex
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2022-01-05 22:10:26 +00:00 |
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David Harris
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d17a305538
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Finished removing generate statements
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2022-01-05 16:41:17 +00:00 |
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David Harris
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6d4714651c
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Removed more generate statements
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2022-01-05 16:25:08 +00:00 |
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David Harris
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da5ead23bf
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Removed more generate statements
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2022-01-05 16:01:03 +00:00 |
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David Harris
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d66f7c841b
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Removed generate statements
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2022-01-05 14:35:25 +00:00 |
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David Harris
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115287adc8
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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