598 Commits

Author	SHA1	Message	Date
David Harris	cb4f1bec8e	Removed fcovimp support	2024-11-15 05:58:30 -08:00
Rose Thompson	a7dd2eff01	Switch rv64gc_CacheSim.py to use verilator as the default sim rather than questa.	2024-11-13 12:29:02 -06:00
Rose Thompson	ef7072b7c2	Merge branch 'main' into lrufixes	2024-11-12 17:57:28 -06:00
Rose Thompson	7868af0f81	Code cleanup.	2024-11-12 17:43:09 -06:00
Rose Thompson	8659d6efdb	Resolved all CacheSim.py vs Wally mismaches.	2024-11-12 17:24:06 -06:00
Rose Thompson	ea2b69e1e7	Updates to wavefile.	2024-11-12 14:44:09 -06:00
Rose Thompson	b7b7c79726	CBO.FLUSH was not clearing the valid bit if the cacheline was clean.	2024-11-12 14:16:55 -06:00
Rose Thompson	5cc1fd4a85	Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally.	2024-11-12 12:08:14 -06:00
Rose Thompson	8a4868ac57	Resolved a bug in the cache but there are still mismatches with the cache simulator.	2024-11-12 11:35:29 -06:00
Jordan Carlin	c776ef3fd4	enable assertions in Verilator	2024-11-10 22:20:51 -08:00
Huda-10xe	f258384596	Adding sv32 coverpoins	2024-11-01 06:07:49 -07:00
David Harris	da2310fb3e	Merge conflict in coverage.svh	2024-10-22 04:48:57 -07:00
David Harris	69cc36795b	privileged coverage updates	2024-10-22 04:45:40 -07:00
Huda-10xe	7bed187e8d	Combinin fcov and fcovpriv	2024-10-16 09:44:34 -07:00
Huda-10xe	a9e41c1a7c	Improving the priv func cov flow to run with --fcovpriv flag	2024-10-16 07:14:11 -07:00
Huda-10xe	fba5214a00	Adding a separate folder for priv coverage files	2024-10-07 04:34:09 -07:00
Huda-10xe	24f97fa696	Adding DUT signals to the tracer for VM Coverage	2024-10-07 03:49:43 -07:00
Huda-10xe	e0ea37fe21	Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi_setup	2024-10-07 03:44:43 -07:00
Huda-10xe	0817c69152	Adding priv coverage to ISACOV	2024-10-07 03:44:35 -07:00
Huda-10xe	072120d2fa	Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi_setup	2024-10-03 06:53:34 -07:00
Rose Thompson	f4b1f6a1e7	Updated coverage exclusions for the pma checker updates which fixed ... issue #980.	2024-10-02 15:41:34 -05:00
Rose Thompson	1e2a9e3b18	Added test to check for AMO access fault.	2024-10-02 14:17:37 -05:00
Jordan Carlin	29801485de	Add Xcelium readme	2024-10-01 12:48:10 -07:00
Jordan Carlin	9363379b55	Combine floating point test documentation	2024-10-01 12:44:47 -07:00
Jordan Carlin	f937e31ee9	Remove bpred-sim.py	2024-10-01 12:08:39 -07:00
Jordan Carlin	a23c1cf18b	Remove buildrootBugFinder.py	2024-10-01 12:00:12 -07:00
Huda-10xe	88eb758760	Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi_setup	2024-10-01 03:07:56 -07:00
Jordan Carlin	e1b85289f3	remove deprecated questa scripts	2024-09-30 10:44:36 -07:00
Jordan Carlin	d007f3f66f	remove deprecated verilator scripts	2024-09-30 10:44:36 -07:00
Jordan Carlin	7cfeb15c42	remove old files and scripts from sim directory	2024-09-30 10:44:36 -07:00
Huda-10xe	36d74c745d	discarding changes	2024-09-30 01:55:20 -07:00
Jordan Carlin	9711cc7348	Restore riscvdv make targets	2024-09-29 22:27:22 -07:00
Jordan Carlin	68b854fc20	Finish updating riscof and sim Makefiles to allow targets to run in parallel	2024-09-29 14:05:28 -07:00
Jordan Carlin	14d76b9189	Remove old functcov targets in Makefile	2024-09-29 10:37:08 -07:00
Jordan Carlin	ad6ab2fb0c	Wally.do cleanup	2024-09-10 16:12:10 -07:00
Jordan Carlin	ae593ed81d	Merge branch 'main' of https://github.com/openhwgroup/cvw into imperas_verbose	2024-09-10 16:10:05 -07:00
David Harris	a2a2091835	Associated coverage fixes	2024-09-09 18:06:08 -07:00
David Harris	de26b7b6a7	Per config coverage initially working with RV32M in rv32gc config	2024-09-07 07:00:52 -07:00
David Harris	ecb444697c	Starting to define per-config coverage	2024-09-07 06:14:50 -07:00
David Harris	6e0b0487dd	Recreated coverage changes	2024-09-05 16:32:45 -07:00
Jordan Carlin	9e98c834f1	Add lockstepverbose flag	2024-08-30 12:32:41 -07:00
Rose Thompson	65e338e762	Merges Jordan's wally.do updates with the new fcov2 changes. Updates ... cvw-arch-verif commit.	2024-08-30 12:31:26 -07:00
Jordan Carlin	4929581576	Cleanup	2024-08-30 11:57:31 -07:00
Jordan Carlin	80750f2308	Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates	2024-08-29 15:55:54 -07:00
Rose Thompson	e07f303353	Have basic rv32gc functional coverage running with open source riscvISACOV.	2024-08-29 15:29:04 -07:00
Rose Thompson	0ce4d1b452	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-29 10:50:27 -07:00
Rose Thompson	6ad2c2e7a6	Merge pull request #935 from davidharrishmc/dev ... Added lockstep support for RV32. Not all wally privileged tests pass…	2024-08-29 10:45:17 -07:00
David Harris	26f3c2a607	Added lockstep support for RV32. Not all wally privileged tests pass yet	2024-08-29 10:44:37 -07:00
Rose Thompson	cb05697698	Added basic SPI signals to waveform.	2024-08-27 15:51:19 -07:00
Rose Thompson	2dd897e7e1	Merge pull request #932 from davidharrishmc/dev ... Added temporary --fcov2 option to start adopting open-source riscvISACOV	2024-08-27 08:47:59 -07:00