Rose Thompson 6ad2c2e7a6 Merge pull request #935 from davidharrishmc/dev ... Added lockstep support for RV32. Not all wally privileged tests pass…		2024-08-29 10:45:17 -07:00
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bp-results	Updates to branch predictor collection.	2024-03-29 13:52:28 -05:00
questa	Merge pull request #932 from davidharrishmc/dev	2024-08-27 08:47:59 -07:00
slack-notifier	Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)	2024-07-03 20:42:55 -07:00
vcs	Update run_vcs shebang after merge	2024-07-03 23:47:26 -07:00
verilator	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00
xcelium	Reorganizing sim directory for multiple simulators	2024-04-05 18:19:46 -07:00
bpred-sim.py	Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)	2024-07-03 20:42:55 -07:00
buildrootBugFinder.py	Remove hardcoded /opt/riscv	2024-07-23 23:29:45 -07:00
coverage	tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker	2023-09-02 12:56:36 -07:00
FPbuild.txt	Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file	2023-06-20 17:26:54 -05:00
make-tests.sh	Renamed regression to sim	2023-02-02 14:48:23 -08:00
Makefile	Fixed bug in Makefile.	2024-08-21 16:04:21 -07:00
makefile-memfile	Renamed regression to sim	2023-02-02 14:48:23 -08:00
run-imperasdv-tests.bash	Revert "Update for new layout of ImperasDV files"	2023-06-13 04:17:56 -07:00
rv64gc_CacheSim.py	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
test	Renamed regression to sim	2023-02-02 14:48:23 -08:00