Ross Thompson
dbf9e5da0b
Updated Arty A7 fpga config and device tree to 256MiB main memory.
2023-07-25 15:11:47 -05:00
Ross Thompson
e99c6e5e1d
Updated arty a7 device clock speed for 20Mhz.
2023-07-24 11:50:00 -05:00
Ross Thompson
49b87d4550
Merge branch 'main' of github.com:ross144/cvw
2023-07-24 10:47:05 -05:00
Ross Thompson
065e5e98c9
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
2023-07-24 10:46:49 -05:00
Ross Thompson
481f27e3fe
Updated arty a7 device tree.
2023-07-21 19:08:45 -05:00
Ross Thompson
ab6ef5bb58
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
d04d2afed2
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
b756b248b4
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
d1ea52f6ea
Added artya7 device tree.
2023-07-17 16:01:02 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Ross Thompson
cf00f85456
Updated vcu118 constraints to run cpu at 38.43Mhz.
2022-11-15 10:19:38 -06:00
Ross Thompson
cc80f1f7b2
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
...
Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
d58a862f59
Added new device trees for vcu118 and vcu108 boards.
2022-10-24 17:45:10 -05:00
Ross Thompson
897982400c
Updated the device tree to use 30Mhz instead of 10Mhz for the cpu timebase.
2022-10-20 15:05:39 -05:00
slmnemo
a5d5bd272b
changes suggested by ben, hopefully fixing buildroot (which is now not running)
2022-05-20 18:42:38 -07:00
bbracker
871f63374e
upgrade Buildroot Makefile to also copy over vmlinux
2022-04-25 07:36:59 -07:00
bbracker
27920d3504
less hardcoded paths in Makefile
2022-04-21 20:42:02 -07:00
David Harris
5c607f2b6b
Simplified profile for UART boot; added warnings on UART Rx errors
2022-04-21 04:54:45 +00:00
bbracker
3aec080e15
parsePlicState.py bugfix
2022-04-13 13:04:43 -07:00
bbracker
52ed99ca1b
improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
2022-04-13 03:37:53 -07:00
bbracker
6c56f52e7c
fix bugs in PLIC checkpoint state parsing
2022-04-13 01:59:21 -07:00
bbracker
777de6e05b
whoops fix address for PLIC int enables in checkpoint generation
2022-04-13 01:36:09 -07:00
bbracker
3c1deb551d
deprecate remove_dup.awk in favor of expanding parseGDBtoTrace.py to internally remove duplicates; this way the instruction counts in traps.txt are hopefully now in sync with the line numbers of all.txt
2022-04-07 19:43:22 -07:00
bbracker
1e5e2704f7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 08:37:44 -07:00
bbracker
95438fca0d
fix parseQEMUtoGDB.py to pass on interrupt messages correctly
2022-04-07 04:47:15 -07:00
kaveh Pezeshki
7b85b39c48
using -S for busybox objdump to provide source code snippets
2022-04-06 23:06:49 +00:00
bbracker
241ec053e8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-06 07:50:57 -07:00
bbracker
c9c75d2e3e
filter traps list down to just interrupts
2022-04-06 07:49:44 -07:00
bbracker
241100c6ac
change RAM size in genInitMem.sh
2022-04-06 07:49:04 -07:00
David Harris
c22d6f2848
Added bootmem source ccode
2022-04-05 23:22:53 +00:00
David Harris
4f7c37e406
Changed Linux disassembly to -S to preserve source code lines
2022-04-01 16:49:13 +00:00
bbracker
6fc54435c5
checkpointSweep is bash-specific, so add shebang to make it so
2022-03-28 13:40:50 -07:00
bbracker
2900117341
fix genCheckpoint.sh binary memory dump
2022-03-27 20:54:59 -07:00
bbracker
6b812f33e1
change genCheckpoint.sh to only log 128MB of RAM
2022-03-27 19:16:39 -07:00
bbracker
284f1ab75e
fix parseGDBtoTrace.py to expect the CSRs that QEMU actually prints out
2022-03-27 19:05:44 -07:00
bbracker
d1e4b61aa3
refactored buildroot configuration
2022-03-27 15:13:03 -07:00
bbracker
6b2474a306
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-27 15:11:42 -07:00
bbracker
3dcb87473b
change devicetree to expect only 128MB of RAM
2022-03-27 15:11:36 -07:00
bbracker
b08066381a
fix multiple-context PLIC checkpoint generation
2022-03-25 01:02:22 +00:00
bbracker
9f60256f22
1st attempt at multiple channel PLIC
2022-03-24 17:08:10 -07:00
Ross Thompson
7fc128ba7c
added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
2022-03-22 21:28:34 -05:00
bbracker
e3303331ef
change genTrace to dump UART output to file so we can see how far parsing got
2022-03-08 09:52:17 -08:00
bbracker
51e68819c4
fix up PLIC and UART checkpointing
2022-03-07 23:48:47 -08:00
bbracker
9dbcdca433
change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers
2022-03-07 22:12:08 -08:00
bbracker
52bfd65fd3
change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state
2022-03-07 17:59:49 -08:00
bbracker
a93f36824d
modify debug.sh to not rely on external GDB script
2022-03-07 11:56:04 -08:00
bbracker
74ff583f9b
add debug.sh
2022-03-07 19:52:19 +00:00
bbracker
01eeab2131
update checkpointSweep in accordance to having removed trace parsing feature
2022-03-06 14:55:51 -08:00
