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1522 Commits

Author SHA1 Message Date
Ross Thompson
13e6f7d80b Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
788ae5fb18 Updated wave file. 2022-11-13 21:34:45 -06:00
Ross Thompson
9d7ba19fe1 Changed IMWriteDataM to IHWriteDataM. 2022-11-13 12:27:48 -06:00
Ross Thompson
421c6f9c48 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
hazard was not a straight forward merge.  I changed the way the LSU and IFU generate IFUStallF and LSUStallM.  They need to be suppressed by TrapM now.
 2022-11-13 12:25:22 -06:00
David Harris
84c4558641 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-13 04:23:26 -08:00
David Harris
879e62912b HPTW cleanup 2022-11-13 04:23:23 -08:00
David Harris
2ebdfa3f68 Comments about division hazards 2022-11-13 04:17:37 -08:00
Ross Thompson
54544ae251 Moved all remaining bus logic from the LSU into ahbcacheinterface. 2022-11-11 14:30:32 -06:00
cturek
4a8661649c Added integer step counter to fsm 2022-11-11 00:23:25 +00:00
Ross Thompson
c028306ba3 Fixed name change in hptw. 2022-11-10 16:13:31 -06:00
Ross Thompson
d912981ec9 Wavefile update. 2022-11-10 15:48:06 -06:00
Ross Thompson
40367eaf45 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-10 15:46:25 -06:00
Ross Thompson
8658a25218 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
028e2b0f91 Renamed CACHE_EVICT to CACHE_WRITEBACK. 2022-11-09 17:43:06 -06:00
cturek
9d30a832c3 Reoredered tests for arch32m 2022-11-09 18:42:00 +00:00
cturek
b723e16893 Fixed asign and bsign 2022-11-09 18:41:26 +00:00
Ross Thompson
be8e0eee1b Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
David Harris
f7b94c12fc Moved lsuvirtmem muxes into hptw 2022-11-07 11:13:34 -08:00
Ross Thompson
d4f4950d2c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-07 09:10:51 -06:00
cturek
d571b5f9a5 propagated otfc swap to Rad2 and 4 qslc 2022-11-06 23:32:38 +00:00
Ross Thompson
e7d24609cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-06 17:22:25 -06:00
cturek
54f09f3616 Added conditional OTFC swap for simplified int postprocessing 2022-11-06 23:09:09 +00:00
cturek
c3e635c788 Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv 2022-11-06 22:40:21 +00:00
cturek
a49ea2a16d Added n and rightshiftx 2022-11-06 22:31:48 +00:00
cturek
350d4d254f p calculation 2022-11-06 22:24:21 +00:00
cturek
83051a5351 Changed lzc names, started int/fp size merge in preproc 2022-11-06 22:21:35 +00:00
cturek
2cbe2fd70b Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench. 2022-11-06 22:08:18 +00:00
cturek
6bc4c1318e Added new macros for int div preprocessing, added p, n, and rightshiftx logic 2022-11-06 21:53:48 +00:00
David Harris
53a88fec8f Reorder embench tests to prevent crash 2022-11-04 15:21:51 -07:00
David Harris
60cfa0d69c HPTW cleanup 2022-11-04 15:21:09 -07:00
Ross Thompson
44ee31a7f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-04 13:30:08 -05:00
cturek
06a9305766 renamed remOp to RemOp 2022-11-03 22:37:25 +00:00
cturek
e37f564e84 Added rem/div operation to postprocessor 2022-11-02 17:49:40 +00:00
Ross Thompson
44171c342d Reduced complexity of logic supressing cache operations. 2022-11-01 15:23:24 -05:00
cturek
e8d7607e87 Added buffered signals for int/fp 2022-10-28 21:47:24 +00:00
cturek
9f41e57f03 Config Cleanup 2022-10-27 22:38:56 +00:00
Ross Thompson
dc3a9f2342 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-26 14:48:50 -05:00
Ross Thompson
403434580d Fixed the uart transmit fifo overrun bug. 2022-10-26 14:48:09 -05:00
cturek
7301fc7f18 small signal cleanup 2022-10-26 18:42:49 +00:00
cturek
6caf7bb7e2 abs for int inputs 2022-10-26 16:18:05 +00:00
cturek
ec4646b412 Added signed division to fdivsqrt 2022-10-26 16:13:41 +00:00
cturek
71d16eacef unbroke DIVb 2022-10-26 16:11:51 +00:00
cturek
1febdb75b7 Config cleanup 2022-10-25 21:04:09 +00:00
Jacob Pease
160ca366c8 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
cturek
ff7d6b2932 Started Integer Preprocessing 2022-10-25 17:48:43 +00:00
Ross Thompson
9ba487c323 Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
7244ca1e7b Bit width error. 2022-10-24 13:48:47 -05:00
Ross Thompson
51408c620e Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks. 2022-10-23 13:46:50 -05:00
Ross Thompson
775309165b Small cleanup of interlockfsm. 2022-10-22 16:29:51 -05:00
Ross Thompson
a59df0c77d Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00