Commit Graph

254 Commits

Author SHA1 Message Date
Limnanthes Serafini
ff72cbc1b2 Finished up testbench reformatting 2023-04-13 19:18:26 -07:00
Limnanthes Serafini
b9c97c6a8c Further indents 2023-04-13 19:07:43 -07:00
Limnanthes Serafini
44356559bc testbench code visual improvements 2023-04-13 19:06:09 -07:00
Limnanthes Serafini
2e809a4e69 A couple indents->spaces 2023-04-13 17:00:41 -07:00
Limnanthes Serafini
7d274eae74 Fix of InvalDelayed warning 2023-04-13 16:53:36 -07:00
Limnanthes Serafini
a6545a0f47 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Ross Thompson
7cdd12a40a Merge pull request #206 from AlecVercruysse/coverage2
i$ coverage improvements
2023-04-05 17:29:35 -05:00
Alec Vercruysse
8b6b96012d add ram1p1rwe for read-only cache ways (remove byte-enable)
- increases coverage
2023-04-05 11:48:18 -07:00
Limnanthes Serafini
9cbc2a8e4c Merge remote-tracking branch 'upstream/main' into cachesim 2023-04-05 09:53:05 -07:00
Limnanthes Serafini
49226a1eb2 Commenting, attribution for sim, minor log changes 2023-04-05 02:43:02 -07:00
Limnanthes Serafini
53cff56a97 Changed logging enables, debug mode in sim. 2023-04-04 23:49:35 -07:00
Limnanthes Serafini
6f7620e7c1 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00
Ross Thompson
02909b3c57 Fixed the d cache logger. 2023-04-04 14:19:19 -05:00
Ross Thompson
87e88a798f Improved d/i cache logger. 2023-04-04 13:38:32 -05:00
David Harris
115c042015 Turned off hpm counters 2023-03-28 21:28:56 -07:00
Ross Thompson
84860a062d Modified the testbench to not use the loggers for unsupported configurations. 2023-03-28 16:27:54 -05:00
Ross Thompson
c65c9e52d4 Disable loggers by default. 2023-03-28 16:20:45 -05:00
Ross Thompson
650a1a8d7e Now reports if there is a hit or miss. 2023-03-28 16:20:14 -05:00
Ross Thompson
ef26600689 Restored performance counter reports. 2023-03-28 16:15:05 -05:00
Ross Thompson
a5601ea264 Now have logging of i/d cache addresses, but the performance counter reports are x's. 2023-03-28 16:09:54 -05:00
Ross Thompson
514738ad96 Now reports i cache and d cache memory accesses. 2023-03-27 23:44:50 -05:00
Ross Thompson
059c73a4d2 First stab at the i cache logger. 2023-03-27 18:36:51 -05:00
Ross Thompson
0afba56927 Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
David Harris
ba4e0d2721 Merged bit manip 2023-03-23 06:55:29 -07:00
David Harris
3b3aa942c7 Added coverage tests to regression coverage 2023-03-22 13:00:10 -07:00
Kevin Kim
82d52f892b Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
Ross Thompson
673044f923 Modified branch logger to indicate when the warmup period is done.
The branch-predictor-simulator also changed to support this.
2023-03-13 13:26:27 -05:00
Ross Thompson
dea9dd962e Added script to separate branch.log into separate logs for each benchmark. 2023-03-12 17:58:36 -05:00
Ross Thompson
187752a339 Modified the branch log to include markers for the start and end of tests with exclusion of warmup period. 2023-03-12 17:15:56 -05:00
Ross Thompson
4db17cde2f Updated testbench to record coremark performance counters.
Added comment about mtval probably not being correct for compressed instructions.
2023-03-08 17:11:27 -06:00
Kip Macsai-Goren
f28a284e5e Merge remote-tracking branch 'upstream/main' into bit-manip 2023-03-07 13:45:04 -08:00
Kip Macsai-Goren
4cede344a1 Merge remote-tracking branch 'upstream/main' into bit-manip 2023-03-04 14:43:12 -08:00
Ross Thompson
a3a45f696f Fixed a bunch of odd bugs with the test bench preventing correct measurement of performance counters. 2023-03-03 17:49:44 -06:00
Ross Thompson
486148b45d Fixed batch mode regression test to work with hpmc loggic.
Added logic to exclude the embench warmups from preformance counters.
2023-03-03 14:59:20 -06:00
Ross Thompson
0ecd1ef681 Setup the testbench to exclude the warmup from performance counter reports. 2023-03-03 13:10:01 -06:00
Ross Thompson
e70492ea3f Added performance new counter prints to testbench. 2023-03-03 10:42:52 -06:00
Kip Macsai-Goren
055dbfe8cf removed comment out on stop in testbench 2023-02-22 20:47:14 -08:00
Kip Macsai-Goren
bb1e99a58c Cleaned up consolidated arch_b tests from tests.vh 2023-02-22 20:35:01 -08:00
Kip Macsai-Goren
d668c563f4 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
Kevin Kim
35bd4f7219 added individual zb tests in tests.vh and testbench
- also minor alu/controller configurability changes
2023-02-21 11:52:05 -08:00
Kevin Kim
9d9de8f8dd added arch32b tests (giving errors in sim however) 2023-02-20 14:39:34 -08:00
Ross Thompson
1a46c1efb2 reset branch predictor after each test. 2023-02-19 23:48:37 -06:00
Ross Thompson
407d9e7b4a Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-19 22:54:27 -06:00
Ross Thompson
89aa57e25e Possibly much better branch predictor implemention.
The complexity is significantly reduced.
2023-02-19 00:17:37 -06:00
Kip Macsai-Goren
9c3aa55349 merge upstream synth changes 2023-02-18 14:35:19 -08:00
David Harris
9d83749ca6 moved riscvassertons to its own file, added proper license headers to testbench support files 2023-02-16 19:40:27 -08:00
David Harris
0d2baed943 Reverted lab3 changes in dev branch 2023-02-16 18:10:05 -08:00
David Harris
26ea8b03c3 Merge branch 'lab3_2023' of https://github.com/openhwgroup/cvw into dev 2023-02-16 17:57:51 -08:00
David Harris
0eb0817ea1 Update testbench.sv 2023-02-16 17:55:46 -08:00
David Harris
59cb560e01 Update testbench.sv 2023-02-16 17:54:27 -08:00
David Harris
b0cedcff7c Added check that SSTC_SUPPORTED is viable 2023-02-16 07:37:44 -08:00
Kip Macsai-Goren
76593cb282 Added necessary files to make bit make and run bit manipulation tests as part of regression 2023-02-10 10:35:19 -08:00
David Harris
b09002c71d Fixed license on testbench files 2023-02-04 08:19:20 -08:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00