Limnanthes Serafini
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ff72cbc1b2
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Finished up testbench reformatting
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2023-04-13 19:18:26 -07:00 |
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Limnanthes Serafini
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b9c97c6a8c
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Further indents
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2023-04-13 19:07:43 -07:00 |
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Limnanthes Serafini
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44356559bc
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testbench code visual improvements
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2023-04-13 19:06:09 -07:00 |
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Limnanthes Serafini
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2e809a4e69
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A couple indents->spaces
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2023-04-13 17:00:41 -07:00 |
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Limnanthes Serafini
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7d274eae74
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Fix of InvalDelayed warning
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2023-04-13 16:53:36 -07:00 |
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Limnanthes Serafini
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a6545a0f47
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Logger significantly improved.
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2023-04-11 19:29:51 -07:00 |
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Ross Thompson
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7cdd12a40a
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Merge pull request #206 from AlecVercruysse/coverage2
i$ coverage improvements
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2023-04-05 17:29:35 -05:00 |
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Alec Vercruysse
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8b6b96012d
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add ram1p1rwe for read-only cache ways (remove byte-enable)
- increases coverage
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2023-04-05 11:48:18 -07:00 |
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Limnanthes Serafini
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9cbc2a8e4c
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Merge remote-tracking branch 'upstream/main' into cachesim
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2023-04-05 09:53:05 -07:00 |
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Limnanthes Serafini
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49226a1eb2
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Commenting, attribution for sim, minor log changes
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2023-04-05 02:43:02 -07:00 |
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Limnanthes Serafini
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53cff56a97
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Changed logging enables, debug mode in sim.
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2023-04-04 23:49:35 -07:00 |
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Limnanthes Serafini
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6f7620e7c1
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CacheSim edits, tests. I/D$ logging, Lim's version
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2023-04-04 21:12:35 -07:00 |
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Ross Thompson
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02909b3c57
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Fixed the d cache logger.
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2023-04-04 14:19:19 -05:00 |
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Ross Thompson
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87e88a798f
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Improved d/i cache logger.
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2023-04-04 13:38:32 -05:00 |
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David Harris
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115c042015
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Turned off hpm counters
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2023-03-28 21:28:56 -07:00 |
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Ross Thompson
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84860a062d
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Modified the testbench to not use the loggers for unsupported configurations.
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2023-03-28 16:27:54 -05:00 |
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Ross Thompson
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c65c9e52d4
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Disable loggers by default.
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2023-03-28 16:20:45 -05:00 |
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Ross Thompson
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650a1a8d7e
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Now reports if there is a hit or miss.
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2023-03-28 16:20:14 -05:00 |
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Ross Thompson
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ef26600689
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Restored performance counter reports.
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2023-03-28 16:15:05 -05:00 |
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Ross Thompson
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a5601ea264
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Now have logging of i/d cache addresses, but the performance counter reports are x's.
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2023-03-28 16:09:54 -05:00 |
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Ross Thompson
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514738ad96
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Now reports i cache and d cache memory accesses.
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2023-03-27 23:44:50 -05:00 |
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Ross Thompson
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059c73a4d2
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First stab at the i cache logger.
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2023-03-27 18:36:51 -05:00 |
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Ross Thompson
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0afba56927
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Updated GPIO signal names to reflect book.
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2023-03-24 18:55:43 -05:00 |
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David Harris
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ba4e0d2721
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Merged bit manip
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2023-03-23 06:55:29 -07:00 |
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David Harris
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3b3aa942c7
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Added coverage tests to regression coverage
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2023-03-22 13:00:10 -07:00 |
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Kevin Kim
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82d52f892b
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Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip
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2023-03-20 13:06:10 -07:00 |
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Ross Thompson
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673044f923
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Modified branch logger to indicate when the warmup period is done.
The branch-predictor-simulator also changed to support this.
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2023-03-13 13:26:27 -05:00 |
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Ross Thompson
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dea9dd962e
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Added script to separate branch.log into separate logs for each benchmark.
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2023-03-12 17:58:36 -05:00 |
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Ross Thompson
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187752a339
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Modified the branch log to include markers for the start and end of tests with exclusion of warmup period.
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2023-03-12 17:15:56 -05:00 |
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Ross Thompson
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4db17cde2f
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Updated testbench to record coremark performance counters.
Added comment about mtval probably not being correct for compressed instructions.
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2023-03-08 17:11:27 -06:00 |
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Kip Macsai-Goren
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f28a284e5e
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Merge remote-tracking branch 'upstream/main' into bit-manip
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2023-03-07 13:45:04 -08:00 |
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Kip Macsai-Goren
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4cede344a1
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Merge remote-tracking branch 'upstream/main' into bit-manip
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2023-03-04 14:43:12 -08:00 |
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Ross Thompson
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a3a45f696f
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Fixed a bunch of odd bugs with the test bench preventing correct measurement of performance counters.
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2023-03-03 17:49:44 -06:00 |
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Ross Thompson
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486148b45d
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Fixed batch mode regression test to work with hpmc loggic.
Added logic to exclude the embench warmups from preformance counters.
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2023-03-03 14:59:20 -06:00 |
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Ross Thompson
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0ecd1ef681
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Setup the testbench to exclude the warmup from performance counter reports.
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2023-03-03 13:10:01 -06:00 |
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Ross Thompson
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e70492ea3f
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Added performance new counter prints to testbench.
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2023-03-03 10:42:52 -06:00 |
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Kip Macsai-Goren
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055dbfe8cf
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removed comment out on stop in testbench
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2023-02-22 20:47:14 -08:00 |
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Kip Macsai-Goren
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bb1e99a58c
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Cleaned up consolidated arch_b tests from tests.vh
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2023-02-22 20:35:01 -08:00 |
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Kip Macsai-Goren
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d668c563f4
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-21 14:48:41 -08:00 |
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Kevin Kim
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35bd4f7219
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added individual zb tests in tests.vh and testbench
- also minor alu/controller configurability changes
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2023-02-21 11:52:05 -08:00 |
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Kevin Kim
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9d9de8f8dd
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added arch32b tests (giving errors in sim however)
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2023-02-20 14:39:34 -08:00 |
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Ross Thompson
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1a46c1efb2
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reset branch predictor after each test.
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2023-02-19 23:48:37 -06:00 |
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Ross Thompson
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407d9e7b4a
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-19 22:54:27 -06:00 |
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Ross Thompson
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89aa57e25e
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Possibly much better branch predictor implemention.
The complexity is significantly reduced.
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2023-02-19 00:17:37 -06:00 |
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Kip Macsai-Goren
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9c3aa55349
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merge upstream synth changes
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2023-02-18 14:35:19 -08:00 |
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David Harris
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9d83749ca6
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moved riscvassertons to its own file, added proper license headers to testbench support files
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2023-02-16 19:40:27 -08:00 |
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David Harris
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0d2baed943
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Reverted lab3 changes in dev branch
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2023-02-16 18:10:05 -08:00 |
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David Harris
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26ea8b03c3
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Merge branch 'lab3_2023' of https://github.com/openhwgroup/cvw into dev
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2023-02-16 17:57:51 -08:00 |
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David Harris
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0eb0817ea1
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Update testbench.sv
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2023-02-16 17:55:46 -08:00 |
|
David Harris
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59cb560e01
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Update testbench.sv
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2023-02-16 17:54:27 -08:00 |
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David Harris
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b0cedcff7c
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Added check that SSTC_SUPPORTED is viable
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2023-02-16 07:37:44 -08:00 |
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Kip Macsai-Goren
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76593cb282
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Added necessary files to make bit make and run bit manipulation tests as part of regression
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2023-02-10 10:35:19 -08:00 |
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David Harris
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b09002c71d
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Fixed license on testbench files
|
2023-02-04 08:19:20 -08:00 |
|
David Harris
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78eb90715c
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Removed pipelined level of hierarchy
|
2023-02-02 14:14:11 -08:00 |
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