Jacob Pease
2839f4f41a
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Ross Thompson
3588c53e66
It's almost working.
2023-04-18 14:24:59 -05:00
Ross Thompson
deb0bfc24d
Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
2023-04-17 20:05:59 -05:00
Ross Thompson
fbbba0e5c2
Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8.
2023-04-17 18:39:25 -05:00
Ross Thompson
2cbaa5c27b
Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way.
2023-04-17 16:37:18 -05:00
Ross Thompson
480562e53e
Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there.
2023-04-17 16:00:02 -05:00
Ross Thompson
f4734c0d1b
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
...
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
5bcb0f6ace
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
0700202001
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
Jacob Pease
b796b1b492
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Ross Thompson
0afba56927
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
Jacob Pease
2d0199a354
Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore
2023-03-24 17:01:27 -05:00
Jacob Pease
449b835fcd
Disabled old SD card and attached IOBUF's to new SD peripheral.
2023-02-28 12:20:46 -06:00
Jacob Pease
85d789a7e0
AXI Crossbar is working. Fixed address width in generator script.
2023-02-22 15:13:16 -06:00
Jacob Pease
c36d32f850
Flipped crossbar inputs and outputs to correctly place masters.
2023-01-27 14:57:36 -06:00
Jacob Pease
264f0ba0da
Removed IOBUF's from sdc_controller.
2023-01-27 14:35:34 -06:00
Jacob Pease
c8d487b9e6
Created missing wires for axi interfaces in fpgaTop.v.
2023-01-23 19:02:01 -06:00
Jacob Pease
12b379ebd8
Added IOBUFs to SDCDat. Edited debug2.xdc. Dwidth converter error.
2023-01-19 16:57:43 -06:00
Jacob Pease
ee3a9537a8
Fixed errors in uncore and included newsdc stuff in wally.tcl
2023-01-17 16:46:00 -06:00
Jacob Pease
b618518907
Fixed typos. Apparently `defube causes a weird vivado error.
2023-01-13 16:59:18 -06:00
Jacob Pease
dcfb68daee
Added IPs to wally.tcl.
2023-01-13 14:36:23 -06:00
Jacob Pease
e5d4277406
Connected the axi_sdc_controller with an axi crossbar.
...
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
2023-01-13 13:56:01 -06:00
Ross Thompson
e99a424ddc
Updated top level fpga file.
2022-11-18 11:10:45 -06:00
Ross Thompson
16e10a4c5b
added new constraints for fpga.
2022-09-17 22:20:06 -05:00
Ross Thompson
3d829dbbd3
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
41258529f0
Fixed bug in the top level of fpga verilog.
2021-12-03 17:55:36 -06:00
Ross Thompson
6a228ade04
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
Ross Thompson
96926877c4
Created top level FPGA module which replicates the schematic of the initial fpga design.
2021-11-30 17:18:28 -06:00
