Kevin Kim
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8feeaa5e94
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zbc and carry-less multiply work properly
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2023-02-15 17:37:09 -08:00 |
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Ross Thompson
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8d28524c35
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Merge pull request #82 from stineje/main
Update if-then-else for ram items
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2023-02-15 18:16:44 -06:00 |
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James Stine
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a3aeff2703
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Update if-then-else for ram items
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2023-02-15 18:12:12 -06:00 |
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David Harris
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abf3fbbebf
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Merge pull request #80 from ross144/main
Branch predictor acuracy fixes caused by last two weeks optimazations"
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2023-02-15 09:39:26 -08:00 |
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Kevin Kim
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2eb8721843
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continued ZBC integration into ALU
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2023-02-15 09:35:07 -08:00 |
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Ross Thompson
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c6920ab08e
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-15 11:29:39 -06:00 |
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Ross Thompson
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9c7339694b
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Merge branch 'main' of github.com:ross144/cvw
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2023-02-15 11:28:50 -06:00 |
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Ross Thompson
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3f91c11a08
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Merge pull request #79 from eroom1966/add-coverage
add files to support coverage
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2023-02-15 11:18:25 -06:00 |
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Kevin Kim
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2a58a86371
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added ALUResult Signal
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2023-02-15 09:13:10 -08:00 |
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David Harris
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d92f0e9642
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Ignore new tests from lab
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2023-02-15 06:43:00 -08:00 |
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David Harris
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2b80004db4
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Debug test case update
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2023-02-15 06:42:38 -08:00 |
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David Harris
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13390fffe7
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-15 06:39:17 -08:00 |
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David Harris
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7b58683d2d
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Commented config mode of synthesis makefile
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2023-02-15 06:39:10 -08:00 |
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eroom1966
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237a115377
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add files to support coverage
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2023-02-15 11:13:50 +00:00 |
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Kevin Kim
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27817c5b1d
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controller passes funct7 from decode to execute
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2023-02-14 16:06:10 -08:00 |
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Kevin Kim
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857097282c
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git
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2023-02-14 16:03:26 -08:00 |
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Kevin Kim
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420a0209dd
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Merge branch 'tmp' into main
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2023-02-14 13:12:57 -08:00 |
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Kevin Kim
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7b7957594e
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removed unncessary stuff
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2023-02-14 13:07:03 -08:00 |
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Kevin Kim
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1a209aac21
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reverted back to I tests working
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2023-02-14 13:06:31 -08:00 |
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Ross Thompson
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4d2d166b8f
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Merge pull request #77 from kevindkim723/patch-1
fixed typo in LZC
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2023-02-14 13:20:55 -06:00 |
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Kevin Kim
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4fed8d9196
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added critical rsync command to python script and builds I-ext tests
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
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2023-02-14 10:40:29 -08:00 |
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Kevin Kim
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bcea347370
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added ALU result select mux for B instructions
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2023-02-13 17:38:00 -08:00 |
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Kevin Kim
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1364ac2a14
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controller handles bclr
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2023-02-13 16:57:05 -08:00 |
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Ross Thompson
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911023f441
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Merge branch 'main' of github.com:ross144/cvw
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2023-02-13 18:54:07 -06:00 |
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Ross Thompson
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fc3baa6846
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Updated gshare (no speculation) to have better performance.
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2023-02-13 18:52:52 -06:00 |
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Kevin Kim
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2679f06a00
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Shadd instructions pass tests
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2023-02-13 16:36:17 -08:00 |
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Ross Thompson
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f3c8c6e60a
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More fixeds to global history.
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2023-02-13 18:08:51 -06:00 |
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Ross Thompson
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6ea830cf44
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Fixed global history predictor.
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2023-02-13 18:08:13 -06:00 |
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Ross Thompson
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3847d9e39a
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Updated global history predictor.
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2023-02-13 18:07:32 -06:00 |
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Ross Thompson
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1ab2d0d19b
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Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now.
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2023-02-13 17:57:05 -06:00 |
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Ross Thompson
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c18ac35332
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Created copy of gshare. I think there may be a simpler implementation.
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2023-02-13 17:29:51 -06:00 |
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Ross Thompson
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10b45ed6c7
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Further branch predictor improvements.
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2023-02-13 17:23:56 -06:00 |
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Ross Thompson
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1cfdd201a5
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Partial improvement.
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2023-02-13 17:10:24 -06:00 |
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Ross Thompson
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0165fd54b4
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Hacked commit. Fixes the gshare bugs introduced last week.
Need to recover the good changes in the next commit.
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2023-02-13 16:14:17 -06:00 |
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Kevin Kim
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02a7dc45f0
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ALU lint fixes
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2023-02-13 14:01:51 -08:00 |
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Kevin Kim
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ed6a0466ad
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ALU configurability changes
-stuff that was ZBA supported was in ZBB so I changed that
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2023-02-13 14:00:06 -08:00 |
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Kevin Kim
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c9e6b9aeef
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edited controller so that add.uw passes tests
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2023-02-13 13:49:46 -08:00 |
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Kevin Kim
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cf09bbff5f
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alu add.uw needs w64 to be false
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2023-02-13 13:49:35 -08:00 |
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Ross Thompson
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4c42b939a2
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-13 11:58:02 -06:00 |
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Ross Thompson
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716fbca2b1
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Partial fix for gshare bugs from the last two weeks.
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2023-02-13 11:57:25 -06:00 |
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Ross Thompson
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51158e94ba
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Removed another bit from btb class.
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2023-02-12 11:33:43 -06:00 |
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Kevin Kim
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19c8fa75f5
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simulation runs-- clmul doesn't pass lint with xor tree
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2023-02-11 21:22:33 -08:00 |
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Kevin Kim
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67db085b24
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lint fixes
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2023-02-11 21:13:10 -08:00 |
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Kevin Kim
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c7dbb49208
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zbb, zbs, cnt lint fixes
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2023-02-11 20:41:52 -08:00 |
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Kevin Kim
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016634d842
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fixed byte unit lints
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2023-02-11 20:25:34 -08:00 |
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Kevin Kim
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3653ea61b5
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fixed lints in cnt
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2023-02-11 20:22:42 -08:00 |
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Kevin Kim
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2dfbf15ff9
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fixed typo in LZC
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2023-02-11 19:59:03 -08:00 |
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Kevin Kim
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52ca8fa691
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popcnt passes lint
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2023-02-11 19:19:38 -08:00 |
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Kevin Kim
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2fefc3019e
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clmul passes lint
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2023-02-11 19:16:13 -08:00 |
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Kevin Kim
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4ca27d1475
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edited rv64i convig to support bit manipulation
|
2023-02-11 12:14:00 -08:00 |
|