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Author SHA1 Message Date
David Harris
f9bfca047b Merge pull request #147 from stineje/main 
Add correction for regression on Sail due to bug in recent release.  …
 2023-03-21 06:44:46 -07:00
James Stine
48a73e8ee8 Add correction for regression on Sail due to bug in recent release. This hash is known to work (verified by Stine/Thompson). May remove later if Sail ever gets fixed 2023-03-21 08:36:30 -05:00
David Harris
fecb282ff7 Commented out failing tests related to sip and sie 2023-03-21 05:51:43 -07:00
David Harris
df9ce03252 Renamed intdivrestoring to div 2023-03-21 05:51:02 -07:00
David Harris
718844012e Renamed intdivrestoring to div 2023-03-20 16:22:06 -07:00
David Harris
9e128f3926 Update LICENSE to Soldered 2023-03-20 16:05:36 -07:00
Kevin Kim
72a8b25272 formatting 2023-03-20 14:25:05 -07:00
Kevin Kim
2ad807728c more structural mux changes 2023-03-20 14:23:54 -07:00
Kevin Kim
4ecfa1bad3 added bitmanip 64 tests to updated regression script 
+ alu structural mux changes
 2023-03-20 14:19:39 -07:00
Kevin Kim
5056eb404c formatting 2023-03-20 13:09:49 -07:00
Kevin Kim
82d52f892b Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
David Harris
18737b58df formatting cleanup 2023-03-20 12:45:10 -07:00
David Harris
c3bf3f956e Merge pull request #144 from ross144/main 
Fixed bug in tool chain install script
 2023-03-20 10:40:44 -07:00
Ross Thompson
cfec2d0bcb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-20 11:52:18 -05:00
Ross Thompson
31e8ae1cd1 Fixed bug in the tool chain install script. 2023-03-20 11:52:10 -05:00
Kevin Kim
b394e343f6 format + min/max structural mux 2023-03-20 09:37:57 -07:00
David Harris
cd0240d938 Eliminate transitions to FLUSH and WRITEBACK in cachefsm for READ_ONLY_CACHE 2023-03-19 10:41:47 -07:00
David Harris
3fa570835a Ignore more log files left from ImperasDV 2023-03-19 10:26:53 -07:00
David Harris
85fc86729b Renamed coverage-exclusions-rv64gc 2023-03-19 10:26:09 -07:00
David Harris
4c6f539449 Removed flq from LLEN=64 2023-03-19 10:25:04 -07:00
David Harris
adbdc44f7b Improved coverage reporting 2023-03-19 10:24:35 -07:00
David Harris
ff22520d9e Added comments about PMP checker fixes when test cases will be ready to initialize PMP before entering user mode 2023-03-19 05:46:34 -07:00
David Harris
4cde207958 Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression. 2023-03-18 10:10:58 -07:00
David Harris
f53b2f6e1f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-18 09:24:37 -07:00
David Harris
6922298f21 Replaced FenceM with InvalidateICacheM for event counting of fence.i 2023-03-18 09:24:31 -07:00
Mike Thompson
255d5efb51 Merge pull request #140 from ross144/main 
Added notes on linux image generation
 2023-03-17 09:16:14 -04:00
Ross Thompson
318a9ec0f3 Merge branch 'main' of github.com:ross144/cvw into main 2023-03-17 00:48:04 -05:00
Ross Thompson
2150091e54 Added notes on how to run QEMU to generate linux image. 2023-03-17 00:47:52 -05:00
Mike Thompson
59985ff8a2 Merge pull request #139 from ross144/main 
Updates for book
 2023-03-14 15:44:59 -04:00
Ross Thompson
3d37d2769a Book updates. 2023-03-14 13:09:50 -05:00
Ross Thompson
36062e2758 Merge pull request #138 from eroom1966/main 
Fix MISA RO and UART addresses
 2023-03-13 23:32:56 -05:00
Ross Thompson
3cae6ca90f Updated NextAdr to NextSet. 2023-03-13 14:54:13 -05:00
Ross Thompson
c190444fa2 Updated CAdr to CacheSet. 2023-03-13 14:53:00 -05:00
Ross Thompson
a8d6c1cc2f More accurate c model gshare results. 2023-03-13 13:54:04 -05:00
Ross Thompson
2df36f23a7 On our way to finish the C reference data collection. 2023-03-13 13:32:09 -05:00
Ross Thompson
64502fa34c Merge branch 'main' of github.com:ross144/cvw into main 2023-03-13 13:30:49 -05:00
Ross Thompson
d2968376a9 Added reference data. 2023-03-13 13:30:43 -05:00
Ross Thompson
673044f923 Modified branch logger to indicate when the warmup period is done. 
The branch-predictor-simulator also changed to support this.
 2023-03-13 13:26:27 -05:00
eroom1966
9ddfe52c9f Fix MISA RO and UART addresses 
It appears on inspection that the MISA register is read only in Wally
In which case this has now also been set in the ImperasDV representation
Also the Addresss for the UART R/W privileges are corrected
 2023-03-13 11:07:19 +00:00
Ross Thompson
be05fd5297 Created script to batch processes all the embench branch outcomes into C model branch prediction rate. 2023-03-12 23:15:44 -05:00
Ross Thompson
d7066f72e9 Renamed script to parse branch.log 2023-03-12 22:40:59 -05:00
Ross Thompson
dea9dd962e Added script to separate branch.log into separate logs for each benchmark. 2023-03-12 17:58:36 -05:00
Ross Thompson
187752a339 Modified the branch log to include markers for the start and end of tests with exclusion of warmup period. 2023-03-12 17:15:56 -05:00
Ross Thompson
ada099c58b Changes BTA to BPBTA. 2023-03-12 14:36:46 -05:00
Ross Thompson
a5523400ae Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
Kevin Kim
0d0d3b981e more checks in bitmanip decode 2023-03-10 17:17:24 -08:00
Kevin Kim
9b4f3219db formatting 2023-03-10 14:32:01 -08:00
Kevin Kim
c380b0816d removed redundant convinvb signal 2023-03-10 14:18:24 -08:00
Kevin Kim
dcaf9de228 removed redundant condinvb mux 2023-03-10 14:17:38 -08:00
Ross Thompson
e4f35a768d Merge pull request #137 from davidharrishmc/dev 
Fixes to wally-batch for coverage
 2023-03-10 15:36:24 -06:00