Kip Macsai-Goren
cdb1a9e997
fixed write pmp csr test, added physical exe test, fixed instr fault return problem, general light cleanup
2021-07-23 15:27:54 -04:00
Kip Macsai-Goren
f02d52ce50
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-23 15:16:01 -04:00
bbracker
d7edfb7a70
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-23 14:00:52 -04:00
bbracker
71ef87bc55
testbench workaround for QEMU's SSTATUS XLEN bits
2021-07-23 14:00:44 -04:00
kipmacsaigoren
3bb6c8b32f
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
2021-07-23 11:57:58 -05:00
David Harris
5306d42bfe
Removed LEVELx states from HPTW
2021-07-23 08:11:15 -04:00
Ross Thompson
00f798b37e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 19:42:32 -05:00
Ross Thompson
32ec457e09
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
...
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Kip Macsai-Goren
ee1eef3620
include SFENCE.VMA in legal instructions
2021-07-22 20:24:24 -04:00
Kip Macsai-Goren
8b5b7f16cc
removed backups that are no longer needed
2021-07-22 20:23:17 -04:00
David Harris
427063ee05
Minor unpacking cleanup
2021-07-22 17:52:37 -04:00
Ross Thompson
007812dbdc
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
00858cd401
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 14:05:08 -05:00
Ross Thompson
936e034be9
Fixed bug with the itlb fault not dcache ptw ready state to ready state.
2021-07-22 14:04:56 -05:00
David Harris
0822d46e97
Move Z sign swapping out of unpacker
2021-07-22 14:32:38 -04:00
David Harris
85aaa4c6d7
Move Z=0 mux out of unpacker.
2021-07-22 14:28:55 -04:00
David Harris
c04f40d6e5
Move Z=0 mux out of unpacker.
2021-07-22 14:22:28 -04:00
David Harris
625d925369
Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.
2021-07-22 14:18:27 -04:00
David Harris
f4b45adf44
Simplify unpacker
2021-07-22 13:42:16 -04:00
David Harris
02f0c67e6f
Simplify unpacker
2021-07-22 13:40:42 -04:00
David Harris
2f23ca2b77
Removed Assumed1 from FPU interface
2021-07-22 13:04:47 -04:00
David Harris
926ffc8a15
Simplified interface to fclassify and fsgn (fixed)
2021-07-22 12:33:38 -04:00
David Harris
ae29eaa98d
Simplified interface to fclassify and fsgn
2021-07-22 12:30:46 -04:00
Ross Thompson
42fe5ceee3
Cleaned up icache and dcache.
2021-07-22 11:06:44 -05:00
Ross Thompson
89e22bc5e8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 10:38:24 -05:00
Ross Thompson
e907d57340
Tested all numbers of ways for dcache 1, 2, 4, and 8.
2021-07-22 10:38:07 -05:00
bbracker
9dcd5d3622
fix UART RX FIFO bug where tail pointer can overtake head pointer
2021-07-22 02:09:41 -04:00
bbracker
cdcf419147
make address translator signals visible in waveview
2021-07-21 20:07:49 -04:00
bbracker
70ef670da1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-21 20:07:03 -04:00
bbracker
3c6a1f8824
replace physical address checking with virtual address checking because address translator is broken
2021-07-21 19:47:13 -04:00
bbracker
b48d179c37
hardcoded hack to fix missing STVEC vector
2021-07-21 19:34:57 -04:00
Ross Thompson
1e88784bd4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
bb8ec549a7
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
aa624625bc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:39:07 -05:00
Ross Thompson
1f0ff804cf
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 14:56:30 -05:00
Ross Thompson
511c36fb1b
Improved address bus names and usages in the walker, dcache, and tlbs.
...
Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
abe57e3fd0
Added comment about better muxing.
2021-07-21 14:40:14 -05:00
Ross Thompson
3d79dc51bb
4 way set associative is now working.
2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
e25b4643a8
removed remaining 32 bit loads/stores with 64 bit ones.
2021-07-21 14:45:22 -04:00
Kip Macsai-Goren
e59490d032
Fixed TLB parameterization and valid bit flop to correctly do instr page faults
2021-07-21 14:44:43 -04:00
Katherine Parry
59f79722ab
FDIV and FSQRT work
2021-07-21 14:08:14 -04:00
bbracker
e8b966c5d1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-21 13:04:11 -04:00
bbracker
f7a61a5c73
progress on recovering from QEMU's errors
2021-07-21 13:00:32 -04:00
Ross Thompson
39fc9278ba
Fixed remaining bugs in 2 way set associative dcache.
2021-07-21 10:35:23 -05:00
Ross Thompson
ba3aed8760
Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux.
...
Also forgot to include cacheLRU.sv file.
2021-07-20 23:17:42 -05:00
Katherine Parry
61f81bb76e
FMA parameterized
2021-07-20 22:04:21 -04:00
Kip Macsai-Goren
53945adf4a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 21:04:53 -04:00
Kip Macsai-Goren
87e3f6c36d
light cleanup
2021-07-20 20:49:07 -04:00
Kip Macsai-Goren
f6bdb7b743
added new execution tests that should work with dcache memory non-syncness with 'real memory'. They make, but don't pass regression yet
2021-07-20 20:47:20 -04:00
Kip Macsai-Goren
e9fa2e18fd
added new executable test, cheange PTE to test library
2021-07-20 20:39:00 -04:00
