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Configurable RISC-V Processor
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32ec457e09
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Ross Thompson 32ec457e09 Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
riscv-coremark Updated location to find compiler for coremark 2021-07-16 19:13:18 -04:00
testsBP
wally-pipelined Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 2021-07-22 19:42:19 -05:00
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.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
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README.md

riscv-wally

Configurable RISC-V Processor