981 Commits

Author	SHA1	Message	Date
Katherine Parry	09f51871c5	lint warnings fixed	2021-10-12 09:45:02 -07:00
Katherine Parry	4ea56ac68b	some fpu lint warnings fixed - still working on it	2021-10-11 18:32:03 -07:00
Shreya Sanghai	51185478df	made redunantmul generate DW02_multp for synopsys sythnesis	2021-10-11 11:54:39 -07:00
Shreya Sanghai	295a3c7af2	actually added redundant mul	2021-10-11 11:29:13 -07:00
Shreya Sanghai	324230e2f9	added redundant multiplier	2021-10-11 11:20:12 -07:00
David Harris	fc39f77cba	Starting to optimize multiplier	2021-10-11 11:06:07 -07:00
David Harris	8a64675b02	intdiv cleanup	2021-10-11 08:14:21 -07:00
David Harris	a8ce4568aa	Divider FSM simplification	2021-10-10 22:24:14 -07:00
David Harris	a077735ecc	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
David Harris	266c706804	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-10 12:26:15 -07:00
David Harris	77f1ae54d8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-10 12:25:11 -07:00
bbracker	8eff03bf1a	simplify flopenrc's that didn't actually need to be flopenrc's	2021-10-10 12:25:05 -07:00
David Harris	93e6ec96a7	Divider cleanup	2021-10-10 12:24:44 -07:00
David Harris	6d2d93deeb	Simplifying divider FSM	2021-10-10 12:21:43 -07:00
David Harris	2d09994a91	Simplifying divider FSM	2021-10-10 12:21:36 -07:00
David Harris	644af40855	Moved & ~StallM from FSM into DivStartE	2021-10-10 11:49:32 -07:00
David Harris	e93014d6d8	Moved divide iteration register names to M stage	2021-10-10 11:30:53 -07:00
David Harris	e8d013b106	Simplified remainder for divide by 0	2021-10-10 11:20:07 -07:00
David Harris	94fd682cdc	divider control signal simplificaiton	2021-10-10 10:55:02 -07:00
David Harris	bfe8bf3855	Removed negedge flops from divider	2021-10-10 10:41:13 -07:00
David Harris	99fd79c20b	Simplified divider sign handling	2021-10-10 08:35:26 -07:00
David Harris	eaa8be14b9	renamed DivStart	2021-10-10 08:32:04 -07:00
David Harris	5cb30164d4	renamed DivSigned	2021-10-10 08:30:19 -07:00
Katherine Parry	44b023ace1	FMA matches diagram and lint warnings fixed	2021-10-09 17:38:10 -07:00
kipmacsaigoren	086e6d130a	rename adder in fpu for synthesis	2021-10-08 17:47:54 -05:00
kipmacsaigoren	8e35701103	Merging new changes into the old one's I've made in the OKstate servers	2021-10-08 17:47:11 -05:00
Kip Macsai-Goren	3623dfa51e	removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.	2021-10-08 15:33:18 -07:00
kipmacsaigoren	3103b78493	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-08 12:01:44 -05:00
bbracker	25e0745a6a	fix div restarting bug	2021-10-07 18:55:00 -04:00
kipmacsaigoren	086a0234ba	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-06 11:52:34 -05:00
James E. Stine	b90d7b8083	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
kipmacsaigoren	4a9dd49785	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-04 12:28:03 -05:00
David Harris	cc41d40d61	Divider cleaup	2021-10-03 11:22:34 -04:00
David Harris	3398328bf1	Divider cleanup	2021-10-03 11:16:48 -04:00
David Harris	9809e57d0c	Replacing XE and DE with SrcAE and SrcBE in divider	2021-10-03 11:11:53 -04:00
David Harris	bf0061be66	Reduced cycle count for DIVW/DIVUW by two	2021-10-03 09:42:22 -04:00
David Harris	bd61ec544b	Divider comments cleanup	2021-10-03 01:12:40 -04:00
David Harris	30ec68d567	Parameterized number of bits per cycle for integer division	2021-10-03 01:10:15 -04:00
David Harris	078ddfd341	Divider cleanup	2021-10-03 00:41:41 -04:00
David Harris	8f36297569	Added suffixes to more divider signals	2021-10-03 00:32:58 -04:00
David Harris	dcbbee6623	More divider cleanup	2021-10-03 00:20:35 -04:00
David Harris	6aa2521959	Eliminated extra inversion for subtraction in divider	2021-10-03 00:10:12 -04:00
David Harris	371f9d9a4a	Added more pipeline stage suffixes to divider	2021-10-03 00:06:57 -04:00
David Harris	24bb3f4baf	Added more pipeline stage suffixes to divider	2021-10-02 22:54:01 -04:00
David Harris	3441991d93	Divider mostly cleaned up	2021-10-02 21:10:35 -04:00
David Harris	67690c2ed7	Partial divider cleanup 3	2021-10-02 21:00:13 -04:00
David Harris	775520c05a	Partial divider cleanup 2	2021-10-02 20:57:54 -04:00
David Harris	fe69513bb7	Partial divider cleanup	2021-10-02 20:55:37 -04:00
David Harris	a86ce5cd37	Divider code cleanup	2021-10-02 10:41:09 -04:00
David Harris	d532bde931	Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division	2021-10-02 10:36:51 -04:00