Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
23194c0308
fix parseState.py to correctly take in PMPCFG
2021-11-24 16:52:51 -08:00
bbracker
4e96d0f1db
add checkpoints to regression
2021-11-20 19:42:53 -08:00
bbracker
e5d3416258
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-19 20:25:06 -08:00
bbracker
713aa7faac
automatic bug finder script
2021-11-19 20:25:00 -08:00
bbracker
c07caf4fe8
increase buildroot progress expecttions; increase timeout to 20 hours
2021-11-19 12:52:11 -08:00
David Harris
402b473dbb
CoreMark testing
2021-11-18 16:14:25 -08:00
David Harris
0a281a06e0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:28:33 -08:00
Kevin Kim
6437c04074
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 12:18:25 -08:00
Kevin Kim
38437c664e
root level makefile added
2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
7a8c21e71f
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
f4c221f20a
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
David Harris
c610be25a7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
Ross Thompson
7497422667
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
David Harris
570f24a9e4
bringing Coremark back to life
2021-11-10 12:43:31 -08:00
Kevin Kim
7cb8b76ef6
Makefile added in regression directory:
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-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
f6a555009b
increase expectations for buildroot and timeout count
2021-11-06 14:57:29 -07:00
bbracker
0c7681b942
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
David Harris
d7f0abca5a
Add3d wally32i test
2021-11-01 13:17:49 -07:00
David Harris
60573b92b2
Adding custom Wally test infrastructure
2021-11-01 08:48:46 -07:00
bbracker
fe2cda493c
fix buildroot graphical sim
2021-10-31 18:33:43 -07:00
David Harris
247f247ad3
tesgen cleanup, added riscv-arch-test D tests
2021-10-29 22:31:48 -07:00
David Harris
5783e47e1a
Changes for floating point sims
2021-10-27 10:37:35 -07:00
David Harris
b7b6d6f23f
removed unused signal from wave.do
2021-10-26 09:02:22 -07:00
bbracker
66e53929ce
adapt testbench linux to use reset_ext
2021-10-25 13:26:44 -07:00
Ross Thompson
81054d9168
Fixed issue with dtim (fpga) external abhlite select not triggering.
...
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
bbracker
39efadf2cf
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-25 12:25:37 -07:00
bbracker
8c4e6baf48
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
2021-10-25 12:25:32 -07:00
Ross Thompson
32f0b97cd3
Updated uncore to use sdc.
...
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
David Harris
2bf51362e2
Added synchronizer to reset
2021-10-25 10:05:41 -07:00
bbracker
13763b002a
switch linux graphical sim over to Ross's waves
2021-10-24 18:39:23 -07:00
bbracker
c0a7b12f94
or actually needed to reduce expectations of buildroot
2021-10-24 06:59:34 -07:00
bbracker
d3969bb1ba
increase regression's expectations of buildroot
2021-10-24 06:50:22 -07:00
bbracker
e0b6566cbd
buildroot do scripts now compile flops
2021-10-23 23:14:59 -07:00
bbracker
de6a52f6eb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2
add option for regression to do a partial execution of buildroot
2021-10-23 13:17:30 -07:00
David Harris
200eb453fb
wrapping up lint cleanup; many unused signals removed
2021-10-23 12:15:14 -07:00
David Harris
ac1b1bfbb6
update scripts for handling src/*/* subdirectories
2021-10-23 08:54:29 -07:00
David Harris
e2e950ac0f
Cleaned up LINT erors
2021-10-23 06:28:49 -07:00
David Harris
3249d65209
Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
2021-10-23 06:15:26 -07:00
Ross Thompson
de4ea16d32
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
Ross Thompson
d11136c406
Fixed bug with the external memory region selection.
...
Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
James E. Stine
1dba57dce7
Update to fpdivsqrt to go on posedge as it should. Also an update to
...
individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
4abc6fc915
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Ross Thompson
f6c6cb9ed2
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
bfe633d087
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
David Harris
4139f27d10
Divider FSM simplification
2021-10-10 22:24:14 -07:00
David Harris
75c17dc372
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
bbracker
13352eccda
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 13:12:44 -07:00
bbracker
161767cddd
make regression expect what buildroot is actually able to reach
2021-10-10 13:12:36 -07:00
David Harris
c2bb0324c6
Removed negedge flops from divider
2021-10-10 10:41:13 -07:00
bbracker
55f6584e62
update wave-do
2021-10-07 19:16:52 -04:00
James E. Stine
199ce88b39
Add generic wave command file
2021-10-06 13:17:49 -05:00
James E. Stine
93668b5185
Update to testbench for FP stuff
2021-10-06 13:16:38 -05:00
Ross Thompson
047bbcf3d7
updated fpga wavefile.
2021-10-03 12:14:22 -05:00
Ross Thompson
e9135f1fd5
Added fpga wave file.
2021-10-03 11:56:11 -05:00
David Harris
78eba19a1f
Replacing XE and DE with SrcAE and SrcBE in divider
2021-10-03 11:11:53 -04:00
David Harris
c690a863b5
Added suffixes to more divider signals
2021-10-03 00:32:58 -04:00
David Harris
b3bded9e6c
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
David Harris
f913305993
Partial divider cleanup
2021-10-02 20:55:37 -04:00
David Harris
4926ae343a
Divider code cleanup
2021-10-02 10:13:49 -04:00
David Harris
852eb24731
Moved negating divider otuput to M stage
2021-10-02 10:03:02 -04:00
Ross Thompson
fca9b9e593
Movied tristate to test bench level.
2021-09-30 11:27:42 -05:00
Ross Thompson
cefbcd1b0c
Partially sd card read on fpga.
2021-09-30 11:23:09 -05:00
David Harris
42d573be57
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
Ross Thompson
7ca801113e
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
Ross Thompson
c917f14b6b
Almost done writting driver for flash card reader.
2021-09-25 19:05:07 -05:00
Ross Thompson
69674f272a
We now have a rough sdc read routine.
2021-09-25 17:51:38 -05:00
Ross Thompson
23425c8d71
Write of the SDC address register is correct. The command register is not yet working.
...
The root problem is the command register needs to be reset at the end of the SDC transaction.
2021-09-24 18:48:11 -05:00
Ross Thompson
86524a5f64
Now have software interacting with the initialization and settting the address register.
2021-09-24 18:30:26 -05:00
Ross Thompson
44196af61a
Have program which checks for sdc init and issues read, but read done is
...
not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
80e37d2291
Added SDC defines to each config mode.
...
Added sd_top which is the sd card reader.
2021-09-24 12:24:30 -05:00
Ross Thompson
c644e940c2
Updated Imperas test bench to work with the SDC reader.
2021-09-24 11:22:54 -05:00
Ross Thompson
221dbe92b2
Fixed the amo on dcache miss cpu stall issue.
2021-09-17 22:15:03 -05:00
Ross Thompson
e16c27225b
Finished adding the d cache flush. Required ensuring the write data, address, and size are
...
correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Ross Thompson
0b1e59d075
Updated Dcache to fully support flush. This appears to work.
...
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
cae350abb7
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
bbracker
a158558b83
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-15 17:31:11 -04:00
bbracker
ff5379fd95
fix regression
2021-09-15 17:30:59 -04:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
9fa048980d
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
David Harris
7be1160a48
Cleaned up wally-arch test scripts
2021-09-13 00:02:32 -04:00
David Harris
12bd351edf
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6550f38af9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
Ross Thompson
a15d6c1c96
Slight modification to wave file.
2021-09-08 10:40:46 -05:00
bbracker
bb84354a47
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
bbracker
da9a366d20
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
Ross Thompson
05455f8392
Changed name of memory in icache.
2021-09-06 20:54:52 -05:00
bbracker
c463f177e9
restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair
2021-09-04 19:45:04 -04:00
Ross Thompson
2968623f9a
Partial multiway set associative icache.
2021-08-30 10:49:24 -05:00
Ross Thompson
6a9fa2fae3
Fixed bugs I introduced to the icache.
2021-08-27 15:00:40 -05:00
Ross Thompson
96cbd8e785
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
...
One downside is it increases the icache complexity. However it also fixes an untested bug. If a region
was uncacheable it would have been possible for the request to be made multiple times. Now that is
not possible. Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
Ross Thompson
d6ff89b7e6
Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
2021-08-26 15:43:02 -05:00
Ross Thompson
e4bbd3bbc7
Converted the icache type from logic to state type.
2021-08-26 10:41:42 -05:00
Ross Thompson
0530047f53
Moved dcache fsm to separate module.
2021-08-25 21:37:10 -05:00
Ross Thompson
d23b860c96
Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
...
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
2021-08-25 21:09:42 -05:00
Ross Thompson
e9a1dc90f6
Removed generate around the dcache memories.
2021-08-25 13:27:26 -05:00
