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Updated Imperas test bench to work with the SDC reader.

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This commit is contained in:
Ross Thompson 2021-09-24 11:22:54 -05:00
parent fea439b84d
commit c644e940c2
9 changed files with 23 additions and 24 deletions
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25
wally-pipelined/regression/wave.do
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@ -516,25 +516,10 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
add wave -noupdate -color Gold /testbench/dut/hart/lsu/dcache/subwordread/offset0
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3
add wave -noupdate /testbench/dut/hart/ExceptionM
add wave -noupdate /testbench/dut/hart/PendingInterruptM
add wave -noupdate /testbench/dut/hart/TrapM
add wave -noupdate /testbench/dut/hart/ifu/icache/CompressedF
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
add wave -noupdate /testbench/dut/hart/ifu/PCPFmmu
add wave -noupdate /testbench/dut/hart/ifu/PCPF
add wave -noupdate /testbench/dut/hart/ifu/PCF
add wave -noupdate /testbench/dut/hart/ifu/immu/Translate
add wave -noupdate /testbench/dut/hart/ifu/icache/FinalInstrRawF
add wave -noupdate /testbench/dut/hart/ifu/icache/StallF
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheMemReadData
add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn
add wave -noupdate -expand -group SDC -color Gold /testbench/dut/uncore/sdc/SDC/CurrState
add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/HCLK
add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/CLKGate
add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/SDCCLK
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 6} {122378 ns} 0}
quietly wave cursor active 1
@ -552,4 +537,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {122227 ns} {122479 ns}
WaveRestoreZoom {122134 ns} {122622 ns}

2
wally-pipelined/src/sdc/SDC.sv
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@ -25,7 +25,7 @@
`include "wally-config.vh"
`define SDCCLKDIV 2
`define SDCCLKDIV 8'd2
module SDC
(input logic HCLK,

2
wally-pipelined/src/sdc/tb/run_tb.do
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@ -6,7 +6,7 @@ if [file exists work] {
}
vlib work
vlog +incdir+../../../config/rv64ic +incdir+../../../config/shared ../../../testbench/common/*.sv ../../*/*.sv sd_top_tb.sv sdModel.sv sd_crc_7.sv sd_crc_16.sv -suppress 2583
vlog +incdir+../../../config/rv64ic +incdir+../../../config/shared ../../../testbench/common/*.sv ../../*/*.sv sd_top_tb.sv -suppress 2583
vopt -fsmdebug +acc -gDEBUG=1 work.sd_top_tb -o workopt
vsim workopt -fsmdebug

6
wally-pipelined/src/uncore/uncore.sv
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@ -129,8 +129,10 @@ module uncore (
// interrupt to PLIC
.SDCIntM
);
end else begin : uart
assign UARTSout = 0; assign UARTIntr = 0;
end else begin : sdc
assign SDCCLK = 0;
assign SDCCmdOut = 0;
assign SDCCmdOE = 0;
end
endgenerate

0
wally-pipelined/src/sdc/tb/sdModel.sv → wally-pipelined/testbench/common/sdModel.sv
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0
wally-pipelined/src/sdc/tb/sd_crc_16.sv → wally-pipelined/testbench/common/sd_crc_16.sv
View File

0
wally-pipelined/src/sdc/tb/sd_crc_7.sv → wally-pipelined/testbench/common/sd_crc_7.sv
View File

0
wally-pipelined/src/sdc/tb/sd_defines.h → wally-pipelined/testbench/common/sd_defines.h
View File

12
wally-pipelined/testbench/testbench-imperas.sv
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@ -566,6 +566,10 @@ string tests32f[] = '{
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
logic UARTSin, UARTSout;
logic SDCCLK;
tri1 SDCCmd;
tri1 [3:0] SDCDat;
// instantiate device to be tested
assign GPIOPinsIn = 0;
assign UARTSin = 1;
@ -582,6 +586,14 @@ string tests32f[] = '{
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// SD card model
sdModel sdcard
(.sdClk(SDCCLK),
.cmd(SDCCmd),
.dat(SDCDat));
// initialize tests
localparam integer MemStartAddr = `TIM_BASE>>(1+`XLEN/32);
localparam integer MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32);