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58 Commits

Author SHA1 Message Date
David Harris
9dd3857c26 Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
bbracker
17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
7e41b17e65 restructured so that pma/pmp are a part of mmu 2021-06-04 17:05:07 -04:00
Thomas Fleming
980c00fa64 Clean up MMU code 2021-05-14 07:12:32 -04:00
bbracker
535046e494 small synthesis fixes 2021-05-04 15:21:01 -04:00
Thomas Fleming
00c3b5a033 Remove remnants of InstrReadC 2021-05-03 17:36:25 -04:00
Thomas Fleming
94d734cca9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-05-03 14:02:19 -04:00
bbracker
9c08ce5359 rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Thomas Fleming
e091f430e0 Clean up PMA checker and begin PMP checker 2021-04-29 02:20:39 -04:00
Ross Thompson
44d28dbd1c Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
8d77012995 progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Thomas Fleming
6f23858609 Fix HSIZE and HBURST signal widths in PMA checker 2021-04-23 20:11:43 -04:00
Ross Thompson
d7fea1ba3c almost working icache. 2021-04-23 16:47:23 -05:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925 Yes. The hack to not repeat the d memory operation fixed this issue. 2021-04-22 15:22:56 -05:00
Thomas Fleming
74fb1dccad Prepare to squash bad ahb accesses 2021-04-22 15:36:45 -04:00
Thomas Fleming
e7822ce20c Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Thomas Fleming
4d4ca24640 Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
Thomas Fleming
70c801331a Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
Thomas Fleming
bb2d433971 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
ae888b5705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Teo Ene
0bffac2c74 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Thomas Fleming
e04ad8f304 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Jarred Allen
73d4dd8c15 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Jarred Allen
fdecd6c56c Clean up some stuff 2021-03-25 13:04:54 -04:00
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Thomas Fleming
89a2fe5741 Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
bbracker
eea7e2e47e first pass at PLIC interface 2021-03-22 10:14:21 -04:00
bbracker
df51d9908d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
Thomas Fleming
062c4d40da Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
David Harris
d4e84c58ed 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Thomas Fleming
e57b6cf18c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
fe4d288589 Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Noah Boorstin
2d1f63b590 change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
David Harris
52d4a04eb0 Created atomic test vector and directories 2021-03-08 09:38:55 -05:00
Thomas Fleming
e48dc38869 Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Thomas Fleming
692d4152fa Begin hardware page table walker 2021-03-03 17:13:45 -05:00
David Harris
0258901865 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
David Harris
225102047a Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
38b8cc652c All tests passing with bus interface 2021-02-24 07:25:03 -05:00
David Harris
f372e2b8e8 Debugging Bus interface 2021-02-22 13:48:30 -05:00