Ross Thompson
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7d6093b302
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Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
About 149307ns of simulation run.
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2021-02-18 21:32:15 -06:00 |
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Ross Thompson
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bbe0db3ebe
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Integrated the branch predictor into the hardward. Not yet working.
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2021-02-17 22:19:17 -06:00 |
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Ross Thompson
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ca546beaf8
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We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
This is not yet tested but the system verilog does compile.
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2021-02-15 14:51:39 -06:00 |
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Ross Thompson
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935e9e59e9
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added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
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2021-02-14 15:13:55 -06:00 |
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Ross Thompson
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8486f426b7
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The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
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2021-02-14 11:06:31 -06:00 |
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