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0678e70b4b
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317 Commits

Author SHA1 Message Date
Ross Thompson
0678e70b4b Merge branch 'imperas' 2023-01-31 12:46:22 -06:00
Ross Thompson
7a4218788c Imperas found a real bug in virtual memory. 
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.

Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
 2023-01-30 11:47:51 -06:00
Ross Thompson
a9902337cf Merge branch 'main' of https://github.com/openhwgroup/cvw 
This merges the branch predictor improvements into the main repo.
 2023-01-29 15:24:20 -06:00
Ross Thompson
9e3074689d Fixed another bug with the speculative gshare with instruction class prediction. 2023-01-29 00:33:40 -06:00
Ross Thompson
684a7214cb Added another performance counter to track overall branch miss-predictions. 2023-01-28 17:50:46 -06:00
Ross Thompson
3f25123c63 Possible fix for speculative gshare. 2023-01-28 16:14:19 -06:00
Ross Thompson
6c86c0389c Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction. 2023-01-27 11:34:45 -06:00
David Harris
4744996282 Removed suggestion about make allclean 2023-01-27 05:57:05 -08:00
Ross Thompson
bbb47fc943 Changed the performance counters to track different data. 
Now rather than tracking jump(r) we track jump(r) and taken branches.
 2023-01-26 13:21:28 -06:00
Ross Thompson
43d4ac1c7b Intermediate commit. Passes regression tests, but RAS is not correct. 2023-01-25 19:39:18 -06:00
Ross Thompson
0b9f787635 Improved RAS again. 2023-01-25 17:10:52 -06:00
David Harris
c2f7f7324d test 2023-01-20 15:23:38 -08:00
Ross Thompson
11c44006c4 Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
eroom1966
43d5769bd9 update 2023-01-19 13:29:46 +00:00
eroom1966
8dea3491a3 Partial fix for misaligned LD/ST 2023-01-18 17:11:39 +00:00
eroom1966
0ccab9accc changes made with Ross 2023-01-18 16:46:48 +00:00
eroom1966
247879e7c7 add im flags for compressed disass 2023-01-18 13:37:28 +00:00
eroom1966
68af12ece1 refer to correct path 2023-01-18 13:26:07 +00:00
Ross Thompson
8f5b5e0989 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
fd52915f3c Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
b2676e1dd4 Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
sarah-harris
9fb7c8132a Changing signal name to ImmExtD/E to match figures 
Changing signal name:
ExtImmD/E -> ImmExtD/E

to match figures.
 2023-01-17 06:33:58 -08:00
eroom1966
2ead2cdaf4 Code refactor and addition of rvvi interface 2023-01-17 12:47:38 +00:00
David Harris
3e17bfbc53 Removed Imperas tests from regression 2023-01-16 07:01:07 -08:00
David Harris
fdb839edcb Makefile and setup cleanup 2023-01-15 20:27:12 -08:00
Ross Thompson
9a180f88f7 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
8ee80c5d54 Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
97feea2f48 Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
a35fb3addd core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
Ross Thompson
e34f80db2f More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
Ross Thompson
3637067ace Officially added global history with speculation to types of branch predictors. 2023-01-05 14:04:09 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
David Harris
214ef40b1c Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
Ross Thompson
424012ce97 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
66510f38af reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
David Harris
fe5b9081d9 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
a185f563f2 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
Ross Thompson
6b105bd217 Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
942acb354e Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
7a0b3d4fc6 Wavefile updates. 2022-12-22 19:45:02 -06:00
Ross Thompson
968e174d68 Changes to wave file. 2022-12-21 08:41:47 -06:00
David Harris
88ee834c97 Converted tvecmux to structural 2022-12-20 16:24:04 -08:00
David Harris
9133b3a7a4 FPU remove unused signals 2022-12-20 14:43:30 -08:00
Ross Thompson
c3b77926d5 I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
9d1cb9337e Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
Ross Thompson
5acdf541b9 Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back. 2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348 At long last found the subtle bug in the LRU. 
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
 2022-12-17 10:03:08 -06:00
Ross Thompson
3132246a46 Oups found a bug with the new flush cache states. 2022-12-16 16:22:40 -06:00
Ross Thompson
91e64a0d67 Cleanup of cache flush fsm enhancement. 2022-12-16 15:36:53 -06:00