bbracker
59b2a49854
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
Ross Thompson
8dfbf60b67
AMO and LR/SC instructions now working correctly.
...
Page table walking is not working.
2021-06-25 15:42:07 -05:00
Ross Thompson
a4266c0136
Some progress. Had to change how the page table walker got it's ready.
2021-06-25 15:07:41 -05:00
Ross Thompson
9fd1761fd6
Working through a combo loop.
2021-06-25 14:49:27 -05:00
Ross Thompson
17636b3293
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
bbracker
9927f771cc
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
2694a7a43f
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
bbracker
4e09793a9a
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
aac9b46a1f
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
1485d29dde
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
389b9a510e
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Katherine Parry
bc8d660bc5
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
ced5039776
Revert "fixed forwarding"
...
This reverts commit 0f4a4a6ade
2021-06-24 17:39:37 -04:00
Ross Thompson
d8183e59e4
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
732551d6be
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Ross Thompson
0377d3b2c9
Progress.
2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade
fixed forwarding
2021-06-24 11:20:21 -04:00
bbracker
3ae4cd951a
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
3d6b422e34
regression can overcome the fact that buildroots UART prints stuff
2021-06-24 02:00:01 -04:00
bbracker
409a73604c
whoops meant to remove notifications from busybear, not buildroot
2021-06-24 01:54:46 -04:00
bbracker
55cf205222
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
b84419ff4e
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
547bf1d0af
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
abe5bc90bf
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Katherine Parry
44af47608c
fpu clean-up
2021-06-23 16:42:40 -04:00
Ross Thompson
d5063bee7d
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
5de7a46237
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
718630c378
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
4189b2d4a7
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
1972d83002
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6dc54acde8
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
ae0fa90450
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
b43a8885cd
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Ross Thompson
e7d8d0b337
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-22 15:47:16 -05:00
Katherine Parry
9eb6eb40bf
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
d6c5c61b59
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
b78c09baed
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
852bb9296f
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
bbracker
56b0d4d016
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
Ross Thompson
03084a4128
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
Ross Thompson
8ec5b0c4f1
Improved some names in icache.
2021-06-21 16:40:37 -05:00
David Harris
82515862e3
Commented out 100k tests to improve speed
2021-06-21 01:43:18 -04:00
David Harris
29ad38fb9e
Added Physical Address and Size to PMA Checker/MMU
2021-06-21 01:27:02 -04:00
David Harris
aef408af58
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
0a59b006ab
Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
2021-06-20 22:59:04 -04:00
bbracker
83a1f29c37
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
bbracker
5afad80432
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 22:29:40 -04:00
bbracker
665a67f442
linux actually uses FPU now!
2021-06-20 22:29:21 -04:00
Katherine Parry
26bad083ad
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-20 20:24:09 -04:00
bbracker
1f2a967e0f
read from MSTATUS workaround because QEMU has incorrect MSTATUS
2021-06-20 10:11:39 -04:00
bbracker
2611d214a6
testbench update b/c QEMU extends 32b CSRs to 64b
2021-06-20 09:24:19 -04:00
bbracker
7aa2f0d953
make xCOUNTEREN what buildroot expects it to be
2021-06-20 09:22:31 -04:00
bbracker
6e9c6e3e6a
whoops wavedo typo
2021-06-20 05:36:54 -04:00
bbracker
9469367da3
make buildroot ignore SSTATUS because QEMU did not originally log it
2021-06-20 05:31:24 -04:00
bbracker
78f4703dc9
MSTATUS workaround
2021-06-20 04:48:09 -04:00
bbracker
927d99cf3b
workaround for ignoring MTIME
2021-06-20 02:26:39 -04:00
bbracker
52fb630379
remove lingering busybear stuff from buildroot do files
2021-06-20 00:50:53 -04:00
bbracker
124ef980e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 00:40:44 -04:00
bbracker
3e32ba3684
make buildroot waves only turn on after a user-specified point
2021-06-20 00:39:30 -04:00
Ross Thompson
bb756849a7
Revert "Icache now uses physical lenght bits rather than XLEN."
...
This reverts commit d4de8a54a2
2021-06-19 08:58:34 -05:00
Ross Thompson
e4c932265d
Revert "Improved some names in icache."
...
This reverts commit 22ea801edb
2021-06-19 08:58:32 -05:00
bbracker
ebe893b70c
change buildroot config to use relative path for testvectors
2021-06-18 22:28:07 -04:00
bracker
3d99c9c2c4
gitignore merge
2021-06-18 21:12:05 -05:00
bracker
ed75172f21
handle tera usernames more gracefully
2021-06-18 21:11:14 -05:00
bbracker
10ca2ac5bc
on-Tera solution for sym linking to linux testvectors
2021-06-18 22:01:18 -04:00
bracker
a9f9ef1180
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 20:41:01 -05:00
bracker
8a8b0dcfd7
script support for copying large files from tera
2021-06-18 20:40:19 -05:00
bbracker
f394b91515
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 17:37:49 -04:00
bbracker
f84a689c19
fixed PCtext error by using blocking assignments
2021-06-18 17:37:40 -04:00
Ross Thompson
0250d52ae3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-18 12:24:42 -05:00
Ross Thompson
22ea801edb
Improved some names in icache.
2021-06-18 12:22:41 -05:00
Ross Thompson
d4de8a54a2
Icache now uses physical lenght bits rather than XLEN.
2021-06-18 12:02:59 -05:00
David Harris
43bc17350b
Restored wally-busybear testbench now that graphical sim is working
2021-06-18 12:36:25 -04:00
bbracker
958f60c704
restore graphical buildroot sim
2021-06-18 11:58:16 -04:00
Abe
892c14430b
Updated directory coremark_bare's wally-config file to define PMP_ENTRIES
2021-06-18 11:46:25 -04:00
bbracker
1e93bbd119
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 09:49:37 -04:00
bbracker
72f1e3eab6
buildroot added to regression because it passes regression
2021-06-18 09:49:30 -04:00
David Harris
21a55458ca
Made MemPAdrM and related signals PA_BITS wide
2021-06-18 09:36:22 -04:00
David Harris
a3f3533cce
Changed physical addresses to PA_BITS in size in MMU and TLB
2021-06-18 09:11:31 -04:00
bbracker
0980ce92bc
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 08:15:40 -04:00
bbracker
8ae333a6b2
remove unused testbench-busybear.sv
2021-06-18 08:15:19 -04:00
David Harris
cc78504ae4
Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX
2021-06-18 08:13:15 -04:00
David Harris
72d8d34e3c
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
David Harris
e03912f64c
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
David Harris
8357b14957
Further cleaning of PMA checker
2021-06-17 22:27:39 -04:00
David Harris
91a13999a9
Added SUPPORTED to each peripheral in each config file
2021-06-17 21:36:32 -04:00
David Harris
5e7ed4bd88
added inputs to pmaadrdec
2021-06-17 18:54:39 -04:00
David Harris
09c5e27853
Started simplifying PMA checker
2021-06-17 16:28:06 -04:00
bbracker
076469230f
added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
2021-06-17 12:09:10 -04:00
bbracker
db0abfd36d
enable TIME CSR for 32 bit mode as well
2021-06-17 11:34:16 -04:00
bbracker
7d1469a06c
provide time and timeh CSRs based on CLINT's counter
2021-06-17 08:38:30 -04:00
bbracker
832e4fc7e3
making linux waveforms more useful
2021-06-17 08:37:37 -04:00
bbracker
0647094e73
PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable
2021-06-17 05:19:36 -04:00
bbracker
e93e528aa1
changed parsedCSRs2] to parsedCSRs
2021-06-17 05:18:14 -04:00
bbracker
902fd85e9c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-17 00:50:14 -04:00
bbracker
7de660f8aa
still not sure if QEMU workaround is correct, but here is all linux progress so far
2021-06-17 00:50:02 -04:00
bbracker
7a652139b5
mcause test fixes and s-mode interrupt bugfix
2021-06-16 17:37:08 -04:00
bbracker
3f6b018f66
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-16 16:17:53 -04:00
bracker
d1bab12e1e
chmod +x'd privileged testgen scripts
2021-06-16 10:28:57 -05:00
