From 2ca897620fd4a0bea56b6753ef53b53c17eed021 Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Mon, 16 May 2022 15:39:15 +0000 Subject: [PATCH 01/38] tuning modules for ppa --- pipelined/src/ppa/ppa.sv | 29 ++++++++++- synthDC/Synopsys_stack_trace_52064.txt | 17 +++++++ synthDC/Synopsys_stack_trace_55441.txt | 17 +++++++ synthDC/crte_000052064.txt | 67 ++++++++++++++++++++++++++ synthDC/crte_000055441.txt | 67 ++++++++++++++++++++++++++ synthDC/ppa.py | 11 +++-- synthDC/ppaData.csv | 5 ++ 7 files changed, 208 insertions(+), 5 deletions(-) create mode 100644 synthDC/Synopsys_stack_trace_52064.txt create mode 100644 synthDC/Synopsys_stack_trace_55441.txt create mode 100644 synthDC/crte_000052064.txt create mode 100644 synthDC/crte_000055441.txt diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 1ce9b4496..d1ed9d500 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -180,12 +180,39 @@ module ppa_shiftleft #(parameter WIDTH=32) ( assign y = a << amt; endmodule +module ppa_shifter_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter_32 #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, input logic Right, Arith, W64, output logic [WIDTH-1:0] Y); + ppa_shifter #(WIDTH) sh (.*); +endmodule + +module ppa_shifter_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + +module ppa_shifter #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + logic [2*WIDTH-2:0] z, zshift; logic [$clog2(WIDTH)-1:0] amttrunc, offset; @@ -264,7 +291,7 @@ module ppa_prioriyencoder #(parameter N = 8) ( end endmodule -module ppa_decoder ( +module ppa_decoder #(parameter N = 8) ( input logic [$clog2(N)-1:0] a, output logic [N-1:0] y); always_comb begin diff --git a/synthDC/Synopsys_stack_trace_52064.txt b/synthDC/Synopsys_stack_trace_52064.txt new file mode 100644 index 000000000..f62c1acfc --- /dev/null +++ b/synthDC/Synopsys_stack_trace_52064.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 52064 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_55441.txt b/synthDC/Synopsys_stack_trace_55441.txt new file mode 100644 index 000000000..0e7a3c988 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_55441.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 55441 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/crte_000052064.txt b/synthDC/crte_000052064.txt new file mode 100644 index 000000000..2eef81a43 --- /dev/null +++ b/synthDC/crte_000052064.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +52064 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Thu May 12 21:44:48 UTC 2022 (1652391888) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 dest +0x00000000 15204364 harris 644 790528 2 dest +0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000055441.txt b/synthDC/crte_000055441.txt new file mode 100644 index 000000000..7bd6f6855 --- /dev/null +++ b/synthDC/crte_000055441.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +55441 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Thu May 12 21:47:47 UTC 2022 (1652392067) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 dest +0x00000000 15204364 harris 644 790528 2 dest +0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/ppa.py b/synthDC/ppa.py index 91b21d880..4d1657771 100755 --- a/synthDC/ppa.py +++ b/synthDC/ppa.py @@ -4,17 +4,19 @@ import subprocess from multiprocessing import Pool import csv import re -import matplotlib.pyplot as plt -import numpy as np +# import matplotlib.pyplot as plt +# import numpy as np +print("hi") def run_command(module, width, freq): command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq) subprocess.Popen(command, shell=True) -widths = ['32'] +widths = ['16'] modules = ['shifter'] -freqs = ['10', '4000', '5000', '6000'] +freqs = ['10'] + LoT = [] for module in modules: @@ -24,6 +26,7 @@ for module in modules: pool = Pool() pool.starmap(run_command, LoT) +pool.close() bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" outputCPL = subprocess.check_output(['bash','-c', bashCommand]) diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 0919db4ce..368547c60 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -35,11 +35,16 @@ mult,64,10,4.793300,46798.920227 mult,64,4000,1.411752,93087.261425 mult,64,5000,1.404875,94040.801492 mult,64,6000,1.415466,89931.661403 +shifter,16,10,0.000000,0.000000 +shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 shifter,32,4000,0.260606,3490.760054 shifter,32,4000,0.260606,3490.760054 +shifter,32,4000,0.260606,3490.760054 +shifter,32,5000,0.238962,4985.260077 shifter,32,5000,0.238962,4985.260077 shifter,32,5000,0.238962,4985.260077 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 +shifter,32,6000,0.241742,4312.000069 From c84731d6d00637e3d063e55b8077988544d7a118 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Mon, 16 May 2022 22:41:18 +0000 Subject: [PATCH 02/38] Fixed grammar on two comments in bpred.sv --- pipelined/src/ifu/bpred.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index de2ac72ab..2e306dc60 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -116,7 +116,7 @@ module bpred // this predictor will have two pieces of data, // 1) A direction (1 = Taken, 0 = Not Taken) - // 2) Any information which is necessary for the predictor to built it's next state. + // 2) Any information which is necessary for the predictor to build its next state. // For a 2 bit table this is the prediction count. assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) | From 7aba83a35c91161578cb93e257ca34ce7ee13207 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 17 May 2022 00:06:14 +0000 Subject: [PATCH 03/38] Cleaned up unpacker changes in srt and lint errors --- .gitignore | 1 + pipelined/srt/lint-srt | 2 +- pipelined/srt/srt.do | 2 +- pipelined/srt/srt.sv | 3 ++- pipelined/srt/testbench.sv | 23 ++++++++++++++--------- 5 files changed, 19 insertions(+), 12 deletions(-) diff --git a/.gitignore b/.gitignore index 0a25e7d3d..1e986c3bd 100644 --- a/.gitignore +++ b/.gitignore @@ -103,3 +103,4 @@ pipelined/config/rv64ic_noMulDiv pipelined/config/rv64ic_noPriv pipelined/config/rv64ic_orig synthDC/Summary.csv +pipelined/srt/exptestgen diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt index 8fba602e8..3599cdff5 100755 --- a/pipelined/srt/lint-srt +++ b/pipelined/srt/lint-srt @@ -1,2 +1,2 @@ verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv -verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv +verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv diff --git a/pipelined/srt/srt.do b/pipelined/srt/srt.do index df969ad49..b4d9bb138 100644 --- a/pipelined/srt/srt.do +++ b/pipelined/srt/srt.do @@ -17,7 +17,7 @@ if [file exists work] { } vlib work -vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpacking.sv +vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv vopt +acc work.testbench -o workopt vsim workopt diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index bc272b011..81d9e2f25 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -92,8 +92,9 @@ module srtpostproc #(parameter N=52) ( output [N-1:0] Quot ); + // replace with on-the-fly conversion //assign Quot = rp - rm; - finaladd finaladd(rp, rm, Quot); + finaladd finaladd(rp, rm, Quot); endmodule module srtpreproc #(parameter Nf=52) ( diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 8b3fec51d..9985a89cf 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,7 +1,7 @@ ///////////// -// counter // +// divcounter // ///////////// -module counter(input logic clk, +module divcounter(input logic clk, input logic req, output logic done); @@ -36,6 +36,9 @@ endmodule ////////// // testbench // ////////// + +/* verilator lint_off STMTDLY */ +/* verilator lint_off INFINITELOOP */ module testbench; logic clk; logic req; @@ -83,11 +86,11 @@ module testbench; // Unpacker // Note: BiasE will probably get taken out eventually - unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), + unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), - .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE), + .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); // Divider @@ -101,8 +104,8 @@ module testbench; assign result = {1'b0, e, r}; - // Counter - counter counter(clk, req, done); + // Divcounter + divcounter divcounter(clk, req, done); initial @@ -123,7 +126,7 @@ module testbench; a = Vec[`mema]; b = Vec[`memb]; nextr = Vec[`memr]; - req <= #5 1; + req = #5 1; end // Apply directed test vectors read from file. @@ -132,7 +135,7 @@ module testbench; begin if (done) begin - req <= #5 1; + req = #5 1; diffp = correctr - result; diffn = result - correctr; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp @@ -152,7 +155,7 @@ module testbench; end if (req) begin - req <= #5 0; + req = #5 0; correctr = nextr; $display("pre increment"); testnum = testnum+1; @@ -167,3 +170,5 @@ module testbench; endmodule +/* verilator lint_on STMTDLY */ +/* verilator lint_on INFINITELOOP */ From b992a61ca3c04afb3dea9c44c74b039668f2cca8 Mon Sep 17 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pipelined/config/rv64gc/wally-config.vh | 4 ++-- pipelined/testbench/testbench.sv | 20 ++++++++++++++++---- pipelined/testbench/tests.vh | 2 +- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 35b74c6d2..d7ad9d3c8 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -131,8 +131,8 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" +`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/shared/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index d070aa3f2..e3eaf93bd 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -327,11 +327,23 @@ logic [3:0] dummy; .done(DCacheFlushDone)); // initialize the branch predictor - if (`BPRED_ENABLED == 1) + if (`BPRED_ENABLED == 1) initial begin - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); - end + integer adrindex; + + // Initializing all zeroes into the branch predictor memory. + for(adrindex = 0; adrindex < 1024; adrindex++) begin + force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + end + #1; + for(adrindex = 0; adrindex < 1024; adrindex++) begin + release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; + release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end + // $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); + // $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); + end endmodule module riscvassertions; diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 49ff0ff5c..dba197f5f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -962,7 +962,7 @@ string imperas32f[] = '{ "rv64i_m/I/andi-01", "6010", "rv64i_m/I/auipc-01", "2010", "rv64i_m/I/beq-01", "47010", - "rv64i_m/I/bge-01", "46010", + "rv64i_m/I/bge-01", "47010", "rv64i_m/I/bgeu-01", "56010", "rv64i_m/I/blt-01", "4d010", "rv64i_m/I/bltu-01", "57010", From ba572b46f4038636998f0cdcd92d22482e659809 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 01:04:13 +0000 Subject: [PATCH 06/38] Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature. --- pipelined/testbench/testbench.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index e3eaf93bd..5aa1750dc 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -341,8 +341,6 @@ logic [3:0] dummy; release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; end - // $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - // $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); end endmodule From de8f66a121c632c38f813e07547ab6fccc2b147f Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Tue, 17 May 2022 01:10:31 +0000 Subject: [PATCH 07/38] added plotting --- synthDC/ppa.py | 80 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 63 insertions(+), 17 deletions(-) diff --git a/synthDC/ppa.py b/synthDC/ppa.py index 4d1657771..1eefb1021 100755 --- a/synthDC/ppa.py +++ b/synthDC/ppa.py @@ -1,28 +1,37 @@ #!/usr/bin/python3 -# from msilib.schema import File +#from msilib.schema import File import subprocess from multiprocessing import Pool import csv import re -# import matplotlib.pyplot as plt -# import numpy as np +import matplotlib.pyplot as plt +import numpy as np -print("hi") -def run_command(module, width, freq): - command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq) +def run_command(module, width, tech, freq): + command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq) subprocess.Popen(command, shell=True) -widths = ['16'] -modules = ['shifter'] -freqs = ['10'] +def deleteRedundant(LoT): + '''not working''' + synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}_{}_*" + for synth in LoT: + print(synth) + bashCommand = synthStr.format(*synth) + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) +widths = ['8'] +modules = ['add'] +freqs = ['10'] +tech = 'sky90' LoT = [] for module in modules: for width in widths: for freq in freqs: - LoT += [[module, width, freq]] + LoT += [[module, width, tech, freq]] + +deleteRedundant(LoT) pool = Pool() pool.starmap(run_command, LoT) @@ -45,13 +54,11 @@ allSynths = [] for i in range(len(linesCPL)): line = linesCPL[i] - oneSynth = [] mwm = wm.findall(line)[0][4:-4].split('_') - oneSynth += [mwm[0]] - oneSynth += [mwm[1]] - oneSynth += [f.findall(line)[0][1:-4]] - oneSynth += cpl.findall(line) - oneSynth += da.findall(linesDA[i]) + oneSynth = [mwm[0], int(mwm[1])] + oneSynth += [int(f.findall(line)[0][1:-4])] + oneSynth += [float(cpl.findall(line)[0])] + oneSynth += [float(da.findall(linesDA[i])[0])] allSynths += [oneSynth] file = open("ppaData.csv", "w") @@ -61,4 +68,43 @@ writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) for one in allSynths: writer.writerow(one) -file.close() \ No newline at end of file +file.close() + + +def plotPPA(module, freq, var): + ''' + module: string module name + freq: int freq (GHz) + var: string 'delay' or 'area' + plots chosen variable vs width for all matching syntheses with regression + ''' + global allSynths + ind = 3 if (var == 'delay') else 4 + widths = [] + ivar = [] + for oneSynth in allSynths: + if (oneSynth[0] == module) & (oneSynth[2] == freq): + + widths += [oneSynth[1]] + ivar += [oneSynth[ind]] + + x = np.array(widths, dtype=np.int) + y = np.array(ivar, dtype=np.float) + + A = np.vstack([x, np.ones(len(x))]).T + m, c = np.linalg.lstsq(A, y, rcond=None)[0] + z = np.polyfit(x, y, 2) + p = np.poly1d(z) + + xp = np.linspace(0, 140, 200) + + _ = plt.plot(x, y, 'o', label=module, markersize=10) + _ = plt.plot(x, m*x + c, 'r', label='Linear fit') + _ = plt.plot(xp, p(xp), label='Quadratic fit') + _ = plt.legend() + _ = plt.xlabel("Width (bits)") + _ = plt.ylabel(str.title(var)) + plt.show() + + +plotPPA('add', 5000, 'delay') \ No newline at end of file From 24420dea6cc89775499e3cced136a020f21b3931 Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Tue, 17 May 2022 01:11:43 +0000 Subject: [PATCH 08/38] added 8 and 128 bit versions, adjusted alu --- pipelined/src/ppa/ppa.sv | 80 +++++++++++++++++++++++++++++++++++----- 1 file changed, 70 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 01e06bb71..03b004f69 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -3,6 +3,14 @@ // & mmasserfrye@hmc.edu // Measure PPA of various building blocks +module ppa_comparator_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -27,6 +35,14 @@ module ppa_comparator_64 #(parameter WIDTH=64) ( ppa_comparator #(WIDTH) comp (.*); endmodule +module ppa_comparator_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -45,6 +61,13 @@ module ppa_comparator #(parameter WIDTH=16) ( assign flags = {eq, lt}; endmodule +module ppa_add_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + module ppa_add_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] y); @@ -66,6 +89,19 @@ module ppa_add_64 #(parameter WIDTH=64) ( assign y = a + b; endmodule +module ppa_add_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_mult_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_mult_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH*2-1:0] y); //is this right width @@ -84,6 +120,12 @@ module ppa_mult_64 #(parameter WIDTH=64) ( assign y = a * b; endmodule +module ppa_mult_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_alu_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, B, input logic [2:0] ALUControl, @@ -180,6 +222,15 @@ module ppa_shiftleft #(parameter WIDTH=32) ( assign y = a << amt; endmodule +module ppa_shifter_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -207,6 +258,15 @@ module ppa_shifter_64 #(parameter WIDTH=64) ( ppa_shifter #(WIDTH) sh (.*); endmodule +module ppa_shifter_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -221,14 +281,7 @@ module ppa_shifter #(parameter WIDTH=32) ( // For RV64, 32 and 64-bit shifts are needed, with sign extension. // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (WIDTH==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 + if (WIDTH == 64) begin:shifter // RV64 fix what about 128 always_comb // funnel mux if (W64) begin // 32-bit shifts if (Right) @@ -241,8 +294,15 @@ module ppa_shifter #(parameter WIDTH=32) ( else z = {63'b0, A}; else z = {A, 63'b0}; end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift - end + end else begin:shifter // RV32, + always_comb // funnel mux + if (Right) + if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + else z = {{WIDTH-1{1'b0}}, A}; + else z = {A, {WIDTH-1{1'b0}}}; + assign amttrunc = Amt; // shift amount + end + assign amttrunc = (W64 & WIDTH==64) ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift fix // opposite offset for right shfits assign offset = Right ? amttrunc : ~amttrunc; From 20c861ee6fe704fafbc6160f791fbfbac2e34469 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 17 May 2022 15:09:48 +0000 Subject: [PATCH 09/38] Restored srt to working without exponent unit --- pipelined/srt/Makefile | 4 +- pipelined/srt/lint-srt | 1 - pipelined/srt/srt.do | 2 +- pipelined/srt/srt.sv | 17 +- pipelined/srt/srt_stanford.sv | 8 +- pipelined/srt/testbench.sv | 92 +-- pipelined/srt/testgen.c | 3 +- pipelined/srt/testvectors | 1078 ++++++++++++++++++++++++--------- 8 files changed, 821 insertions(+), 384 deletions(-) diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index db5a11f86..73a0b75fa 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -3,5 +3,5 @@ all: sqrttestgen testgen sqrttestgen: sqrttestgen.c gcc sqrttestgen.c -lm -o sqrttestgen -testgen: exptestgen.c - gcc exptestgen.c -lm -o exptestgen +testgen: testgen.c + gcc testgen.c -lm -o testgen diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt index 3599cdff5..399201be0 100755 --- a/pipelined/srt/lint-srt +++ b/pipelined/srt/lint-srt @@ -1,2 +1 @@ verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv -verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv diff --git a/pipelined/srt/srt.do b/pipelined/srt/srt.do index b4d9bb138..8be358057 100644 --- a/pipelined/srt/srt.do +++ b/pipelined/srt/srt.do @@ -17,7 +17,7 @@ if [file exists work] { } vlib work -vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv +vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv vopt +acc work.testbench -o workopt vsim workopt diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 81d9e2f25..044bac9c1 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -37,8 +37,6 @@ module srt #(parameter Nf=52) ( input logic Flush, // *** multiple pipe stages // Floating Point Inputs // later add exponents, signs, special cases - input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits - // end of floating point inputs input logic [Nf-1:0] SrcXFrac, SrcYFrac, input logic [`XLEN-1:0] SrcA, SrcB, input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit @@ -47,7 +45,6 @@ module srt #(parameter Nf=52) ( input logic Int, // Choose integer inputss input logic Sqrt, // perform square root, not divide output logic [Nf-1:0] Quot, Rem, // *** later handle integers - output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision output logic [3:0] Flags ); @@ -81,9 +78,6 @@ module srt #(parameter Nf=52) ( // Partial Product Generation csa csa(WS, WC, Dsel, qp, WSA, WCA); - // Exponent division - exp exp(SrcXExpE, SrcYExpE, Exp); - srtpostproc postproc(rp, rm, Quot); endmodule @@ -92,9 +86,8 @@ module srtpostproc #(parameter N=52) ( output [N-1:0] Quot ); - // replace with on-the-fly conversion //assign Quot = rp - rm; - finaladd finaladd(rp, rm, Quot); + finaladd finaladd(rp, rm, Quot); endmodule module srtpreproc #(parameter Nf=52) ( @@ -254,14 +247,6 @@ module csa #(parameter N=56) ( (in2[54:0] & in3[54:0]), cin}; endmodule -////////////// -// exponent // -////////////// -module exp(input [10:0] e1, e2, - output [10:0] e); // for double precision, exponent is 11 bits - assign e = (e1 - e2) + 11'd1023; // bias is hardcoded -endmodule - ////////////// // finaladd // ////////////// diff --git a/pipelined/srt/srt_stanford.sv b/pipelined/srt/srt_stanford.sv index 23ab683d5..ce0417f56 100644 --- a/pipelined/srt/srt_stanford.sv +++ b/pipelined/srt/srt_stanford.sv @@ -11,9 +11,7 @@ // This Verilog file models a radix 2 SRT divider which // produces one quotient digit per cycle. The divider // keeps the partial remainder in carry-save form. - -`include "wally-config.vh" - + ///////// // srt // ///////// @@ -328,9 +326,7 @@ module testbench; begin req <= #5 1; $display("result was %h, should be %h\n", r, correctr); - //if (abs(correctr - r) > 1) // check if accurate to 1 ulp - // giving error "srt_stanford.sv(395): (vopt-7063) Failed to find 'abs' in hierarchical name 'abs'." - if (correctr - r > 1) // check if accurate to 1 ulp + if ((correctr - r) > 1) // check if accurate to 1 ulp begin errors = errors+1; $display("failed\n"); diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 9985a89cf..0af3821ec 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,7 +1,7 @@ ///////////// -// divcounter // +// counter // ///////////// -module divcounter(input logic clk, +module counter(input logic clk, input logic req, output logic done); @@ -36,76 +36,40 @@ endmodule ////////// // testbench // ////////// - -/* verilator lint_off STMTDLY */ -/* verilator lint_off INFINITELOOP */ module testbench; logic clk; logic req; logic done; - logic [63:0] a; - logic [63:0] b; - logic [63:0] result; - logic [51:0] r; + logic [51:0] a; + logic [51:0] b; + logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits - logic [10:0] e; // output exponent - // input logic for Unpacker - // input logic [63:0] X, Y, Z, - numbers - // input logic FmtE, ---- format, 1 is for double precision, 0 is single - // input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide - // all variables are commented in fpu.sv - - // output logic from Unpacker - logic XSgnE, YSgnE, ZSgnE; - logic [10:0] XExpE, YExpE, ZExpE; // exponent - logic [52:0] XManE, YManE, ZManE; - logic XNormE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; // denormals - logic XZeroE, YZeroE, ZZeroE; - logic [10:0] BiasE; // currrently hardcoded, will probs be removed - logic XInfE, YInfE, ZInfE; - logic XExpMaxE; // says exponent is all ones, can ignore - // Test parameters - parameter MEM_SIZE = 60000; - parameter MEM_WIDTH = 64+64+64; + parameter MEM_SIZE = 40000; + parameter MEM_WIDTH = 52+52+52; - `define memr 63:0 - `define memb 127:64 - `define mema 191:128 + `define memr 51:0 + `define memb 103:52 + `define mema 155:104 // Test logicisters logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a // bit field of an array - logic [63:0] correctr, nextr, diffn, diffp; + logic [51:0] correctr, nextr, diffn, diffp; integer testnum, errors; - // Unpacker - // Note: BiasE will probably get taken out eventually - unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), - .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), - .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), - .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), - .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), - .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); - // Divider srt #(52) srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), - .SrcXExpE(XExpE), .SrcYExpE(YExpE), - .SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]), + .SrcXFrac(a), .SrcYFrac(b), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .Rem(), .Exp(e), .Flags()); + .Quot(r), .Rem(), .Flags()); - assign result = {1'b0, e, r}; - - // Divcounter - divcounter divcounter(clk, req, done); + // Counter + counter counter(clk, req, done); initial @@ -126,7 +90,7 @@ module testbench; a = Vec[`mema]; b = Vec[`memb]; nextr = Vec[`memr]; - req = #5 1; + req <= #5 1; end // Apply directed test vectors read from file. @@ -135,19 +99,17 @@ module testbench; begin if (done) begin - req = #5 1; - diffp = correctr - result; - diffn = result - correctr; + req <= #5 1; + diffp = correctr - r; + diffn = r - correctr; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; - $display("a = %h b = %h result = %h",a,b,correctr); - $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp); - $display("at fail"); + $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); $display("failed\n"); $stop; end - if (a === 64'hxxxxxxxxxxxxxxxx) + if (a === 52'hxxxxxxxxxxxxx) begin $display("%d Tests completed successfully", testnum); $stop; @@ -155,20 +117,16 @@ module testbench; end if (req) begin - req = #5 0; + req <= #5 0; correctr = nextr; - $display("pre increment"); testnum = testnum+1; - a = Vec[`mema]; - b = Vec[`memb]; Vec = Tests[testnum]; - $display("a = %h b = %h result = %h",a,b,nextr); + $display("a = %h b = %h",a,b); + a = Vec[`mema]; + b = Vec[`memb]; nextr = Vec[`memr]; - $display("after increment"); end end endmodule -/* verilator lint_on STMTDLY */ -/* verilator lint_on INFINITELOOP */ diff --git a/pipelined/srt/testgen.c b/pipelined/srt/testgen.c index 143ef058f..98d52819b 100644 --- a/pipelined/srt/testgen.c +++ b/pipelined/srt/testgen.c @@ -28,7 +28,7 @@ double random_input(void); void main(void) { FILE *fptr; - double x1, x2, a, b, r; + double a, b, r; double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -63,7 +63,6 @@ void main(void) void output(FILE *fptr, double a, double b, double r) { - printhex(fptr, a); fprintf(fptr, "_"); printhex(fptr, b); diff --git a/pipelined/srt/testvectors b/pipelined/srt/testvectors index c6412a9e6..112803fe9 100644 --- a/pipelined/srt/testvectors +++ b/pipelined/srt/testvectors @@ -1,289 +1,789 @@ -4000000000000000_4000000000000000_3ff0000000000000 -4018000000000000_4000000000000000_4008000000000000 -4024000000000000_4000000000000000_4014000000000000 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+388a7114e229c_5202a405480a9_d96b8ce030793 +5112a225444a8_71c8e391c7239_d2b5183c88cc1 +2b485690ad216_ba017402e805d_5aad01f0f330a +0130026004c01_e1edc3db87b71_113c45ac1389f +abf757eeafdd6_7a9af535ea6bd_21604b0e84524 +350c6a18d431a_82c905920b242_9918ede81ed1a +2a8c5518aa315_8cbf197e32fc6_8146816fcd820 +80b3016602cc0_915922b245648_eac2cca581d9f From 6c54503b89a01a9f4cb2c0ca4f51e6a6a87373cf Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Tue, 17 May 2022 18:29:38 +0000 Subject: [PATCH 10/38] broke up ppa analysis and synthesis --- synthDC/Synopsys_stack_trace_12580.txt | 17 ++++ synthDC/Synopsys_stack_trace_32764.txt | 17 ++++ synthDC/Synopsys_stack_trace_57184.txt | 17 ++++ synthDC/Synopsys_stack_trace_57185.txt | 17 ++++ synthDC/crte_000012580.txt | 67 +++++++++++++++ synthDC/crte_000032764.txt | 67 +++++++++++++++ synthDC/crte_000057184.txt | 67 +++++++++++++++ synthDC/crte_000057185.txt | 67 +++++++++++++++ synthDC/ppa.py | 110 ------------------------- synthDC/ppaAnalyze.py | 95 +++++++++++++++++++++ synthDC/ppaData.csv | 35 ++++++-- synthDC/ppaSynth.py | 37 +++++++++ 12 files changed, 494 insertions(+), 119 deletions(-) create mode 100644 synthDC/Synopsys_stack_trace_12580.txt create mode 100644 synthDC/Synopsys_stack_trace_32764.txt create mode 100644 synthDC/Synopsys_stack_trace_57184.txt create mode 100644 synthDC/Synopsys_stack_trace_57185.txt create mode 100644 synthDC/crte_000012580.txt create mode 100644 synthDC/crte_000032764.txt create mode 100644 synthDC/crte_000057184.txt create mode 100644 synthDC/crte_000057185.txt delete mode 100755 synthDC/ppa.py create mode 100755 synthDC/ppaAnalyze.py create mode 100755 synthDC/ppaSynth.py diff --git a/synthDC/Synopsys_stack_trace_12580.txt b/synthDC/Synopsys_stack_trace_12580.txt new file mode 100644 index 000000000..ca9522e03 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_12580.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 12580 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_32764.txt b/synthDC/Synopsys_stack_trace_32764.txt new file mode 100644 index 000000000..f845fa3f8 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_32764.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 32764 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57184.txt b/synthDC/Synopsys_stack_trace_57184.txt new file mode 100644 index 000000000..a016d47c4 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_57184.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 57184 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57185.txt b/synthDC/Synopsys_stack_trace_57185.txt new file mode 100644 index 000000000..dec54674a --- /dev/null +++ b/synthDC/Synopsys_stack_trace_57185.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 57185 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/crte_000012580.txt b/synthDC/crte_000012580.txt new file mode 100644 index 000000000..2bc74daac --- /dev/null +++ b/synthDC/crte_000012580.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +12580 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 23:44:09 UTC 2022 (1652744649) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000032764.txt b/synthDC/crte_000032764.txt new file mode 100644 index 000000000..87eaa3c4c --- /dev/null +++ b/synthDC/crte_000032764.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +32764 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Tue May 17 00:05:18 UTC 2022 (1652745918) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 dest +0x00000000 15204364 harris 644 790528 3 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000057184.txt b/synthDC/crte_000057184.txt new file mode 100644 index 000000000..77c41bece --- /dev/null +++ b/synthDC/crte_000057184.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +57184 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 22:54:26 UTC 2022 (1652741666) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000057185.txt b/synthDC/crte_000057185.txt new file mode 100644 index 000000000..d99b82eb3 --- /dev/null +++ b/synthDC/crte_000057185.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +57185 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 22:54:26 UTC 2022 (1652741666) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/ppa.py b/synthDC/ppa.py deleted file mode 100755 index 1eefb1021..000000000 --- a/synthDC/ppa.py +++ /dev/null @@ -1,110 +0,0 @@ -#!/usr/bin/python3 -#from msilib.schema import File -import subprocess -from multiprocessing import Pool -import csv -import re -import matplotlib.pyplot as plt -import numpy as np - - -def run_command(module, width, tech, freq): - command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq) - subprocess.Popen(command, shell=True) - -def deleteRedundant(LoT): - '''not working''' - synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}_{}_*" - for synth in LoT: - print(synth) - bashCommand = synthStr.format(*synth) - outputCPL = subprocess.check_output(['bash','-c', bashCommand]) - -widths = ['8'] -modules = ['add'] -freqs = ['10'] -tech = 'sky90' - -LoT = [] -for module in modules: - for width in widths: - for freq in freqs: - LoT += [[module, width, tech, freq]] - -deleteRedundant(LoT) - -pool = Pool() -pool.starmap(run_command, LoT) -pool.close() - -bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" -outputCPL = subprocess.check_output(['bash','-c', bashCommand]) -linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] - -bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" -outputDA = subprocess.check_output(['bash','-c', bashCommand]) -linesDA = outputDA.decode("utf-8").split('\n')[:-1] - -cpl = re.compile('\d{1}\.\d{6}') -f = re.compile('_\d*_MHz') -wm = re.compile('ppa_\w*_\d*_qor') -da = re.compile('\d*\.\d{6}') - -allSynths = [] - -for i in range(len(linesCPL)): - line = linesCPL[i] - mwm = wm.findall(line)[0][4:-4].split('_') - oneSynth = [mwm[0], int(mwm[1])] - oneSynth += [int(f.findall(line)[0][1:-4])] - oneSynth += [float(cpl.findall(line)[0])] - oneSynth += [float(da.findall(linesDA[i])[0])] - allSynths += [oneSynth] - -file = open("ppaData.csv", "w") -writer = csv.writer(file) -writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) - -for one in allSynths: - writer.writerow(one) - -file.close() - - -def plotPPA(module, freq, var): - ''' - module: string module name - freq: int freq (GHz) - var: string 'delay' or 'area' - plots chosen variable vs width for all matching syntheses with regression - ''' - global allSynths - ind = 3 if (var == 'delay') else 4 - widths = [] - ivar = [] - for oneSynth in allSynths: - if (oneSynth[0] == module) & (oneSynth[2] == freq): - - widths += [oneSynth[1]] - ivar += [oneSynth[ind]] - - x = np.array(widths, dtype=np.int) - y = np.array(ivar, dtype=np.float) - - A = np.vstack([x, np.ones(len(x))]).T - m, c = np.linalg.lstsq(A, y, rcond=None)[0] - z = np.polyfit(x, y, 2) - p = np.poly1d(z) - - xp = np.linspace(0, 140, 200) - - _ = plt.plot(x, y, 'o', label=module, markersize=10) - _ = plt.plot(x, m*x + c, 'r', label='Linear fit') - _ = plt.plot(xp, p(xp), label='Quadratic fit') - _ = plt.legend() - _ = plt.xlabel("Width (bits)") - _ = plt.ylabel(str.title(var)) - plt.show() - - -plotPPA('add', 5000, 'delay') \ No newline at end of file diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py new file mode 100755 index 000000000..fef78921a --- /dev/null +++ b/synthDC/ppaAnalyze.py @@ -0,0 +1,95 @@ +#!/usr/bin/python3 +import subprocess +import csv +import re +import matplotlib.pyplot as plt +import numpy as np + +def getData(): + bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] + + bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" + outputDA = subprocess.check_output(['bash','-c', bashCommand]) + linesDA = outputDA.decode("utf-8").split('\n')[:-1] + + cpl = re.compile('\d{1}\.\d{6}') + f = re.compile('_\d*_MHz') + wm = re.compile('ppa_\w*_\d*_qor') + da = re.compile('\d*\.\d{6}') + + allSynths = [] + + for i in range(len(linesCPL)): + line = linesCPL[i] + mwm = wm.findall(line)[0][4:-4].split('_') + oneSynth = [mwm[0], int(mwm[1])] + oneSynth += [int(f.findall(line)[0][1:-4])] + oneSynth += [float(cpl.findall(line)[0])] + oneSynth += [float(da.findall(linesDA[i])[0])] + allSynths += [oneSynth] + + return allSynths + +def writeCSV(allSynths): + file = open("ppaData.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) + + for one in allSynths: + writer.writerow(one) + + file.close() + +def plotPPA(module, freq, var): + ''' + module: string module name + freq: int freq (GHz) + var: string 'delay' or 'area' + plots chosen variable vs width for all matching syntheses with regression + ''' + global allSynths + ind = 3 if (var == 'delay') else 4 + widths = [] + ivar = [] + for oneSynth in allSynths: + if (oneSynth[0] == module) & (oneSynth[2] == freq): + + widths += [oneSynth[1]] + ivar += [oneSynth[ind]] + + x = np.array(widths, dtype=np.int) + y = np.array(ivar, dtype=np.float) + + A = np.vstack([x, np.ones(len(x))]).T + m, c = np.linalg.lstsq(A, y, rcond=None)[0] + + z = np.polyfit(x, y, 2) + p = np.poly1d(z) + + zlog = np.polyfit(np.log(x), y, 1) + plog = np.poly1d(zlog) + + xp = np.linspace(0, 140, 200) + xplog = np.log(xp) + + _ = plt.plot(x, y, 'o', label=module, markersize=10) + _ = plt.plot(x, m*x + c, 'r', label='Linear fit') + _ = plt.plot(xp, p(xp), label='Quadratic fit') + _ = plt.plot(xp, plog(xplog), label = 'Log fit') + _ = plt.legend() + _ = plt.xlabel("Width (bits)") + _ = plt.ylabel(str.title(var)) + _ = plt.title("Target frequency " + str(freq)) + plt.show() +#fix square microns, picosec, end plots at 8 to stop negs, add equation to plots and R2 +# try linear term with delay as well (w and wo) + +allSynths = getData() + +writeCSV(allSynths) + +plotPPA('mult', 5000, 'delay') +plotPPA('mult', 5000, 'area') +plotPPA('mult', 10, 'area') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 368547c60..d5232bb4e 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,28 +1,38 @@ Module,Width,Target Freq,Delay,Area +add,128,10,7.100851,1867.879976 +add,128,5000,0.389771,7007.980119 add,16,10,2.032906,221.479998 -add,16,4000,0.249839,551.740010 +add,16,4000,0.249839,551.74001 add,16,5000,0.228259,924.140017 add,16,6000,0.225754,1120.140018 add,32,10,4.160501,456.679995 add,32,4000,0.280842,1730.680031 -add,32,5000,0.250500,1933.540033 -add,32,6000,0.271774,1746.360030 +add,32,5000,0.2505,1933.540033 +add,32,6000,0.271774,1746.36003 add,64,10,8.474034,927.079988 add,64,4000,0.323267,3758.300065 add,64,5000,0.334061,3798.480071 add,64,6000,0.328457,3749.480066 +add,8,10,0.940062,103.879999 +add,8,5000,0.199689,197.960003 +comparator,128,10,0.842074,1997.240039 +comparator,128,5000,0.260142,5215.56005 comparator,16,10,0.576329,252.840005 comparator,16,4000,0.249312,280.280005 comparator,16,5000,0.199026,313.600006 comparator,16,6000,0.166568,422.380007 -comparator,32,10,0.765874,495.880010 -comparator,32,4000,0.249950,608.580012 +comparator,32,10,0.765874,495.88001 +comparator,32,4000,0.24995,608.580012 comparator,32,5000,0.205372,919.240014 -comparator,32,6000,0.201200,1248.520016 -comparator,64,10,0.561562,1008.420020 +comparator,32,6000,0.2012,1248.520016 +comparator,64,10,0.561562,1008.42002 comparator,64,4000,0.249905,1437.660027 comparator,64,5000,0.219296,2738.120023 comparator,64,6000,0.221138,2341.220025 +comparator,8,10,0.29577,118.580002 +comparator,8,5000,0.195502,129.360003 +mult,128,10,9.334627,180734.540854 +mult,128,5000,1.78322,314617.244472 mult,16,10,4.730546,3869.040009 mult,16,4000,0.821111,9132.620147 mult,16,5000,0.820059,9583.420143 @@ -31,11 +41,16 @@ mult,32,10,7.575772,12412.680067 mult,32,4000,1.091389,31262.980534 mult,32,5000,1.092153,31497.200524 mult,32,6000,1.084816,33519.920555 -mult,64,10,4.793300,46798.920227 +mult,64,10,4.7933,46798.920227 mult,64,4000,1.411752,93087.261425 mult,64,5000,1.404875,94040.801492 mult,64,6000,1.415466,89931.661403 -shifter,16,10,0.000000,0.000000 +mult,8,10,2.076433,1009.399998 +mult,8,5000,0.552339,4261.040075 +shifter,128,10,2.577935,8113.420158 +shifter,128,5000,0.395847,16602.180268 +shifter,16,10,0.0,0.0 +shifter,16,10,0.0,0.0 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 @@ -48,3 +63,5 @@ shifter,32,5000,0.238962,4985.260077 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 +shifter,8,10,0.0,0.0 +shifter,8,5000,0.0,0.0 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py new file mode 100755 index 000000000..654d77391 --- /dev/null +++ b/synthDC/ppaSynth.py @@ -0,0 +1,37 @@ +#!/usr/bin/python3 +import subprocess +from multiprocessing import Pool + + +def runCommand(module, width, tech, freq): + command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq) + subprocess.Popen(command, shell=True) + +def deleteRedundant(LoT): + '''removes any previous runs for the current synthesis specifications''' + synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}nm_{}_*" + for synth in LoT: + bashCommand = synthStr.format(*synth) + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + +widths = ['128'] +modules = ['mult'] +freqs = ['5000'] +tech = 'sky90' + +#to run: add 8 10, shifter 8 16 (check .sv!) + +LoT = [] +for module in modules: + for width in widths: + for freq in freqs: + LoT += [[module, width, tech, freq]] + +deleteRedundant(LoT) + +pool = Pool() +pool.starmap(runCommand, LoT) +pool.close() + +bashCommand = "wait" +outputCPL = subprocess.check_output(['bash','-c', bashCommand]) \ No newline at end of file From 9d1283c787dfdf7ea2252ce024024ed3e4439b37 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 17 May 2022 19:26:17 +0000 Subject: [PATCH 11/38] comments about activity factor in synthesis --- synthDC/scripts/synth.tcl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 9d6aac68a..368e45f3a 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -137,6 +137,10 @@ if {$tech == "sky130"} { # Set the wire load model set_wire_load_mode "top" +# Set switching activities +# default activity factors are 1 for clocks, 0.1 for others +# static probability of 0.5 is used for leakage + # Attempt Area Recovery - if looking for minimal area # set_max_area 2000 @@ -359,4 +363,4 @@ redirect $filename { report_constraint } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] # redirect $filename { report_hierarchy } -quit +#quit From 1131d4134336ae265c68b53183e8ab87a67b8758 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 20:32:38 +0000 Subject: [PATCH 12/38] added wkdir in regression so regression runs out of box (assuming the old version of arch tests) --- pipelined/regression/wkdir/.gitignore | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 pipelined/regression/wkdir/.gitignore diff --git a/pipelined/regression/wkdir/.gitignore b/pipelined/regression/wkdir/.gitignore new file mode 100644 index 000000000..5e7d2734c --- /dev/null +++ b/pipelined/regression/wkdir/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore From 83e4ab711cc4f66fc0cde311aa9bf7ca35431812 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 16:33:09 -0700 Subject: [PATCH 13/38] Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression --- pipelined/src/ieu/datapath.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 90b5f0335..068beb1c3 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -88,7 +88,7 @@ module datapath ( logic [`XLEN-1:0] IFResultW; // Decode stage - assign Rs1D = InstrD[19:15]; + assign Rs1D = InstrD[18:14]; // Broke this, it should be 19 to 15. assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); From c15aab9c6f0921b20ba34cf9802198e84837da00 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 16:54:29 -0700 Subject: [PATCH 14/38] Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" This reverts commit d601c89d2a07c586bda032c4a0bc33338983d782, reversing changes made to 1131d4134336ae265c68b53183e8ab87a67b8758. undid things --- pipelined/src/ppa/ppa.sv | 80 +- pipelined/srt/Makefile | 4 +- pipelined/srt/lint-srt | 1 + pipelined/srt/srt.do | 2 +- pipelined/srt/srt.sv | 17 +- pipelined/srt/srt_stanford.sv | 8 +- pipelined/srt/testbench.sv | 92 +- pipelined/srt/testgen.c | 3 +- pipelined/srt/testvectors | 1078 +++++++----------------- synthDC/Synopsys_stack_trace_12580.txt | 17 - synthDC/Synopsys_stack_trace_32764.txt | 17 - synthDC/Synopsys_stack_trace_57184.txt | 17 - synthDC/Synopsys_stack_trace_57185.txt | 17 - synthDC/crte_000012580.txt | 67 -- synthDC/crte_000032764.txt | 67 -- synthDC/crte_000057184.txt | 67 -- synthDC/crte_000057185.txt | 67 -- synthDC/ppa.py | 64 ++ synthDC/ppaAnalyze.py | 95 --- synthDC/ppaData.csv | 35 +- synthDC/ppaSynth.py | 37 - synthDC/scripts/synth.tcl | 6 +- 22 files changed, 468 insertions(+), 1390 deletions(-) delete mode 100644 synthDC/Synopsys_stack_trace_12580.txt delete mode 100644 synthDC/Synopsys_stack_trace_32764.txt delete mode 100644 synthDC/Synopsys_stack_trace_57184.txt delete mode 100644 synthDC/Synopsys_stack_trace_57185.txt delete mode 100644 synthDC/crte_000012580.txt delete mode 100644 synthDC/crte_000032764.txt delete mode 100644 synthDC/crte_000057184.txt delete mode 100644 synthDC/crte_000057185.txt create mode 100755 synthDC/ppa.py delete mode 100755 synthDC/ppaAnalyze.py delete mode 100755 synthDC/ppaSynth.py diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 03b004f69..01e06bb71 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -3,14 +3,6 @@ // & mmasserfrye@hmc.edu // Measure PPA of various building blocks -module ppa_comparator_8 #(parameter WIDTH=8) ( - input logic [WIDTH-1:0] a, b, - input logic sgnd, - output logic [1:0] flags); - - ppa_comparator #(WIDTH) comp (.*); -endmodule - module ppa_comparator_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -35,14 +27,6 @@ module ppa_comparator_64 #(parameter WIDTH=64) ( ppa_comparator #(WIDTH) comp (.*); endmodule -module ppa_comparator_128 #(parameter WIDTH=128) ( - input logic [WIDTH-1:0] a, b, - input logic sgnd, - output logic [1:0] flags); - - ppa_comparator #(WIDTH) comp (.*); -endmodule - module ppa_comparator #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -61,13 +45,6 @@ module ppa_comparator #(parameter WIDTH=16) ( assign flags = {eq, lt}; endmodule -module ppa_add_8 #(parameter WIDTH=8) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); - - assign y = a + b; -endmodule - module ppa_add_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] y); @@ -89,19 +66,6 @@ module ppa_add_64 #(parameter WIDTH=64) ( assign y = a + b; endmodule -module ppa_add_128 #(parameter WIDTH=128) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); - - assign y = a + b; -endmodule - -module ppa_mult_8 #(parameter WIDTH=8) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH*2-1:0] y); //is this right width - assign y = a * b; -endmodule - module ppa_mult_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH*2-1:0] y); //is this right width @@ -120,12 +84,6 @@ module ppa_mult_64 #(parameter WIDTH=64) ( assign y = a * b; endmodule -module ppa_mult_128 #(parameter WIDTH=128) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH*2-1:0] y); //is this right width - assign y = a * b; -endmodule - module ppa_alu_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, B, input logic [2:0] ALUControl, @@ -222,15 +180,6 @@ module ppa_shiftleft #(parameter WIDTH=32) ( assign y = a << amt; endmodule -module ppa_shifter_8 #(parameter WIDTH=8) ( - input logic [WIDTH-1:0] A, - input logic [$clog2(WIDTH)-1:0] Amt, - input logic Right, Arith, W64, - output logic [WIDTH-1:0] Y); - - ppa_shifter #(WIDTH) sh (.*); -endmodule - module ppa_shifter_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -258,15 +207,6 @@ module ppa_shifter_64 #(parameter WIDTH=64) ( ppa_shifter #(WIDTH) sh (.*); endmodule -module ppa_shifter_128 #(parameter WIDTH=128) ( - input logic [WIDTH-1:0] A, - input logic [$clog2(WIDTH)-1:0] Amt, - input logic Right, Arith, W64, - output logic [WIDTH-1:0] Y); - - ppa_shifter #(WIDTH) sh (.*); -endmodule - module ppa_shifter #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -281,7 +221,14 @@ module ppa_shifter #(parameter WIDTH=32) ( // For RV64, 32 and 64-bit shifts are needed, with sign extension. // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (WIDTH == 64) begin:shifter // RV64 fix what about 128 + if (WIDTH==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 always_comb // funnel mux if (W64) begin // 32-bit shifts if (Right) @@ -294,15 +241,8 @@ module ppa_shifter #(parameter WIDTH=32) ( else z = {63'b0, A}; else z = {A, 63'b0}; end - end else begin:shifter // RV32, - always_comb // funnel mux - if (Right) - if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; - else z = {{WIDTH-1{1'b0}}, A}; - else z = {A, {WIDTH-1{1'b0}}}; - assign amttrunc = Amt; // shift amount - end - assign amttrunc = (W64 & WIDTH==64) ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift fix + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift + end // opposite offset for right shfits assign offset = Right ? amttrunc : ~amttrunc; diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index 73a0b75fa..db5a11f86 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -3,5 +3,5 @@ all: sqrttestgen testgen sqrttestgen: sqrttestgen.c gcc sqrttestgen.c -lm -o sqrttestgen -testgen: testgen.c - gcc testgen.c -lm -o testgen +testgen: exptestgen.c + gcc exptestgen.c -lm -o exptestgen diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt index 399201be0..3599cdff5 100755 --- a/pipelined/srt/lint-srt +++ b/pipelined/srt/lint-srt @@ -1 +1,2 @@ verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv +verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv diff --git a/pipelined/srt/srt.do b/pipelined/srt/srt.do index 8be358057..b4d9bb138 100644 --- a/pipelined/srt/srt.do +++ b/pipelined/srt/srt.do @@ -17,7 +17,7 @@ if [file exists work] { } vlib work -vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv +vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv vopt +acc work.testbench -o workopt vsim workopt diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 044bac9c1..81d9e2f25 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -37,6 +37,8 @@ module srt #(parameter Nf=52) ( input logic Flush, // *** multiple pipe stages // Floating Point Inputs // later add exponents, signs, special cases + input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits + // end of floating point inputs input logic [Nf-1:0] SrcXFrac, SrcYFrac, input logic [`XLEN-1:0] SrcA, SrcB, input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit @@ -45,6 +47,7 @@ module srt #(parameter Nf=52) ( input logic Int, // Choose integer inputss input logic Sqrt, // perform square root, not divide output logic [Nf-1:0] Quot, Rem, // *** later handle integers + output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision output logic [3:0] Flags ); @@ -78,6 +81,9 @@ module srt #(parameter Nf=52) ( // Partial Product Generation csa csa(WS, WC, Dsel, qp, WSA, WCA); + // Exponent division + exp exp(SrcXExpE, SrcYExpE, Exp); + srtpostproc postproc(rp, rm, Quot); endmodule @@ -86,8 +92,9 @@ module srtpostproc #(parameter N=52) ( output [N-1:0] Quot ); + // replace with on-the-fly conversion //assign Quot = rp - rm; - finaladd finaladd(rp, rm, Quot); + finaladd finaladd(rp, rm, Quot); endmodule module srtpreproc #(parameter Nf=52) ( @@ -247,6 +254,14 @@ module csa #(parameter N=56) ( (in2[54:0] & in3[54:0]), cin}; endmodule +////////////// +// exponent // +////////////// +module exp(input [10:0] e1, e2, + output [10:0] e); // for double precision, exponent is 11 bits + assign e = (e1 - e2) + 11'd1023; // bias is hardcoded +endmodule + ////////////// // finaladd // ////////////// diff --git a/pipelined/srt/srt_stanford.sv b/pipelined/srt/srt_stanford.sv index ce0417f56..23ab683d5 100644 --- a/pipelined/srt/srt_stanford.sv +++ b/pipelined/srt/srt_stanford.sv @@ -11,7 +11,9 @@ // This Verilog file models a radix 2 SRT divider which // produces one quotient digit per cycle. The divider // keeps the partial remainder in carry-save form. - + +`include "wally-config.vh" + ///////// // srt // ///////// @@ -326,7 +328,9 @@ module testbench; begin req <= #5 1; $display("result was %h, should be %h\n", r, correctr); - if ((correctr - r) > 1) // check if accurate to 1 ulp + //if (abs(correctr - r) > 1) // check if accurate to 1 ulp + // giving error "srt_stanford.sv(395): (vopt-7063) Failed to find 'abs' in hierarchical name 'abs'." + if (correctr - r > 1) // check if accurate to 1 ulp begin errors = errors+1; $display("failed\n"); diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 0af3821ec..9985a89cf 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,7 +1,7 @@ ///////////// -// counter // +// divcounter // ///////////// -module counter(input logic clk, +module divcounter(input logic clk, input logic req, output logic done); @@ -36,40 +36,76 @@ endmodule ////////// // testbench // ////////// + +/* verilator lint_off STMTDLY */ +/* verilator lint_off INFINITELOOP */ module testbench; logic clk; logic req; logic done; - logic [51:0] a; - logic [51:0] b; - logic [51:0] r; + logic [63:0] a; + logic [63:0] b; + logic [63:0] result; + logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits + logic [10:0] e; // output exponent + // input logic for Unpacker + // input logic [63:0] X, Y, Z, - numbers + // input logic FmtE, ---- format, 1 is for double precision, 0 is single + // input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide + // all variables are commented in fpu.sv + + // output logic from Unpacker + logic XSgnE, YSgnE, ZSgnE; + logic [10:0] XExpE, YExpE, ZExpE; // exponent + logic [52:0] XManE, YManE, ZManE; + logic XNormE; + logic XNaNE, YNaNE, ZNaNE; + logic XSNaNE, YSNaNE, ZSNaNE; + logic XDenormE, YDenormE, ZDenormE; // denormals + logic XZeroE, YZeroE, ZZeroE; + logic [10:0] BiasE; // currrently hardcoded, will probs be removed + logic XInfE, YInfE, ZInfE; + logic XExpMaxE; // says exponent is all ones, can ignore + // Test parameters - parameter MEM_SIZE = 40000; - parameter MEM_WIDTH = 52+52+52; + parameter MEM_SIZE = 60000; + parameter MEM_WIDTH = 64+64+64; - `define memr 51:0 - `define memb 103:52 - `define mema 155:104 + `define memr 63:0 + `define memb 127:64 + `define mema 191:128 // Test logicisters logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a // bit field of an array - logic [51:0] correctr, nextr, diffn, diffp; + logic [63:0] correctr, nextr, diffn, diffp; integer testnum, errors; + // Unpacker + // Note: BiasE will probably get taken out eventually + unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), + .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), + .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), + .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), + .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), + .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); + // Divider srt #(52) srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), - .SrcXFrac(a), .SrcYFrac(b), + .SrcXExpE(XExpE), .SrcYExpE(YExpE), + .SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .Rem(), .Flags()); + .Quot(r), .Rem(), .Exp(e), .Flags()); - // Counter - counter counter(clk, req, done); + assign result = {1'b0, e, r}; + + // Divcounter + divcounter divcounter(clk, req, done); initial @@ -90,7 +126,7 @@ module testbench; a = Vec[`mema]; b = Vec[`memb]; nextr = Vec[`memr]; - req <= #5 1; + req = #5 1; end // Apply directed test vectors read from file. @@ -99,17 +135,19 @@ module testbench; begin if (done) begin - req <= #5 1; - diffp = correctr - r; - diffn = r - correctr; + req = #5 1; + diffp = correctr - result; + diffn = result - correctr; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; - $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); + $display("a = %h b = %h result = %h",a,b,correctr); + $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp); + $display("at fail"); $display("failed\n"); $stop; end - if (a === 52'hxxxxxxxxxxxxx) + if (a === 64'hxxxxxxxxxxxxxxxx) begin $display("%d Tests completed successfully", testnum); $stop; @@ -117,16 +155,20 @@ module testbench; end if (req) begin - req <= #5 0; + req = #5 0; correctr = nextr; + $display("pre increment"); testnum = testnum+1; - Vec = Tests[testnum]; - $display("a = %h b = %h",a,b); - a = Vec[`mema]; + a = Vec[`mema]; b = Vec[`memb]; + Vec = Tests[testnum]; + $display("a = %h b = %h result = %h",a,b,nextr); nextr = Vec[`memr]; + $display("after increment"); end end endmodule +/* verilator lint_on STMTDLY */ +/* verilator lint_on INFINITELOOP */ diff --git a/pipelined/srt/testgen.c b/pipelined/srt/testgen.c index 98d52819b..143ef058f 100644 --- a/pipelined/srt/testgen.c +++ b/pipelined/srt/testgen.c @@ -28,7 +28,7 @@ double random_input(void); void main(void) { FILE *fptr; - double a, b, r; + double x1, x2, a, b, r; double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -63,6 +63,7 @@ void main(void) void output(FILE *fptr, double a, double b, double r) { + printhex(fptr, a); fprintf(fptr, "_"); printhex(fptr, b); diff --git a/pipelined/srt/testvectors b/pipelined/srt/testvectors index 112803fe9..c6412a9e6 100644 --- a/pipelined/srt/testvectors +++ b/pipelined/srt/testvectors @@ -1,789 +1,289 @@ -0000000000000_0000000000000_0000000000000 -8000000000000_0000000000000_8000000000000 -4000000000000_0000000000000_4000000000000 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+4093333333333333_410c71c71c71c71c_3f8599999999999a +40a028f5c28f5c29_410c71c71c71c71c_3f922e147ae147ae +40b004189374bc6a_410c71c71c71c71c_3fa2049ba5e353f8 +40c00068db8bac71_410c71c71c71c71c_3fb20075f6fd21ff +40dd1745d1745d17_410c71c71c71c71c_3fc05d1745d1745d +40e5555555555555_410c71c71c71c71c_3fd8000000000000 +40f999999999999a_410c71c71c71c71c_3fecccccccccccce +410c71c71c71c71c_410c71c71c71c71c_3ff0000000000000 diff --git a/synthDC/Synopsys_stack_trace_12580.txt b/synthDC/Synopsys_stack_trace_12580.txt deleted file mode 100644 index ca9522e03..000000000 --- a/synthDC/Synopsys_stack_trace_12580.txt +++ /dev/null @@ -1,17 +0,0 @@ -GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 -Copyright (C) 2018 Free Software Foundation, Inc. -License GPLv3+: GNU GPL version 3 or later -This is free software: you are free to change and redistribute it. -There is NO WARRANTY, to the extent permitted by law. -Type "show copying" and "show warranty" for details. -This GDB was configured as "x86_64-redhat-linux-gnu". -Type "show configuration" for configuration details. -For bug reporting instructions, please see: -. -Find the GDB manual and other documentation resources online at: - . - -For help, type "help". -Type "apropos word" to search for commands related to "word". -Attaching to process 12580 -(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_32764.txt b/synthDC/Synopsys_stack_trace_32764.txt deleted file mode 100644 index f845fa3f8..000000000 --- a/synthDC/Synopsys_stack_trace_32764.txt +++ /dev/null @@ -1,17 +0,0 @@ -GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 -Copyright (C) 2018 Free Software Foundation, Inc. -License GPLv3+: GNU GPL version 3 or later -This is free software: you are free to change and redistribute it. -There is NO WARRANTY, to the extent permitted by law. -Type "show copying" and "show warranty" for details. -This GDB was configured as "x86_64-redhat-linux-gnu". -Type "show configuration" for configuration details. -For bug reporting instructions, please see: -. -Find the GDB manual and other documentation resources online at: - . - -For help, type "help". -Type "apropos word" to search for commands related to "word". -Attaching to process 32764 -(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57184.txt b/synthDC/Synopsys_stack_trace_57184.txt deleted file mode 100644 index a016d47c4..000000000 --- a/synthDC/Synopsys_stack_trace_57184.txt +++ /dev/null @@ -1,17 +0,0 @@ -GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 -Copyright (C) 2018 Free Software Foundation, Inc. -License GPLv3+: GNU GPL version 3 or later -This is free software: you are free to change and redistribute it. -There is NO WARRANTY, to the extent permitted by law. -Type "show copying" and "show warranty" for details. -This GDB was configured as "x86_64-redhat-linux-gnu". -Type "show configuration" for configuration details. -For bug reporting instructions, please see: -. -Find the GDB manual and other documentation resources online at: - . - -For help, type "help". -Type "apropos word" to search for commands related to "word". -Attaching to process 57184 -(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57185.txt b/synthDC/Synopsys_stack_trace_57185.txt deleted file mode 100644 index dec54674a..000000000 --- a/synthDC/Synopsys_stack_trace_57185.txt +++ /dev/null @@ -1,17 +0,0 @@ -GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 -Copyright (C) 2018 Free Software Foundation, Inc. -License GPLv3+: GNU GPL version 3 or later -This is free software: you are free to change and redistribute it. -There is NO WARRANTY, to the extent permitted by law. -Type "show copying" and "show warranty" for details. -This GDB was configured as "x86_64-redhat-linux-gnu". -Type "show configuration" for configuration details. -For bug reporting instructions, please see: -. -Find the GDB manual and other documentation resources online at: - . - -For help, type "help". -Type "apropos word" to search for commands related to "word". -Attaching to process 57185 -(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/crte_000012580.txt b/synthDC/crte_000012580.txt deleted file mode 100644 index 2bc74daac..000000000 --- a/synthDC/crte_000012580.txt +++ /dev/null @@ -1,67 +0,0 @@ -CRTE_SNAPSHOT_START - -SECTION_CRTE_VERSION -3.0 - -SECTION_PID -12580 - -SECTION_POLLING_INTERVAL -5 - -SECTION_DATE_TIME -Mon May 16 23:44:09 UTC 2022 (1652744649) - -SECTION_OS_VERSION -osname: Linux -hostname: tera -arch: x86_64 -release_version: 5.4.157-1-pve - -SECTION_IPC_INFO - ------- Message Queues -------- -key msqid owner perms used-bytes messages - ------- Shared Memory Segments -------- -key shmid owner perms bytes nattch status -0x00000000 15859713 nwhyte-agu 600 524288 2 dest -0x00000000 360451 nwhyte-agu 600 524288 2 dest -0x00000000 65540 kkim 600 134217728 2 dest -0x00000000 557061 nwhyte-agu 600 67108864 2 dest -0x00000000 6 harris 600 524288 2 dest -0x00000000 7 harris 600 524288 2 dest -0x00000000 5275656 harris 600 2097152 2 dest -0x00000000 11993097 kkim 600 524288 2 dest -0x00000000 15892490 kkim 600 524288 2 dest -0x00000000 11 harris 600 524288 2 SECTION_ULIMIT -core file size (blocks, -c) 0 -data seg size (kbytes, -d) unlimited -scheduling priority (-e) 0 -file size (blocks, -f) unlimited -pending signals (-i) 515072 -max locked memory (kbytes, -l) 64 -max memory size (kbytes, -m) unlimited -open files (-n) 524288 -pipe size (512 bytes, -p) 8 -POSIX message queues (bytes, -q) 819200 -real-time priority (-r) 0 -stack size (kbytes, -s) unlimited -cpu time (seconds, -t) unlimited -max user processes (-u) 515072 -virtual memory (kbytes, -v) unlimited -file locks (-x) unlimited - -SECTION_SYSCONF -_SC_THREAD_SAFE_FUNCTIONS= 200809 -_SC_CLK_TCK= 100 -_SC_OPEN_MAX= 524288 -_SC_PAGE_SIZE= 4096 -_SC_ARG_MAX= 4611686018427387903 -_SC_CHILD_MAX= 515072 -_SC_LINE_MAX= 2048 - -SECTION_FULL_COMMAND -/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl - -SECTION_CPUINFO diff --git a/synthDC/crte_000032764.txt b/synthDC/crte_000032764.txt deleted file mode 100644 index 87eaa3c4c..000000000 --- a/synthDC/crte_000032764.txt +++ /dev/null @@ -1,67 +0,0 @@ -CRTE_SNAPSHOT_START - -SECTION_CRTE_VERSION -3.0 - -SECTION_PID -32764 - -SECTION_POLLING_INTERVAL -5 - -SECTION_DATE_TIME -Tue May 17 00:05:18 UTC 2022 (1652745918) - -SECTION_OS_VERSION -osname: Linux -hostname: tera -arch: x86_64 -release_version: 5.4.157-1-pve - -SECTION_IPC_INFO - ------- Message Queues -------- -key msqid owner perms used-bytes messages - ------- Shared Memory Segments -------- -key shmid owner perms bytes nattch status -0x00000000 360451 nwhyte-agu 600 524288 2 dest -0x00000000 65540 kkim 600 134217728 2 dest -0x00000000 557061 nwhyte-agu 600 67108864 2 dest -0x00000000 6 harris 600 524288 2 dest -0x00000000 7 harris 600 524288 2 dest -0x00000000 5275656 harris 600 2097152 2 dest -0x00000000 11993097 kkim 600 524288 2 dest -0x00000000 15892490 kkim 600 524288 2 dest -0x00000000 11 harris 600 524288 2 dest -0x00000000 15204364 harris 644 790528 3 SECTION_ULIMIT -core file size (blocks, -c) 0 -data seg size (kbytes, -d) unlimited -scheduling priority (-e) 0 -file size (blocks, -f) unlimited -pending signals (-i) 515072 -max locked memory (kbytes, -l) 64 -max memory size (kbytes, -m) unlimited -open files (-n) 524288 -pipe size (512 bytes, -p) 8 -POSIX message queues (bytes, -q) 819200 -real-time priority (-r) 0 -stack size (kbytes, -s) unlimited -cpu time (seconds, -t) unlimited -max user processes (-u) 515072 -virtual memory (kbytes, -v) unlimited -file locks (-x) unlimited - -SECTION_SYSCONF -_SC_THREAD_SAFE_FUNCTIONS= 200809 -_SC_CLK_TCK= 100 -_SC_OPEN_MAX= 524288 -_SC_PAGE_SIZE= 4096 -_SC_ARG_MAX= 4611686018427387903 -_SC_CHILD_MAX= 515072 -_SC_LINE_MAX= 2048 - -SECTION_FULL_COMMAND -/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl - -SECTION_CPUINFO diff --git a/synthDC/crte_000057184.txt b/synthDC/crte_000057184.txt deleted file mode 100644 index 77c41bece..000000000 --- a/synthDC/crte_000057184.txt +++ /dev/null @@ -1,67 +0,0 @@ -CRTE_SNAPSHOT_START - -SECTION_CRTE_VERSION -3.0 - -SECTION_PID -57184 - -SECTION_POLLING_INTERVAL -5 - -SECTION_DATE_TIME -Mon May 16 22:54:26 UTC 2022 (1652741666) - -SECTION_OS_VERSION -osname: Linux -hostname: tera -arch: x86_64 -release_version: 5.4.157-1-pve - -SECTION_IPC_INFO - ------- Message Queues -------- -key msqid owner perms used-bytes messages - ------- Shared Memory Segments -------- -key shmid owner perms bytes nattch status -0x00000000 15859713 nwhyte-agu 600 524288 2 dest -0x00000000 360451 nwhyte-agu 600 524288 2 dest -0x00000000 65540 kkim 600 134217728 2 dest -0x00000000 557061 nwhyte-agu 600 67108864 2 dest -0x00000000 6 harris 600 524288 2 dest -0x00000000 7 harris 600 524288 2 dest -0x00000000 5275656 harris 600 2097152 2 dest -0x00000000 11993097 kkim 600 524288 2 dest -0x00000000 15892490 kkim 600 524288 2 dest -0x00000000 11 harris 600 524288 2 SECTION_ULIMIT -core file size (blocks, -c) 0 -data seg size (kbytes, -d) unlimited -scheduling priority (-e) 0 -file size (blocks, -f) unlimited -pending signals (-i) 515072 -max locked memory (kbytes, -l) 64 -max memory size (kbytes, -m) unlimited -open files (-n) 524288 -pipe size (512 bytes, -p) 8 -POSIX message queues (bytes, -q) 819200 -real-time priority (-r) 0 -stack size (kbytes, -s) unlimited -cpu time (seconds, -t) unlimited -max user processes (-u) 515072 -virtual memory (kbytes, -v) unlimited -file locks (-x) unlimited - -SECTION_SYSCONF -_SC_THREAD_SAFE_FUNCTIONS= 200809 -_SC_CLK_TCK= 100 -_SC_OPEN_MAX= 524288 -_SC_PAGE_SIZE= 4096 -_SC_ARG_MAX= 4611686018427387903 -_SC_CHILD_MAX= 515072 -_SC_LINE_MAX= 2048 - -SECTION_FULL_COMMAND -/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl - -SECTION_CPUINFO diff --git a/synthDC/crte_000057185.txt b/synthDC/crte_000057185.txt deleted file mode 100644 index d99b82eb3..000000000 --- a/synthDC/crte_000057185.txt +++ /dev/null @@ -1,67 +0,0 @@ -CRTE_SNAPSHOT_START - -SECTION_CRTE_VERSION -3.0 - -SECTION_PID -57185 - -SECTION_POLLING_INTERVAL -5 - -SECTION_DATE_TIME -Mon May 16 22:54:26 UTC 2022 (1652741666) - -SECTION_OS_VERSION -osname: Linux -hostname: tera -arch: x86_64 -release_version: 5.4.157-1-pve - -SECTION_IPC_INFO - ------- Message Queues -------- -key msqid owner perms used-bytes messages - ------- Shared Memory Segments -------- -key shmid owner perms bytes nattch status -0x00000000 15859713 nwhyte-agu 600 524288 2 dest -0x00000000 360451 nwhyte-agu 600 524288 2 dest -0x00000000 65540 kkim 600 134217728 2 dest -0x00000000 557061 nwhyte-agu 600 67108864 2 dest -0x00000000 6 harris 600 524288 2 dest -0x00000000 7 harris 600 524288 2 dest -0x00000000 5275656 harris 600 2097152 2 dest -0x00000000 11993097 kkim 600 524288 2 dest -0x00000000 15892490 kkim 600 524288 2 dest -0x00000000 11 harris 600 524288 2 SECTION_ULIMIT -core file size (blocks, -c) 0 -data seg size (kbytes, -d) unlimited -scheduling priority (-e) 0 -file size (blocks, -f) unlimited -pending signals (-i) 515072 -max locked memory (kbytes, -l) 64 -max memory size (kbytes, -m) unlimited -open files (-n) 524288 -pipe size (512 bytes, -p) 8 -POSIX message queues (bytes, -q) 819200 -real-time priority (-r) 0 -stack size (kbytes, -s) unlimited -cpu time (seconds, -t) unlimited -max user processes (-u) 515072 -virtual memory (kbytes, -v) unlimited -file locks (-x) unlimited - -SECTION_SYSCONF -_SC_THREAD_SAFE_FUNCTIONS= 200809 -_SC_CLK_TCK= 100 -_SC_OPEN_MAX= 524288 -_SC_PAGE_SIZE= 4096 -_SC_ARG_MAX= 4611686018427387903 -_SC_CHILD_MAX= 515072 -_SC_LINE_MAX= 2048 - -SECTION_FULL_COMMAND -/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl - -SECTION_CPUINFO diff --git a/synthDC/ppa.py b/synthDC/ppa.py new file mode 100755 index 000000000..4d1657771 --- /dev/null +++ b/synthDC/ppa.py @@ -0,0 +1,64 @@ +#!/usr/bin/python3 +# from msilib.schema import File +import subprocess +from multiprocessing import Pool +import csv +import re +# import matplotlib.pyplot as plt +# import numpy as np + +print("hi") + +def run_command(module, width, freq): + command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq) + subprocess.Popen(command, shell=True) + +widths = ['16'] +modules = ['shifter'] +freqs = ['10'] + + +LoT = [] +for module in modules: + for width in widths: + for freq in freqs: + LoT += [[module, width, freq]] + +pool = Pool() +pool.starmap(run_command, LoT) +pool.close() + +bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" +outputCPL = subprocess.check_output(['bash','-c', bashCommand]) +linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] + +bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" +outputDA = subprocess.check_output(['bash','-c', bashCommand]) +linesDA = outputDA.decode("utf-8").split('\n')[:-1] + +cpl = re.compile('\d{1}\.\d{6}') +f = re.compile('_\d*_MHz') +wm = re.compile('ppa_\w*_\d*_qor') +da = re.compile('\d*\.\d{6}') + +allSynths = [] + +for i in range(len(linesCPL)): + line = linesCPL[i] + oneSynth = [] + mwm = wm.findall(line)[0][4:-4].split('_') + oneSynth += [mwm[0]] + oneSynth += [mwm[1]] + oneSynth += [f.findall(line)[0][1:-4]] + oneSynth += cpl.findall(line) + oneSynth += da.findall(linesDA[i]) + allSynths += [oneSynth] + +file = open("ppaData.csv", "w") +writer = csv.writer(file) +writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) + +for one in allSynths: + writer.writerow(one) + +file.close() \ No newline at end of file diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py deleted file mode 100755 index fef78921a..000000000 --- a/synthDC/ppaAnalyze.py +++ /dev/null @@ -1,95 +0,0 @@ -#!/usr/bin/python3 -import subprocess -import csv -import re -import matplotlib.pyplot as plt -import numpy as np - -def getData(): - bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" - outputCPL = subprocess.check_output(['bash','-c', bashCommand]) - linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] - - bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" - outputDA = subprocess.check_output(['bash','-c', bashCommand]) - linesDA = outputDA.decode("utf-8").split('\n')[:-1] - - cpl = re.compile('\d{1}\.\d{6}') - f = re.compile('_\d*_MHz') - wm = re.compile('ppa_\w*_\d*_qor') - da = re.compile('\d*\.\d{6}') - - allSynths = [] - - for i in range(len(linesCPL)): - line = linesCPL[i] - mwm = wm.findall(line)[0][4:-4].split('_') - oneSynth = [mwm[0], int(mwm[1])] - oneSynth += [int(f.findall(line)[0][1:-4])] - oneSynth += [float(cpl.findall(line)[0])] - oneSynth += [float(da.findall(linesDA[i])[0])] - allSynths += [oneSynth] - - return allSynths - -def writeCSV(allSynths): - file = open("ppaData.csv", "w") - writer = csv.writer(file) - writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) - - for one in allSynths: - writer.writerow(one) - - file.close() - -def plotPPA(module, freq, var): - ''' - module: string module name - freq: int freq (GHz) - var: string 'delay' or 'area' - plots chosen variable vs width for all matching syntheses with regression - ''' - global allSynths - ind = 3 if (var == 'delay') else 4 - widths = [] - ivar = [] - for oneSynth in allSynths: - if (oneSynth[0] == module) & (oneSynth[2] == freq): - - widths += [oneSynth[1]] - ivar += [oneSynth[ind]] - - x = np.array(widths, dtype=np.int) - y = np.array(ivar, dtype=np.float) - - A = np.vstack([x, np.ones(len(x))]).T - m, c = np.linalg.lstsq(A, y, rcond=None)[0] - - z = np.polyfit(x, y, 2) - p = np.poly1d(z) - - zlog = np.polyfit(np.log(x), y, 1) - plog = np.poly1d(zlog) - - xp = np.linspace(0, 140, 200) - xplog = np.log(xp) - - _ = plt.plot(x, y, 'o', label=module, markersize=10) - _ = plt.plot(x, m*x + c, 'r', label='Linear fit') - _ = plt.plot(xp, p(xp), label='Quadratic fit') - _ = plt.plot(xp, plog(xplog), label = 'Log fit') - _ = plt.legend() - _ = plt.xlabel("Width (bits)") - _ = plt.ylabel(str.title(var)) - _ = plt.title("Target frequency " + str(freq)) - plt.show() -#fix square microns, picosec, end plots at 8 to stop negs, add equation to plots and R2 -# try linear term with delay as well (w and wo) - -allSynths = getData() - -writeCSV(allSynths) - -plotPPA('mult', 5000, 'delay') -plotPPA('mult', 5000, 'area') -plotPPA('mult', 10, 'area') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index d5232bb4e..368547c60 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,38 +1,28 @@ Module,Width,Target Freq,Delay,Area -add,128,10,7.100851,1867.879976 -add,128,5000,0.389771,7007.980119 add,16,10,2.032906,221.479998 -add,16,4000,0.249839,551.74001 +add,16,4000,0.249839,551.740010 add,16,5000,0.228259,924.140017 add,16,6000,0.225754,1120.140018 add,32,10,4.160501,456.679995 add,32,4000,0.280842,1730.680031 -add,32,5000,0.2505,1933.540033 -add,32,6000,0.271774,1746.36003 +add,32,5000,0.250500,1933.540033 +add,32,6000,0.271774,1746.360030 add,64,10,8.474034,927.079988 add,64,4000,0.323267,3758.300065 add,64,5000,0.334061,3798.480071 add,64,6000,0.328457,3749.480066 -add,8,10,0.940062,103.879999 -add,8,5000,0.199689,197.960003 -comparator,128,10,0.842074,1997.240039 -comparator,128,5000,0.260142,5215.56005 comparator,16,10,0.576329,252.840005 comparator,16,4000,0.249312,280.280005 comparator,16,5000,0.199026,313.600006 comparator,16,6000,0.166568,422.380007 -comparator,32,10,0.765874,495.88001 -comparator,32,4000,0.24995,608.580012 +comparator,32,10,0.765874,495.880010 +comparator,32,4000,0.249950,608.580012 comparator,32,5000,0.205372,919.240014 -comparator,32,6000,0.2012,1248.520016 -comparator,64,10,0.561562,1008.42002 +comparator,32,6000,0.201200,1248.520016 +comparator,64,10,0.561562,1008.420020 comparator,64,4000,0.249905,1437.660027 comparator,64,5000,0.219296,2738.120023 comparator,64,6000,0.221138,2341.220025 -comparator,8,10,0.29577,118.580002 -comparator,8,5000,0.195502,129.360003 -mult,128,10,9.334627,180734.540854 -mult,128,5000,1.78322,314617.244472 mult,16,10,4.730546,3869.040009 mult,16,4000,0.821111,9132.620147 mult,16,5000,0.820059,9583.420143 @@ -41,16 +31,11 @@ mult,32,10,7.575772,12412.680067 mult,32,4000,1.091389,31262.980534 mult,32,5000,1.092153,31497.200524 mult,32,6000,1.084816,33519.920555 -mult,64,10,4.7933,46798.920227 +mult,64,10,4.793300,46798.920227 mult,64,4000,1.411752,93087.261425 mult,64,5000,1.404875,94040.801492 mult,64,6000,1.415466,89931.661403 -mult,8,10,2.076433,1009.399998 -mult,8,5000,0.552339,4261.040075 -shifter,128,10,2.577935,8113.420158 -shifter,128,5000,0.395847,16602.180268 -shifter,16,10,0.0,0.0 -shifter,16,10,0.0,0.0 +shifter,16,10,0.000000,0.000000 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 @@ -63,5 +48,3 @@ shifter,32,5000,0.238962,4985.260077 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 -shifter,8,10,0.0,0.0 -shifter,8,5000,0.0,0.0 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py deleted file mode 100755 index 654d77391..000000000 --- a/synthDC/ppaSynth.py +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/python3 -import subprocess -from multiprocessing import Pool - - -def runCommand(module, width, tech, freq): - command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq) - subprocess.Popen(command, shell=True) - -def deleteRedundant(LoT): - '''removes any previous runs for the current synthesis specifications''' - synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}nm_{}_*" - for synth in LoT: - bashCommand = synthStr.format(*synth) - outputCPL = subprocess.check_output(['bash','-c', bashCommand]) - -widths = ['128'] -modules = ['mult'] -freqs = ['5000'] -tech = 'sky90' - -#to run: add 8 10, shifter 8 16 (check .sv!) - -LoT = [] -for module in modules: - for width in widths: - for freq in freqs: - LoT += [[module, width, tech, freq]] - -deleteRedundant(LoT) - -pool = Pool() -pool.starmap(runCommand, LoT) -pool.close() - -bashCommand = "wait" -outputCPL = subprocess.check_output(['bash','-c', bashCommand]) \ No newline at end of file diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 368e45f3a..9d6aac68a 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -137,10 +137,6 @@ if {$tech == "sky130"} { # Set the wire load model set_wire_load_mode "top" -# Set switching activities -# default activity factors are 1 for clocks, 0.1 for others -# static probability of 0.5 is used for leakage - # Attempt Area Recovery - if looking for minimal area # set_max_area 2000 @@ -363,4 +359,4 @@ redirect $filename { report_constraint } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] # redirect $filename { report_hierarchy } -#quit +quit From 29bc8d6902d61e17f8ecd0b012e348cbb7430eaf Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 16:57:00 -0700 Subject: [PATCH 15/38] Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main"" This reverts commit c15aab9c6f0921b20ba34cf9802198e84837da00. reverted the wrong commit --- pipelined/src/ppa/ppa.sv | 80 +- pipelined/srt/Makefile | 4 +- pipelined/srt/lint-srt | 1 - pipelined/srt/srt.do | 2 +- pipelined/srt/srt.sv | 17 +- pipelined/srt/srt_stanford.sv | 8 +- pipelined/srt/testbench.sv | 92 +- pipelined/srt/testgen.c | 3 +- pipelined/srt/testvectors | 1078 +++++++++++++++++------- synthDC/Synopsys_stack_trace_12580.txt | 17 + synthDC/Synopsys_stack_trace_32764.txt | 17 + synthDC/Synopsys_stack_trace_57184.txt | 17 + synthDC/Synopsys_stack_trace_57185.txt | 17 + synthDC/crte_000012580.txt | 67 ++ synthDC/crte_000032764.txt | 67 ++ synthDC/crte_000057184.txt | 67 ++ synthDC/crte_000057185.txt | 67 ++ synthDC/ppa.py | 64 -- synthDC/ppaAnalyze.py | 95 +++ synthDC/ppaData.csv | 35 +- synthDC/ppaSynth.py | 37 + synthDC/scripts/synth.tcl | 6 +- 22 files changed, 1390 insertions(+), 468 deletions(-) create mode 100644 synthDC/Synopsys_stack_trace_12580.txt create mode 100644 synthDC/Synopsys_stack_trace_32764.txt create mode 100644 synthDC/Synopsys_stack_trace_57184.txt create mode 100644 synthDC/Synopsys_stack_trace_57185.txt create mode 100644 synthDC/crte_000012580.txt create mode 100644 synthDC/crte_000032764.txt create mode 100644 synthDC/crte_000057184.txt create mode 100644 synthDC/crte_000057185.txt delete mode 100755 synthDC/ppa.py create mode 100755 synthDC/ppaAnalyze.py create mode 100755 synthDC/ppaSynth.py diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 01e06bb71..03b004f69 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -3,6 +3,14 @@ // & mmasserfrye@hmc.edu // Measure PPA of various building blocks +module ppa_comparator_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -27,6 +35,14 @@ module ppa_comparator_64 #(parameter WIDTH=64) ( ppa_comparator #(WIDTH) comp (.*); endmodule +module ppa_comparator_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -45,6 +61,13 @@ module ppa_comparator #(parameter WIDTH=16) ( assign flags = {eq, lt}; endmodule +module ppa_add_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + module ppa_add_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] y); @@ -66,6 +89,19 @@ module ppa_add_64 #(parameter WIDTH=64) ( assign y = a + b; endmodule +module ppa_add_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_mult_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_mult_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH*2-1:0] y); //is this right width @@ -84,6 +120,12 @@ module ppa_mult_64 #(parameter WIDTH=64) ( assign y = a * b; endmodule +module ppa_mult_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_alu_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, B, input logic [2:0] ALUControl, @@ -180,6 +222,15 @@ module ppa_shiftleft #(parameter WIDTH=32) ( assign y = a << amt; endmodule +module ppa_shifter_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -207,6 +258,15 @@ module ppa_shifter_64 #(parameter WIDTH=64) ( ppa_shifter #(WIDTH) sh (.*); endmodule +module ppa_shifter_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -221,14 +281,7 @@ module ppa_shifter #(parameter WIDTH=32) ( // For RV64, 32 and 64-bit shifts are needed, with sign extension. // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (WIDTH==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 + if (WIDTH == 64) begin:shifter // RV64 fix what about 128 always_comb // funnel mux if (W64) begin // 32-bit shifts if (Right) @@ -241,8 +294,15 @@ module ppa_shifter #(parameter WIDTH=32) ( else z = {63'b0, A}; else z = {A, 63'b0}; end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift - end + end else begin:shifter // RV32, + always_comb // funnel mux + if (Right) + if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + else z = {{WIDTH-1{1'b0}}, A}; + else z = {A, {WIDTH-1{1'b0}}}; + assign amttrunc = Amt; // shift amount + end + assign amttrunc = (W64 & WIDTH==64) ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift fix // opposite offset for right shfits assign offset = Right ? amttrunc : ~amttrunc; diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index db5a11f86..73a0b75fa 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -3,5 +3,5 @@ all: sqrttestgen testgen sqrttestgen: sqrttestgen.c gcc sqrttestgen.c -lm -o sqrttestgen -testgen: exptestgen.c - gcc exptestgen.c -lm -o exptestgen +testgen: testgen.c + gcc testgen.c -lm -o testgen diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt index 3599cdff5..399201be0 100755 --- a/pipelined/srt/lint-srt +++ b/pipelined/srt/lint-srt @@ -1,2 +1 @@ verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv -verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv diff --git a/pipelined/srt/srt.do b/pipelined/srt/srt.do index b4d9bb138..8be358057 100644 --- a/pipelined/srt/srt.do +++ b/pipelined/srt/srt.do @@ -17,7 +17,7 @@ if [file exists work] { } vlib work -vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv +vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv vopt +acc work.testbench -o workopt vsim workopt diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 81d9e2f25..044bac9c1 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -37,8 +37,6 @@ module srt #(parameter Nf=52) ( input logic Flush, // *** multiple pipe stages // Floating Point Inputs // later add exponents, signs, special cases - input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits - // end of floating point inputs input logic [Nf-1:0] SrcXFrac, SrcYFrac, input logic [`XLEN-1:0] SrcA, SrcB, input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit @@ -47,7 +45,6 @@ module srt #(parameter Nf=52) ( input logic Int, // Choose integer inputss input logic Sqrt, // perform square root, not divide output logic [Nf-1:0] Quot, Rem, // *** later handle integers - output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision output logic [3:0] Flags ); @@ -81,9 +78,6 @@ module srt #(parameter Nf=52) ( // Partial Product Generation csa csa(WS, WC, Dsel, qp, WSA, WCA); - // Exponent division - exp exp(SrcXExpE, SrcYExpE, Exp); - srtpostproc postproc(rp, rm, Quot); endmodule @@ -92,9 +86,8 @@ module srtpostproc #(parameter N=52) ( output [N-1:0] Quot ); - // replace with on-the-fly conversion //assign Quot = rp - rm; - finaladd finaladd(rp, rm, Quot); + finaladd finaladd(rp, rm, Quot); endmodule module srtpreproc #(parameter Nf=52) ( @@ -254,14 +247,6 @@ module csa #(parameter N=56) ( (in2[54:0] & in3[54:0]), cin}; endmodule -////////////// -// exponent // -////////////// -module exp(input [10:0] e1, e2, - output [10:0] e); // for double precision, exponent is 11 bits - assign e = (e1 - e2) + 11'd1023; // bias is hardcoded -endmodule - ////////////// // finaladd // ////////////// diff --git a/pipelined/srt/srt_stanford.sv b/pipelined/srt/srt_stanford.sv index 23ab683d5..ce0417f56 100644 --- a/pipelined/srt/srt_stanford.sv +++ b/pipelined/srt/srt_stanford.sv @@ -11,9 +11,7 @@ // This Verilog file models a radix 2 SRT divider which // produces one quotient digit per cycle. The divider // keeps the partial remainder in carry-save form. - -`include "wally-config.vh" - + ///////// // srt // ///////// @@ -328,9 +326,7 @@ module testbench; begin req <= #5 1; $display("result was %h, should be %h\n", r, correctr); - //if (abs(correctr - r) > 1) // check if accurate to 1 ulp - // giving error "srt_stanford.sv(395): (vopt-7063) Failed to find 'abs' in hierarchical name 'abs'." - if (correctr - r > 1) // check if accurate to 1 ulp + if ((correctr - r) > 1) // check if accurate to 1 ulp begin errors = errors+1; $display("failed\n"); diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 9985a89cf..0af3821ec 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,7 +1,7 @@ ///////////// -// divcounter // +// counter // ///////////// -module divcounter(input logic clk, +module counter(input logic clk, input logic req, output logic done); @@ -36,76 +36,40 @@ endmodule ////////// // testbench // ////////// - -/* verilator lint_off STMTDLY */ -/* verilator lint_off INFINITELOOP */ module testbench; logic clk; logic req; logic done; - logic [63:0] a; - logic [63:0] b; - logic [63:0] result; - logic [51:0] r; + logic [51:0] a; + logic [51:0] b; + logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits - logic [10:0] e; // output exponent - // input logic for Unpacker - // input logic [63:0] X, Y, Z, - numbers - // input logic FmtE, ---- format, 1 is for double precision, 0 is single - // input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide - // all variables are commented in fpu.sv - - // output logic from Unpacker - logic XSgnE, YSgnE, ZSgnE; - logic [10:0] XExpE, YExpE, ZExpE; // exponent - logic [52:0] XManE, YManE, ZManE; - logic XNormE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; // denormals - logic XZeroE, YZeroE, ZZeroE; - logic [10:0] BiasE; // currrently hardcoded, will probs be removed - logic XInfE, YInfE, ZInfE; - logic XExpMaxE; // says exponent is all ones, can ignore - // Test parameters - parameter MEM_SIZE = 60000; - parameter MEM_WIDTH = 64+64+64; + parameter MEM_SIZE = 40000; + parameter MEM_WIDTH = 52+52+52; - `define memr 63:0 - `define memb 127:64 - `define mema 191:128 + `define memr 51:0 + `define memb 103:52 + `define mema 155:104 // Test logicisters logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a // bit field of an array - logic [63:0] correctr, nextr, diffn, diffp; + logic [51:0] correctr, nextr, diffn, diffp; integer testnum, errors; - // Unpacker - // Note: BiasE will probably get taken out eventually - unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), - .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), - .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), - .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), - .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), - .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); - // Divider srt #(52) srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), - .SrcXExpE(XExpE), .SrcYExpE(YExpE), - .SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]), + .SrcXFrac(a), .SrcYFrac(b), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .Rem(), .Exp(e), .Flags()); + .Quot(r), .Rem(), .Flags()); - assign result = {1'b0, e, r}; - - // Divcounter - divcounter divcounter(clk, req, done); + // Counter + counter counter(clk, req, done); initial @@ -126,7 +90,7 @@ module testbench; a = Vec[`mema]; b = Vec[`memb]; nextr = Vec[`memr]; - req = #5 1; + req <= #5 1; end // Apply directed test vectors read from file. @@ -135,19 +99,17 @@ module testbench; begin if (done) begin - req = #5 1; - diffp = correctr - result; - diffn = result - correctr; + req <= #5 1; + diffp = correctr - r; + diffn = r - correctr; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; - $display("a = %h b = %h result = %h",a,b,correctr); - $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp); - $display("at fail"); + $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); $display("failed\n"); $stop; end - if (a === 64'hxxxxxxxxxxxxxxxx) + if (a === 52'hxxxxxxxxxxxxx) begin $display("%d Tests completed successfully", testnum); $stop; @@ -155,20 +117,16 @@ module testbench; end if (req) begin - req = #5 0; + req <= #5 0; correctr = nextr; - $display("pre increment"); testnum = testnum+1; - a = Vec[`mema]; - b = Vec[`memb]; Vec = Tests[testnum]; - $display("a = %h b = %h result = %h",a,b,nextr); + $display("a = %h b = %h",a,b); + a = Vec[`mema]; + b = Vec[`memb]; nextr = Vec[`memr]; - $display("after increment"); end end endmodule -/* verilator lint_on STMTDLY */ -/* verilator lint_on INFINITELOOP */ diff --git a/pipelined/srt/testgen.c b/pipelined/srt/testgen.c index 143ef058f..98d52819b 100644 --- a/pipelined/srt/testgen.c +++ b/pipelined/srt/testgen.c @@ -28,7 +28,7 @@ double random_input(void); void main(void) { FILE *fptr; - double x1, x2, a, b, r; + double a, b, r; double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -63,7 +63,6 @@ void main(void) void output(FILE *fptr, double a, double b, double r) { - printhex(fptr, a); fprintf(fptr, "_"); printhex(fptr, b); diff --git a/pipelined/srt/testvectors b/pipelined/srt/testvectors index c6412a9e6..112803fe9 100644 --- a/pipelined/srt/testvectors +++ b/pipelined/srt/testvectors @@ -1,289 +1,789 @@ -4000000000000000_4000000000000000_3ff0000000000000 -4018000000000000_4000000000000000_4008000000000000 -4024000000000000_4000000000000000_4014000000000000 -4032000000000000_4000000000000000_4022000000000000 -4041000000000000_4000000000000000_4031000000000000 -405c000000000000_4000000000000000_404c000000000000 -406e000000000000_4000000000000000_405e000000000000 -407ffff583a53b8e_4000000000000000_406ffff583a53b8e -408199999999999a_4000000000000000_407199999999999a -4093333333333333_4000000000000000_4083333333333333 -40a028f5c28f5c29_4000000000000000_409028f5c28f5c29 -40b004189374bc6a_4000000000000000_40a004189374bc6a -40c00068db8bac71_4000000000000000_40b00068db8bac71 -40dd1745d1745d17_4000000000000000_40cd1745d1745d17 -40e5555555555555_4000000000000000_40d5555555555555 -40f999999999999a_4000000000000000_40e999999999999a -410c71c71c71c71c_4000000000000000_40fc71c71c71c71c -4000000000000000_4018000000000000_3fe5555555555555 -4018000000000000_4018000000000000_3ff0000000000000 -4024000000000000_4018000000000000_400aaaaaaaaaaaab -4032000000000000_4018000000000000_4018000000000000 -4041000000000000_4018000000000000_4026aaaaaaaaaaab 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+388a7114e229c_5202a405480a9_d96b8ce030793 +5112a225444a8_71c8e391c7239_d2b5183c88cc1 +2b485690ad216_ba017402e805d_5aad01f0f330a +0130026004c01_e1edc3db87b71_113c45ac1389f +abf757eeafdd6_7a9af535ea6bd_21604b0e84524 +350c6a18d431a_82c905920b242_9918ede81ed1a +2a8c5518aa315_8cbf197e32fc6_8146816fcd820 +80b3016602cc0_915922b245648_eac2cca581d9f diff --git a/synthDC/Synopsys_stack_trace_12580.txt b/synthDC/Synopsys_stack_trace_12580.txt new file mode 100644 index 000000000..ca9522e03 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_12580.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 12580 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_32764.txt b/synthDC/Synopsys_stack_trace_32764.txt new file mode 100644 index 000000000..f845fa3f8 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_32764.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 32764 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57184.txt b/synthDC/Synopsys_stack_trace_57184.txt new file mode 100644 index 000000000..a016d47c4 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_57184.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 57184 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57185.txt b/synthDC/Synopsys_stack_trace_57185.txt new file mode 100644 index 000000000..dec54674a --- /dev/null +++ b/synthDC/Synopsys_stack_trace_57185.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 57185 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/crte_000012580.txt b/synthDC/crte_000012580.txt new file mode 100644 index 000000000..2bc74daac --- /dev/null +++ b/synthDC/crte_000012580.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +12580 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 23:44:09 UTC 2022 (1652744649) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000032764.txt b/synthDC/crte_000032764.txt new file mode 100644 index 000000000..87eaa3c4c --- /dev/null +++ b/synthDC/crte_000032764.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +32764 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Tue May 17 00:05:18 UTC 2022 (1652745918) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 dest +0x00000000 15204364 harris 644 790528 3 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000057184.txt b/synthDC/crte_000057184.txt new file mode 100644 index 000000000..77c41bece --- /dev/null +++ b/synthDC/crte_000057184.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +57184 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 22:54:26 UTC 2022 (1652741666) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000057185.txt b/synthDC/crte_000057185.txt new file mode 100644 index 000000000..d99b82eb3 --- /dev/null +++ b/synthDC/crte_000057185.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +57185 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 22:54:26 UTC 2022 (1652741666) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/ppa.py b/synthDC/ppa.py deleted file mode 100755 index 4d1657771..000000000 --- a/synthDC/ppa.py +++ /dev/null @@ -1,64 +0,0 @@ -#!/usr/bin/python3 -# from msilib.schema import File -import subprocess -from multiprocessing import Pool -import csv -import re -# import matplotlib.pyplot as plt -# import numpy as np - -print("hi") - -def run_command(module, width, freq): - command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq) - subprocess.Popen(command, shell=True) - -widths = ['16'] -modules = ['shifter'] -freqs = ['10'] - - -LoT = [] -for module in modules: - for width in widths: - for freq in freqs: - LoT += [[module, width, freq]] - -pool = Pool() -pool.starmap(run_command, LoT) -pool.close() - -bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" -outputCPL = subprocess.check_output(['bash','-c', bashCommand]) -linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] - -bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" -outputDA = subprocess.check_output(['bash','-c', bashCommand]) -linesDA = outputDA.decode("utf-8").split('\n')[:-1] - -cpl = re.compile('\d{1}\.\d{6}') -f = re.compile('_\d*_MHz') -wm = re.compile('ppa_\w*_\d*_qor') -da = re.compile('\d*\.\d{6}') - -allSynths = [] - -for i in range(len(linesCPL)): - line = linesCPL[i] - oneSynth = [] - mwm = wm.findall(line)[0][4:-4].split('_') - oneSynth += [mwm[0]] - oneSynth += [mwm[1]] - oneSynth += [f.findall(line)[0][1:-4]] - oneSynth += cpl.findall(line) - oneSynth += da.findall(linesDA[i]) - allSynths += [oneSynth] - -file = open("ppaData.csv", "w") -writer = csv.writer(file) -writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) - -for one in allSynths: - writer.writerow(one) - -file.close() \ No newline at end of file diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py new file mode 100755 index 000000000..fef78921a --- /dev/null +++ b/synthDC/ppaAnalyze.py @@ -0,0 +1,95 @@ +#!/usr/bin/python3 +import subprocess +import csv +import re +import matplotlib.pyplot as plt +import numpy as np + +def getData(): + bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] + + bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" + outputDA = subprocess.check_output(['bash','-c', bashCommand]) + linesDA = outputDA.decode("utf-8").split('\n')[:-1] + + cpl = re.compile('\d{1}\.\d{6}') + f = re.compile('_\d*_MHz') + wm = re.compile('ppa_\w*_\d*_qor') + da = re.compile('\d*\.\d{6}') + + allSynths = [] + + for i in range(len(linesCPL)): + line = linesCPL[i] + mwm = wm.findall(line)[0][4:-4].split('_') + oneSynth = [mwm[0], int(mwm[1])] + oneSynth += [int(f.findall(line)[0][1:-4])] + oneSynth += [float(cpl.findall(line)[0])] + oneSynth += [float(da.findall(linesDA[i])[0])] + allSynths += [oneSynth] + + return allSynths + +def writeCSV(allSynths): + file = open("ppaData.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) + + for one in allSynths: + writer.writerow(one) + + file.close() + +def plotPPA(module, freq, var): + ''' + module: string module name + freq: int freq (GHz) + var: string 'delay' or 'area' + plots chosen variable vs width for all matching syntheses with regression + ''' + global allSynths + ind = 3 if (var == 'delay') else 4 + widths = [] + ivar = [] + for oneSynth in allSynths: + if (oneSynth[0] == module) & (oneSynth[2] == freq): + + widths += [oneSynth[1]] + ivar += [oneSynth[ind]] + + x = np.array(widths, dtype=np.int) + y = np.array(ivar, dtype=np.float) + + A = np.vstack([x, np.ones(len(x))]).T + m, c = np.linalg.lstsq(A, y, rcond=None)[0] + + z = np.polyfit(x, y, 2) + p = np.poly1d(z) + + zlog = np.polyfit(np.log(x), y, 1) + plog = np.poly1d(zlog) + + xp = np.linspace(0, 140, 200) + xplog = np.log(xp) + + _ = plt.plot(x, y, 'o', label=module, markersize=10) + _ = plt.plot(x, m*x + c, 'r', label='Linear fit') + _ = plt.plot(xp, p(xp), label='Quadratic fit') + _ = plt.plot(xp, plog(xplog), label = 'Log fit') + _ = plt.legend() + _ = plt.xlabel("Width (bits)") + _ = plt.ylabel(str.title(var)) + _ = plt.title("Target frequency " + str(freq)) + plt.show() +#fix square microns, picosec, end plots at 8 to stop negs, add equation to plots and R2 +# try linear term with delay as well (w and wo) + +allSynths = getData() + +writeCSV(allSynths) + +plotPPA('mult', 5000, 'delay') +plotPPA('mult', 5000, 'area') +plotPPA('mult', 10, 'area') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 368547c60..d5232bb4e 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,28 +1,38 @@ Module,Width,Target Freq,Delay,Area +add,128,10,7.100851,1867.879976 +add,128,5000,0.389771,7007.980119 add,16,10,2.032906,221.479998 -add,16,4000,0.249839,551.740010 +add,16,4000,0.249839,551.74001 add,16,5000,0.228259,924.140017 add,16,6000,0.225754,1120.140018 add,32,10,4.160501,456.679995 add,32,4000,0.280842,1730.680031 -add,32,5000,0.250500,1933.540033 -add,32,6000,0.271774,1746.360030 +add,32,5000,0.2505,1933.540033 +add,32,6000,0.271774,1746.36003 add,64,10,8.474034,927.079988 add,64,4000,0.323267,3758.300065 add,64,5000,0.334061,3798.480071 add,64,6000,0.328457,3749.480066 +add,8,10,0.940062,103.879999 +add,8,5000,0.199689,197.960003 +comparator,128,10,0.842074,1997.240039 +comparator,128,5000,0.260142,5215.56005 comparator,16,10,0.576329,252.840005 comparator,16,4000,0.249312,280.280005 comparator,16,5000,0.199026,313.600006 comparator,16,6000,0.166568,422.380007 -comparator,32,10,0.765874,495.880010 -comparator,32,4000,0.249950,608.580012 +comparator,32,10,0.765874,495.88001 +comparator,32,4000,0.24995,608.580012 comparator,32,5000,0.205372,919.240014 -comparator,32,6000,0.201200,1248.520016 -comparator,64,10,0.561562,1008.420020 +comparator,32,6000,0.2012,1248.520016 +comparator,64,10,0.561562,1008.42002 comparator,64,4000,0.249905,1437.660027 comparator,64,5000,0.219296,2738.120023 comparator,64,6000,0.221138,2341.220025 +comparator,8,10,0.29577,118.580002 +comparator,8,5000,0.195502,129.360003 +mult,128,10,9.334627,180734.540854 +mult,128,5000,1.78322,314617.244472 mult,16,10,4.730546,3869.040009 mult,16,4000,0.821111,9132.620147 mult,16,5000,0.820059,9583.420143 @@ -31,11 +41,16 @@ mult,32,10,7.575772,12412.680067 mult,32,4000,1.091389,31262.980534 mult,32,5000,1.092153,31497.200524 mult,32,6000,1.084816,33519.920555 -mult,64,10,4.793300,46798.920227 +mult,64,10,4.7933,46798.920227 mult,64,4000,1.411752,93087.261425 mult,64,5000,1.404875,94040.801492 mult,64,6000,1.415466,89931.661403 -shifter,16,10,0.000000,0.000000 +mult,8,10,2.076433,1009.399998 +mult,8,5000,0.552339,4261.040075 +shifter,128,10,2.577935,8113.420158 +shifter,128,5000,0.395847,16602.180268 +shifter,16,10,0.0,0.0 +shifter,16,10,0.0,0.0 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 @@ -48,3 +63,5 @@ shifter,32,5000,0.238962,4985.260077 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 +shifter,8,10,0.0,0.0 +shifter,8,5000,0.0,0.0 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py new file mode 100755 index 000000000..654d77391 --- /dev/null +++ b/synthDC/ppaSynth.py @@ -0,0 +1,37 @@ +#!/usr/bin/python3 +import subprocess +from multiprocessing import Pool + + +def runCommand(module, width, tech, freq): + command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq) + subprocess.Popen(command, shell=True) + +def deleteRedundant(LoT): + '''removes any previous runs for the current synthesis specifications''' + synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}nm_{}_*" + for synth in LoT: + bashCommand = synthStr.format(*synth) + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + +widths = ['128'] +modules = ['mult'] +freqs = ['5000'] +tech = 'sky90' + +#to run: add 8 10, shifter 8 16 (check .sv!) + +LoT = [] +for module in modules: + for width in widths: + for freq in freqs: + LoT += [[module, width, tech, freq]] + +deleteRedundant(LoT) + +pool = Pool() +pool.starmap(runCommand, LoT) +pool.close() + +bashCommand = "wait" +outputCPL = subprocess.check_output(['bash','-c', bashCommand]) \ No newline at end of file diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 9d6aac68a..368e45f3a 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -137,6 +137,10 @@ if {$tech == "sky130"} { # Set the wire load model set_wire_load_mode "top" +# Set switching activities +# default activity factors are 1 for clocks, 0.1 for others +# static probability of 0.5 is used for leakage + # Attempt Area Recovery - if looking for minimal area # set_max_area 2000 @@ -359,4 +363,4 @@ redirect $filename { report_constraint } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] # redirect $filename { report_hierarchy } -quit +#quit From 73d19b095642d4ed7e200231b0beb3fc7325c8d3 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 16:57:29 -0700 Subject: [PATCH 16/38] Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression" This reverts commit 83e4ab711cc4f66fc0cde311aa9bf7ca35431812. unbroke wally --- pipelined/src/ieu/datapath.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 068beb1c3..90b5f0335 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -88,7 +88,7 @@ module datapath ( logic [`XLEN-1:0] IFResultW; // Decode stage - assign Rs1D = InstrD[18:14]; // Broke this, it should be 19 to 15. + assign Rs1D = InstrD[19:15]; assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); From 0dea11fc73b9dda6ecbf513774d314d156ec478e Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 17:03:16 -0700 Subject: [PATCH 17/38] broke it again but this time it doesn't compile due to a missing semicolon on Rs1D. --- pipelined/src/ieu/datapath.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 90b5f0335..5a205d286 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -88,7 +88,7 @@ module datapath ( logic [`XLEN-1:0] IFResultW; // Decode stage - assign Rs1D = InstrD[19:15]; + assign Rs1D = InstrD[19:15] assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); From 36ea0f91268bac92b5706c073eb5ef3eabbc0430 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 17:05:11 -0700 Subject: [PATCH 18/38] Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D." This reverts commit 0dea11fc73b9dda6ecbf513774d314d156ec478e. fixed it --- pipelined/src/ieu/datapath.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 5a205d286..90b5f0335 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -88,7 +88,7 @@ module datapath ( logic [`XLEN-1:0] IFResultW; // Decode stage - assign Rs1D = InstrD[19:15] + assign Rs1D = InstrD[19:15]; assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); From 910475ea56da4ea2b0f3cc87febf514dbae795f0 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 17:22:09 -0700 Subject: [PATCH 19/38] same as last breaking commit, testing if the bisect works to output a breaking commit. --- pipelined/src/ieu/datapath.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 90b5f0335..5a205d286 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -88,7 +88,7 @@ module datapath ( logic [`XLEN-1:0] IFResultW; // Decode stage - assign Rs1D = InstrD[19:15]; + assign Rs1D = InstrD[19:15] assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); From ebeebf3bfcc3d8b4d081b4776ed164517a5b8ab1 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 17:26:33 -0700 Subject: [PATCH 20/38] Revert "same as last breaking commit, testing if the bisect works to output a breaking commit." This reverts commit 910475ea56da4ea2b0f3cc87febf514dbae795f0. gottem --- pipelined/src/ieu/datapath.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 5a205d286..90b5f0335 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -88,7 +88,7 @@ module datapath ( logic [`XLEN-1:0] IFResultW; // Decode stage - assign Rs1D = InstrD[19:15] + assign Rs1D = InstrD[19:15]; assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); From 7cd673fa6e72b2acc56ddc2be3a1e3ee30ba9caf Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 17:29:34 -0700 Subject: [PATCH 21/38] simplified make-tests.sh to run the current makefile in regression --- pipelined/regression/make-tests.sh | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/pipelined/regression/make-tests.sh b/pipelined/regression/make-tests.sh index c5d3644d6..fe4555ff2 100755 --- a/pipelined/regression/make-tests.sh +++ b/pipelined/regression/make-tests.sh @@ -1,14 +1,16 @@ #!/bin/bash rm -r work* -cd ../../tests/imperas-riscv-tests/ make allclean make -cd ../wally-riscv-arch-test -make allclean -make -make XLEN=32 -exe2memfile.pl work/*/*/*.elf -cd ../linux-testgen/linux-testvectors -./tvLinker.sh -cd ../../../pipelined/regression +# cd ../../tests/imperas-riscv-tests/ +# make allclean +# make +# cd ../wally-riscv-arch-test +# make allclean +# make +# make XLEN=32 +# exe2memfile.pl work/*/*/*.elf +# cd ../linux-testgen/linux-testvectors +# ./tvLinker.sh +# cd ../../../pipelined/regression From 0265d1988e8583c66e89976b4b6978bb47cde2f5 Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Wed, 18 May 2022 16:08:40 +0000 Subject: [PATCH 22/38] adapted shifter in ppa.sv for widths beside 32 and 64 modified plotting and regression in ppaAnalyze.py --- pipelined/src/ppa/ppa.sv | 19 +++--- synthDC/ppaAnalyze.py | 126 +++++++++++++++++++++++++++++---------- synthDC/ppaFitting.csv | 10 ++++ synthDC/ppaSynth.py | 7 +-- 4 files changed, 118 insertions(+), 44 deletions(-) create mode 100644 synthDC/ppaFitting.csv diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 03b004f69..96b2581bc 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -281,20 +281,21 @@ module ppa_shifter #(parameter WIDTH=32) ( // For RV64, 32 and 64-bit shifts are needed, with sign extension. // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (WIDTH == 64) begin:shifter // RV64 fix what about 128 + if (WIDTH == 64 | WIDTH ==128) begin:shifter // RV64 or 128 always_comb // funnel mux if (W64) begin // 32-bit shifts if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; + if (Arith) z = {{WIDTH{1'b0}}, {WIDTH/2 -1{A[WIDTH/2 -1]}}, A[WIDTH/2 -1:0]}; + else z = {{WIDTH*3/2-1{1'b0}}, A[WIDTH/2 -1:0]}; + else z = {{WIDTH/2{1'b0}}, A[WIDTH/2 -1:0], {WIDTH-1{1'b0}}}; end else begin if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; + if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + else z = {{WIDTH-1{1'b0}}, A}; + else z = {A, {WIDTH-1{1'b0}}}; end - end else begin:shifter // RV32, + assign amttrunc = W64 ? {1'b0, Amt[$clog2(WIDTH)-2:0]} : Amt; // 32 or 64-bit shift + end else begin:shifter // RV32 or less always_comb // funnel mux if (Right) if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; @@ -302,7 +303,7 @@ module ppa_shifter #(parameter WIDTH=32) ( else z = {A, {WIDTH-1{1'b0}}}; assign amttrunc = Amt; // shift amount end - assign amttrunc = (W64 & WIDTH==64) ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift fix + // opposite offset for right shfits assign offset = Right ? amttrunc : ~amttrunc; diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index fef78921a..9dc7399f7 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -3,6 +3,7 @@ import subprocess import csv import re import matplotlib.pyplot as plt +import matplotlib.lines as lines import numpy as np def getData(): @@ -32,6 +33,23 @@ def getData(): return allSynths +def getVals(module, freq, var): + global allSynths + if (var == 'delay'): + ind = 3 + units = " (ps)" + else: + ind = 4 + units = " (square microns)" + + widths = [] + ivar = [] + for oneSynth in allSynths: + if (oneSynth[0] == module) & (oneSynth[2] == freq): + widths += [oneSynth[1]] + ivar += [oneSynth[ind]] + return widths, ivar, units + def writeCSV(allSynths): file = open("ppaData.csv", "w") writer = csv.writer(file) @@ -42,6 +60,17 @@ def writeCSV(allSynths): file.close() +def polyfitR2(x, y, deg): + ''' from internet, check math''' + z = np.polyfit(x, y, deg) + p = np.poly1d(z) + yhat = p(x) # or [p(z) for z in x] + ybar = np.sum(y)/len(y) # or sum(y)/len(y) + ssreg = np.sum((yhat-ybar)**2) # or sum([ (yihat - ybar)**2 for yihat in yhat]) + sstot = np.sum((y - ybar)**2) # or sum([ (yi - ybar)**2 for yi in y]) + r2 = ssreg / sstot + return p, r2 + def plotPPA(module, freq, var): ''' module: string module name @@ -49,47 +78,82 @@ def plotPPA(module, freq, var): var: string 'delay' or 'area' plots chosen variable vs width for all matching syntheses with regression ''' - global allSynths - ind = 3 if (var == 'delay') else 4 - widths = [] - ivar = [] - for oneSynth in allSynths: - if (oneSynth[0] == module) & (oneSynth[2] == freq): - - widths += [oneSynth[1]] - ivar += [oneSynth[ind]] - x = np.array(widths, dtype=np.int) - y = np.array(ivar, dtype=np.float) + # A = np.vstack([x, np.ones(len(x))]).T + # mcresid = np.linalg.lstsq(A, y, rcond=None) + # m, c = mcresid[0] + # resid = mcresid[1] + # r2 = 1 - resid / (y.size * y.var()) + # p, r2p = polyfitR2(x, y, 2) + # zlog = np.polyfit(np.log(x), y, 1) + # plog = np.poly1d(zlog) + # xplog = np.log(xp) + # _ = plt.plot(x, m*x + c, 'r', label='Linear fit R^2='+ str(r2)[1:7]) + # _ = plt.plot(xp, p(xp), label='Quadratic fit R^2='+ str(r2p)[:6]) + # _ = plt.plot(xp, plog(xplog), label = 'Log fit') - A = np.vstack([x, np.ones(len(x))]).T - m, c = np.linalg.lstsq(A, y, rcond=None)[0] + widths, ivar, units = getVals(module, freq, var) + coefs, r2 = regress(widths, ivar) - z = np.polyfit(x, y, 2) - p = np.poly1d(z) + xp = np.linspace(8, 140, 200) + pred = [coefs[0] + x*coefs[1] + np.log(x)*coefs[2] + x*np.log(x)*coefs[3] for x in xp] - zlog = np.polyfit(np.log(x), y, 1) - plog = np.poly1d(zlog) + r2p = round(r2[0], 4) + rcoefs = [round(c, 3) for c in coefs] - xp = np.linspace(0, 140, 200) - xplog = np.log(xp) + l = "{} + {}*N + {}*log(N) + {}*Nlog(N)".format(*rcoefs) + legend_elements = [lines.Line2D([0], [0], color='steelblue', label=module), + lines.Line2D([0], [0], color='orange', label=l), + lines.Line2D([0], [0], ls='', label=' R^2='+ str(r2p))] - _ = plt.plot(x, y, 'o', label=module, markersize=10) - _ = plt.plot(x, m*x + c, 'r', label='Linear fit') - _ = plt.plot(xp, p(xp), label='Quadratic fit') - _ = plt.plot(xp, plog(xplog), label = 'Log fit') - _ = plt.legend() + _ = plt.plot(widths, ivar, 'o', label=module, markersize=10) + _ = plt.plot(xp, pred) + _ = plt.legend(handles=legend_elements) _ = plt.xlabel("Width (bits)") - _ = plt.ylabel(str.title(var)) - _ = plt.title("Target frequency " + str(freq)) + _ = plt.ylabel(str.title(var) + units) + _ = plt.title("Target frequency " + str(freq) + "MHz") plt.show() -#fix square microns, picosec, end plots at 8 to stop negs, add equation to plots and R2 -# try linear term with delay as well (w and wo) + +def makePlots(mod): + plotPPA(mod, 5000, 'delay') + plotPPA(mod, 5000, 'area') + plotPPA(mod, 10, 'area') + +def regress(widths, var): + + mat = [] + for w in widths: + row = [1, w, np.log(w), w*np.log(w)] + mat += [row] + + y = np.array(var, dtype=np.float) + coefsResid = np.linalg.lstsq(mat, y, rcond=None) + coefs = coefsResid[0] + resid = coefsResid[1] + r2 = 1 - resid / (y.size * y.var()) + return coefs, r2 + +def makeCoefTable(): + file = open("ppaFitting.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Variable', 'Freq', '1', 'N', 'log(N)', 'Nlog(N)', 'R^2']) + + for mod in ['add', 'mult', 'comparator']: + for comb in [['delay', 5000], ['area', 5000], ['area', 10]]: + var = comb[0] + freq = comb[1] + widths, ivar, units = getVals(mod, freq, var) + coefs, r2 = regress(widths, ivar) + row = [mod] + comb + np.ndarray.tolist(coefs) + [r2[0]] + writer.writerow(row) + + file.close() allSynths = getData() writeCSV(allSynths) -plotPPA('mult', 5000, 'delay') -plotPPA('mult', 5000, 'area') -plotPPA('mult', 10, 'area') \ No newline at end of file +makePlots('shifter') + +# makeCoefTable() + diff --git a/synthDC/ppaFitting.csv b/synthDC/ppaFitting.csv new file mode 100644 index 000000000..58a3d036c --- /dev/null +++ b/synthDC/ppaFitting.csv @@ -0,0 +1,10 @@ +Module,Variable,Freq,1,N,log(N),Nlog(N),R^2 +add,delay,5000,0.23935453005464438,0.015973094945355207,-0.058207695467226296,-0.002593789781151714,0.9902532112478974 +add,area,5000,-1032.1274349672115,64.4386855922132,374.6678949053879,-3.2579193244904823,0.9999180068922152 +add,area,10,-13.720004131149423,14.699999256147343,3.6067390521177815e-06,9.312480709428003e-08,1.0 +mult,delay,5000,-0.21755360109289562,-0.00033127390710363004,0.36865114245083547,0.0004100845872014472,0.9999815499619515 +mult,area,5000,-29928.193338752997,-11370.538120558254,39122.3984379376,2592.313970431163,0.9998454828501703 +mult,area,10,-24112.991162714883,-8735.874000034026,30452.017533199683,1892.3032427172166,0.9999575675635335 +comparator,delay,5000,0.18302939890710385,-0.001793523907103751,0.00950014684425352,0.0004195522734073458,0.9999387049502957 +comparator,area,5000,1831.2076391201958,303.59984869227907,-1617.4342555852443,-44.475154143873425,0.9990603962758624 +comparator,area,10,-0.23027509289593326,18.299023530396347,-8.48304611908023,-0.4881808064440773,0.9999674500675539 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py index 654d77391..b2479fed3 100755 --- a/synthDC/ppaSynth.py +++ b/synthDC/ppaSynth.py @@ -14,12 +14,11 @@ def deleteRedundant(LoT): bashCommand = synthStr.format(*synth) outputCPL = subprocess.check_output(['bash','-c', bashCommand]) -widths = ['128'] -modules = ['mult'] -freqs = ['5000'] +widths = ['8', '16', '32', '64', '128'] +modules = ['shifter'] +freqs = ['10', '5000'] tech = 'sky90' -#to run: add 8 10, shifter 8 16 (check .sv!) LoT = [] for module in modules: From 1442afe4e2f00b6b8c125cb30c737a2c98e36216 Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Wed, 18 May 2022 17:01:55 +0000 Subject: [PATCH 23/38] added support for plotting and fitting power --- pipelined/src/ppa/ppa.sv | 2 +- synthDC/ppaAnalyze.py | 32 ++++++++-- synthDC/ppaData.csv | 134 +++++++++++++++++++-------------------- synthDC/ppaFitting.csv | 5 +- synthDC/ppaSynth.py | 6 +- 5 files changed, 101 insertions(+), 78 deletions(-) diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 96b2581bc..0207c99f7 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -361,7 +361,7 @@ module ppa_decoder #(parameter WIDTH = 8) ( end endmodule -module ppa_mux2 #(parameter WIDTH = 8) ( +module ppa_mux2_1 #(parameter WIDTH = 1) ( input logic [WIDTH-1:0] d0, d1, input logic s, output logic [WIDTH-1:0] y); diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index 9dc7399f7..edad94dd4 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -1,4 +1,5 @@ #!/usr/bin/python3 +from distutils.log import error import subprocess import csv import re @@ -6,6 +7,7 @@ import matplotlib.pyplot as plt import matplotlib.lines as lines import numpy as np + def getData(): bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" outputCPL = subprocess.check_output(['bash','-c', bashCommand]) @@ -15,20 +17,28 @@ def getData(): outputDA = subprocess.check_output(['bash','-c', bashCommand]) linesDA = outputDA.decode("utf-8").split('\n')[:-1] + bashCommand = "grep '100' runs/ppa_*/reports/*power*" + outputP = subprocess.check_output(['bash','-c', bashCommand]) + linesP = outputP.decode("utf-8").split('\n')[:-1] + cpl = re.compile('\d{1}\.\d{6}') f = re.compile('_\d*_MHz') wm = re.compile('ppa_\w*_\d*_qor') da = re.compile('\d*\.\d{6}') + p = re.compile('\d+\.\d+[e-]*\d+') allSynths = [] for i in range(len(linesCPL)): line = linesCPL[i] mwm = wm.findall(line)[0][4:-4].split('_') + power = p.findall(linesP[i]) oneSynth = [mwm[0], int(mwm[1])] oneSynth += [int(f.findall(line)[0][1:-4])] oneSynth += [float(cpl.findall(line)[0])] oneSynth += [float(da.findall(linesDA[i])[0])] + oneSynth += [float(power[1])] + oneSynth += [float(power[2])] allSynths += [oneSynth] return allSynths @@ -38,9 +48,17 @@ def getVals(module, freq, var): if (var == 'delay'): ind = 3 units = " (ps)" - else: + elif (var == 'area'): ind = 4 - units = " (square microns)" + units = " (sq microns)" + elif (var == 'dpower'): + ind = 5 + units = " (mW)" + elif (var == 'lpower'): + ind = 6 + units = " (nW)" + else: + error widths = [] ivar = [] @@ -53,7 +71,7 @@ def getVals(module, freq, var): def writeCSV(allSynths): file = open("ppaData.csv", "w") writer = csv.writer(file) - writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) + writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area', 'D Power (mW)', 'L Power (nW)']) for one in allSynths: writer.writerow(one) @@ -118,6 +136,8 @@ def makePlots(mod): plotPPA(mod, 5000, 'delay') plotPPA(mod, 5000, 'area') plotPPA(mod, 10, 'area') + plotPPA(mod, 5000, 'lpower') + plotPPA(mod, 5000, 'dpower') def regress(widths, var): @@ -136,9 +156,9 @@ def regress(widths, var): def makeCoefTable(): file = open("ppaFitting.csv", "w") writer = csv.writer(file) - writer.writerow(['Module', 'Variable', 'Freq', '1', 'N', 'log(N)', 'Nlog(N)', 'R^2']) + writer.writerow(['Module', 'Metric', 'Freq', '1', 'N', 'log(N)', 'Nlog(N)', 'R^2']) - for mod in ['add', 'mult', 'comparator']: + for mod in ['add', 'mult', 'comparator', 'shifter']: for comb in [['delay', 5000], ['area', 5000], ['area', 10]]: var = comb[0] freq = comb[1] @@ -155,5 +175,5 @@ writeCSV(allSynths) makePlots('shifter') -# makeCoefTable() +makeCoefTable() diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index d5232bb4e..3ea5648b6 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,67 +1,67 @@ -Module,Width,Target Freq,Delay,Area -add,128,10,7.100851,1867.879976 -add,128,5000,0.389771,7007.980119 -add,16,10,2.032906,221.479998 -add,16,4000,0.249839,551.74001 -add,16,5000,0.228259,924.140017 -add,16,6000,0.225754,1120.140018 -add,32,10,4.160501,456.679995 -add,32,4000,0.280842,1730.680031 -add,32,5000,0.2505,1933.540033 -add,32,6000,0.271774,1746.36003 -add,64,10,8.474034,927.079988 -add,64,4000,0.323267,3758.300065 -add,64,5000,0.334061,3798.480071 -add,64,6000,0.328457,3749.480066 -add,8,10,0.940062,103.879999 -add,8,5000,0.199689,197.960003 -comparator,128,10,0.842074,1997.240039 -comparator,128,5000,0.260142,5215.56005 -comparator,16,10,0.576329,252.840005 -comparator,16,4000,0.249312,280.280005 -comparator,16,5000,0.199026,313.600006 -comparator,16,6000,0.166568,422.380007 -comparator,32,10,0.765874,495.88001 -comparator,32,4000,0.24995,608.580012 -comparator,32,5000,0.205372,919.240014 -comparator,32,6000,0.2012,1248.520016 -comparator,64,10,0.561562,1008.42002 -comparator,64,4000,0.249905,1437.660027 -comparator,64,5000,0.219296,2738.120023 -comparator,64,6000,0.221138,2341.220025 -comparator,8,10,0.29577,118.580002 -comparator,8,5000,0.195502,129.360003 -mult,128,10,9.334627,180734.540854 -mult,128,5000,1.78322,314617.244472 -mult,16,10,4.730546,3869.040009 -mult,16,4000,0.821111,9132.620147 -mult,16,5000,0.820059,9583.420143 -mult,16,6000,0.831308,8594.600132 -mult,32,10,7.575772,12412.680067 -mult,32,4000,1.091389,31262.980534 -mult,32,5000,1.092153,31497.200524 -mult,32,6000,1.084816,33519.920555 -mult,64,10,4.7933,46798.920227 -mult,64,4000,1.411752,93087.261425 -mult,64,5000,1.404875,94040.801492 -mult,64,6000,1.415466,89931.661403 -mult,8,10,2.076433,1009.399998 -mult,8,5000,0.552339,4261.040075 -shifter,128,10,2.577935,8113.420158 -shifter,128,5000,0.395847,16602.180268 -shifter,16,10,0.0,0.0 -shifter,16,10,0.0,0.0 -shifter,32,10,1.906335,1656.200032 -shifter,32,10,1.906335,1656.200032 -shifter,32,10,1.906335,1656.200032 -shifter,32,4000,0.260606,3490.760054 -shifter,32,4000,0.260606,3490.760054 -shifter,32,4000,0.260606,3490.760054 -shifter,32,5000,0.238962,4985.260077 -shifter,32,5000,0.238962,4985.260077 -shifter,32,5000,0.238962,4985.260077 -shifter,32,6000,0.241742,4312.000069 -shifter,32,6000,0.241742,4312.000069 -shifter,32,6000,0.241742,4312.000069 -shifter,8,10,0.0,0.0 -shifter,8,5000,0.0,0.0 +Module,Width,Target Freq,Delay,Area,D Power (mW),L Power (nW) +add,128,10,7.100851,1867.879976,0.00501,465.925 +add,128,5000,0.389771,7007.980119,3.309,2.77 +add,16,10,2.032906,221.479998,0.000575,55.29 +add,16,4000,0.249839,551.74001,0.239,302.479 +add,16,5000,0.228259,924.140017,0.519,641.631 +add,16,6000,0.225754,1120.140018,0.739,1.01 +add,32,10,4.160501,456.679995,0.00118,112.161 +add,32,4000,0.280842,1730.680031,0.735,849.828 +add,32,5000,0.2505,1933.540033,1.049,1.03 +add,32,6000,0.271774,1746.36003,1.138,955.901 +add,64,10,8.474034,927.079988,0.00246,230.083 +add,64,4000,0.323267,3758.300065,1.523,1.75 +add,64,5000,0.334061,3798.480071,1.917,2.18 +add,64,6000,0.328457,3749.480066,2.346,1.77 +add,8,10,0.940062,103.879999,0.000241,24.765 +add,8,5000,0.199689,197.960003,0.113,83.576 +comparator,128,10,0.842074,1997.240039,0.00087,243.506 +comparator,128,5000,0.260142,5215.56005,3.708,6.0 +comparator,16,10,0.576329,252.840005,0.000144,31.402 +comparator,16,4000,0.249312,280.280005,0.0581,55.248 +comparator,16,5000,0.199026,313.600006,0.0859,78.893 +comparator,16,6000,0.166568,422.380007,0.255,301.506 +comparator,32,10,0.765874,495.88001,0.000226,66.41 +comparator,32,4000,0.24995,608.580012,0.168,130.613 +comparator,32,5000,0.205372,919.240014,0.43,840.47 +comparator,32,6000,0.2012,1248.520016,0.928,1.48 +comparator,64,10,0.561562,1008.42002,0.000449,127.626 +comparator,64,4000,0.249905,1437.660027,0.462,558.66 +comparator,64,5000,0.219296,2738.120023,1.989,2.95 +comparator,64,6000,0.221138,2341.220025,1.343,2.59 +comparator,8,10,0.29577,118.580002,6.83e-05,16.053 +comparator,8,5000,0.195502,129.360003,0.0358,21.443 +mult,128,10,9.334627,180734.540854,0.428,1.8 +mult,128,5000,1.78322,314617.244472,997.34,1.63 +mult,16,10,4.730546,3869.040009,0.0107,641.517 +mult,16,4000,0.821111,9132.620147,14.407,8.03 +mult,16,5000,0.820059,9583.420143,20.175,8.5 +mult,16,6000,0.831308,8594.600132,21.106,7.15 +mult,32,10,7.575772,12412.680067,0.0229,1.18 +mult,32,4000,1.091389,31262.980534,65.471,2.49 +mult,32,5000,1.092153,31497.200524,79.554,2.58 +mult,32,6000,1.084816,33519.920555,103.798,2.91 +mult,64,10,4.7933,46798.920227,0.103,5.46 +mult,64,4000,1.411752,93087.261425,227.876,6.05 +mult,64,5000,1.404875,94040.801492,298.667,6.16 +mult,64,6000,1.415466,89931.661403,337.302,5.63 +mult,8,10,2.076433,1009.399998,0.00206,211.637 +mult,8,5000,0.552339,4261.040075,5.543,5.05 +mux2,1,10,0.060639,6.86,5.15e-06,1.19 +mux2,1,10,0.060639,6.86,5.15e-06,1.19 +shifter,128,10,2.758726,9722.580189,0.00789,720.698 +shifter,128,5000,0.401118,19106.080347,6.94,1.23 +shifter,16,10,1.237745,681.100013,0.000441,52.029 +shifter,16,5000,0.209586,2120.720031,1.025,2.15 +shifter,32,10,1.906335,1656.200032,0.00115,118.773 +shifter,32,4000,0.260606,3490.760054,1.282,2.57 +shifter,32,4000,0.260606,3490.760054,1.282,2.57 +shifter,32,4000,0.260606,3490.760054,1.282,2.57 +shifter,32,5000,0.238962,4985.260077,2.489,4.9 +shifter,32,6000,0.241742,4312.000069,2.411,3.71 +shifter,32,6000,0.241742,4312.000069,2.411,3.71 +shifter,32,6000,0.241742,4312.000069,2.411,3.71 +shifter,64,10,2.919486,4346.300085,0.00297,210.734 +shifter,64,5000,0.358993,9471.700156,4.518,6.94 +shifter,8,10,0.622998,244.020005,0.00019,26.943 +shifter,8,5000,0.198885,495.88001,0.285,300.128 diff --git a/synthDC/ppaFitting.csv b/synthDC/ppaFitting.csv index 58a3d036c..882977245 100644 --- a/synthDC/ppaFitting.csv +++ b/synthDC/ppaFitting.csv @@ -1,4 +1,4 @@ -Module,Variable,Freq,1,N,log(N),Nlog(N),R^2 +Module,Metric,Freq,1,N,log(N),Nlog(N),R^2 add,delay,5000,0.23935453005464438,0.015973094945355207,-0.058207695467226296,-0.002593789781151714,0.9902532112478974 add,area,5000,-1032.1274349672115,64.4386855922132,374.6678949053879,-3.2579193244904823,0.9999180068922152 add,area,10,-13.720004131149423,14.699999256147343,3.6067390521177815e-06,9.312480709428003e-08,1.0 @@ -8,3 +8,6 @@ mult,area,10,-24112.991162714883,-8735.874000034026,30452.017533199683,1892.3032 comparator,delay,5000,0.18302939890710385,-0.001793523907103751,0.00950014684425352,0.0004195522734073458,0.9999387049502957 comparator,area,5000,1831.2076391201958,303.59984869227907,-1617.4342555852443,-44.475154143873425,0.9990603962758624 comparator,area,10,-0.23027509289593326,18.299023530396347,-8.48304611908023,-0.4881808064440773,0.9999674500675539 +shifter,delay,5000,0.4107033934426204,0.03923479405737683,-0.19848886911558317,-0.006549393512462493,0.989283342171845 +shifter,area,5000,-3612.7138133224103,-65.6549821150965,1929.186263038338,35.02443853718661,0.9998392000511572 +shifter,area,10,806.0687632950834,120.52125970491868,-682.1783666753405,-5.1440062238735225,0.9998176364985187 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py index b2479fed3..cf7e430b5 100755 --- a/synthDC/ppaSynth.py +++ b/synthDC/ppaSynth.py @@ -14,9 +14,9 @@ def deleteRedundant(LoT): bashCommand = synthStr.format(*synth) outputCPL = subprocess.check_output(['bash','-c', bashCommand]) -widths = ['8', '16', '32', '64', '128'] -modules = ['shifter'] -freqs = ['10', '5000'] +widths = ['1'] +modules = ['mux2'] +freqs = ['10'] tech = 'sky90' From af14c8a06462fda645ced9688e6cc945b17d7b2e Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 18 May 2022 16:50:31 -0700 Subject: [PATCH 24/38] added instructions to slack notifier --- pipelined/regression/slack-notifier/slack-notifier.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/regression/slack-notifier/slack-notifier.py b/pipelined/regression/slack-notifier/slack-notifier.py index 934932671..273299d23 100755 --- a/pipelined/regression/slack-notifier/slack-notifier.py +++ b/pipelined/regression/slack-notifier/slack-notifier.py @@ -8,7 +8,7 @@ if not os.path.isfile(sys.path[0]+'/slack-webhook-url.txt'): print('slack-notifier.py can help let you know when your sim is done.') print('To make it work, please supply your Slack bot webhook URL in:') print(sys.path[0]+'/slack-webhook-url.txt') - print('Ask Ben for the Tera Slack Notifier Tutorial for more details.') + print('Tutorial for slack webhook urls: https://bit.ly/BenSlackNotifier') print('==============================================================') else: urlFile = open(sys.path[0]+'/slack-webhook-url.txt','r') From cc0ab94ebcd0da620704cc154230594918ccc4c6 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 19 May 2022 16:32:30 +0000 Subject: [PATCH 25/38] Added fp tests - doesnpass yet --- addins/riscv-arch-test | 2 +- pipelined/config/rv64fp/wally-config.vh | 5 +- pipelined/regression/fp.do | 52 + pipelined/regression/sim-fp | 11 + pipelined/regression/sim-fp-batch | 10 + pipelined/regression/wave-fpu.do | 102 ++ pipelined/src/fpu/fcvtfp.sv | 2 +- pipelined/src/fpu/fcvtint.sv | 2 +- pipelined/src/fpu/fpu.sv | 4 +- pipelined/src/fpu/unpack.sv | 9 +- pipelined/testbench/testbench-fp.sv | 1538 +++++++++++++++++++++++ pipelined/testbench/tests-fp.vh | 587 +++++++++ 12 files changed, 2312 insertions(+), 12 deletions(-) create mode 100644 pipelined/regression/fp.do create mode 100755 pipelined/regression/sim-fp create mode 100755 pipelined/regression/sim-fp-batch create mode 100644 pipelined/regression/wave-fpu.do create mode 100644 pipelined/testbench/testbench-fp.sv create mode 100644 pipelined/testbench/tests-fp.vh diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..be67c99bd 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index c6f80d497..36cda4d91 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -38,12 +38,13 @@ `define IEEE754 1 // MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +//16 - quad 3 - double 5 - single +`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 +`define ZFH_SUPPORTED 1 /// Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/regression/fp.do b/pipelined/regression/fp.do new file mode 100644 index 000000000..208118fc6 --- /dev/null +++ b/pipelined/regression/fp.do @@ -0,0 +1,52 @@ +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +# $num = the added words after the call +vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv -suppress 2583,7063,8607,2697 + +vsim -voptargs=+acc work.testbenchfp -G TEST=$2 + +view wave +#-- display input and output signals as hexidecimal values +#do ./wave-dos/peripheral-waves.do +#add log -recursive /* +#do wave.do deal with when ready + +do wave-fpu.do + +#-- Run the Simulation +#run 3600 +run -all +noview testbench-fp.sv +view wave + diff --git a/pipelined/regression/sim-fp b/pipelined/regression/sim-fp new file mode 100755 index 000000000..1d6425425 --- /dev/null +++ b/pipelined/regression/sim-fp @@ -0,0 +1,11 @@ + +# cvtint - test integer conversion unit (fcvtint) +# cvtfp - test floating-point conversion unit (fcvtfp) +# cmp - test comparison unit's LT, LE, EQ opperations (fcmp) +# add - test addition +# sub - test subtraction +# div - test division +# sqrt - test square root +# all - test everything + +vsim -do "do fp.do rv64fp mul" diff --git a/pipelined/regression/sim-fp-batch b/pipelined/regression/sim-fp-batch new file mode 100755 index 000000000..7e2c6a341 --- /dev/null +++ b/pipelined/regression/sim-fp-batch @@ -0,0 +1,10 @@ +# cvtint - test integer conversion unit (fcvtint) +# cvtfp - test floating-point conversion unit (fcvtfp) +# cmp - test comparison unit's LT, LE, EQ opperations (fcmp) +# add - test addition +# sub - test subtraction +# div - test division +# sqrt - test square root +# all - test everything + +vsim -c -do "do fp.do rv64fp fma" \ No newline at end of file diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do new file mode 100644 index 000000000..d2ea6d486 --- /dev/null +++ b/pipelined/regression/wave-fpu.do @@ -0,0 +1,102 @@ + +add wave -noupdate /testbenchfp/clk +add wave -noupdate -radix decimal /testbenchfp/VectorNum +add wave -group Other -noupdate /testbenchfp/FrmNum +add wave -group Other -noupdate /testbenchfp/X +add wave -group Other -noupdate /testbenchfp/Y +add wave -group Other -noupdate /testbenchfp/Z +add wave -group Other -noupdate /testbenchfp/Res +add wave -group Other -noupdate /testbenchfp/Ans + +add wave -group Rne -noupdate /testbenchfp/FmaRneX +add wave -group Rne -noupdate /testbenchfp/FmaRneY +add wave -group Rne -noupdate /testbenchfp/FmaRneZ +add wave -group Rne -noupdate /testbenchfp/FmaRneRes +add wave -group Rne -noupdate /testbenchfp/FmaRneAns +add wave -group Rz -noupdate /testbenchfp/FmaRzX +add wave -group Rz -noupdate /testbenchfp/FmaRzY +add wave -group Rz -noupdate /testbenchfp/FmaRzZ +add wave -group Rz -noupdate /testbenchfp/FmaRzRes +add wave -group Rz -noupdate /testbenchfp/FmaRzAns +add wave -group Ru -noupdate /testbenchfp/FmaRuX +add wave -group Ru -noupdate /testbenchfp/FmaRuY +add wave -group Ru -noupdate /testbenchfp/FmaRuZ +add wave -group Ru -noupdate /testbenchfp/FmaRuRes +add wave -group Ru -noupdate /testbenchfp/FmaRuAns +add wave -group Rd -noupdate /testbenchfp/FmaRdX +add wave -group Rd -noupdate /testbenchfp/FmaRdY +add wave -group Rd -noupdate /testbenchfp/FmaRdZ +add wave -group Rd -noupdate /testbenchfp/FmaRdRes +add wave -group Rd -noupdate /testbenchfp/FmaRdAns +add wave -group Rnm -noupdate /testbenchfp/FmaRnmX +add wave -group Rnm -noupdate /testbenchfp/FmaRnmY +add wave -group Rnm -noupdate /testbenchfp/FmaRnmZ +add wave -group Rnm -noupdate /testbenchfp/FmaRnmRes +add wave -group Rnm -noupdate /testbenchfp/FmaRnmAns +add wave -group AllSignals -noupdate /* +add wave -group AllSignals -noupdate /testbenchfp/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/resultselect/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/resultselect/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/resultselect/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/resultselect/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/resultselect/* \ No newline at end of file diff --git a/pipelined/src/fpu/fcvtfp.sv b/pipelined/src/fpu/fcvtfp.sv index fb8e1ad9a..f43d15661 100644 --- a/pipelined/src/fpu/fcvtfp.sv +++ b/pipelined/src/fpu/fcvtfp.sv @@ -1,6 +1,6 @@ `include "wally-config.vh" -module cvtfp ( +module fcvtfp ( input logic [10:0] XExpE, // input's exponent input logic [52:0] XManE, // input's mantissa input logic XSgnE, // input's sign diff --git a/pipelined/src/fpu/fcvtint.sv b/pipelined/src/fpu/fcvtint.sv index 6a6686993..97007d660 100644 --- a/pipelined/src/fpu/fcvtint.sv +++ b/pipelined/src/fpu/fcvtint.sv @@ -2,7 +2,7 @@ `include "wally-config.vh" // `include "../../config/rv64icfd/wally-config.vh" // `define XLEN 64 -module fcvt ( +module fcvtint ( input logic XSgnE, // X's sign input logic [10:0] XExpE, // X's exponent input logic [52:0] XManE, // X's fraction diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 9a78a36b2..7b05b33f2 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -213,12 +213,12 @@ module fpu ( .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); // other FP execution units - cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); + fcvtfp fcvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE); fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE); fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE); - fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, + fcvtint fcvtint (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE); // data to be stored in memory - to IEU diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 1c0589e10..a1d96b8b9 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -2,7 +2,7 @@ module unpack ( input logic [`FLEN-1:0] X, Y, Z, // inputs from register file - input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 10 - double 11 - quad 10 - half + input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) @@ -50,7 +50,6 @@ module unpack ( end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported - //***need better names for these constants // largest format | smaller format //---------------------------------- @@ -339,9 +338,9 @@ module unpack ( ZExpE = {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; // extract the fraction and add the nessesary trailing zeros - XFracE = {XLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; - YFracE = {YLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; - ZFracE = {ZLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; + XFracE = {XLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; + YFracE = {YLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; + ZFracE = {ZLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; // is the exponent non-zero XExpNonzero = |XLen1[`D_LEN-2:`D_NE]; diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv new file mode 100644 index 000000000..42aa7312b --- /dev/null +++ b/pipelined/testbench/testbench-fp.sv @@ -0,0 +1,1538 @@ + +`include "wally-config.vh" +`include "tests-fp.vh" + +// steps to run FMA Tests +// 1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh +// 2) go to riscv-wally/pipelined/testbench/fp/Tests +// 3) run ./sim-fma-batch +//*** drop the any constants in each file and figure out a way to do them without the code +module testbenchfp; + parameter TEST="none"; + + string Tests[]; + logic [2:0] OpCtrl[]; + logic [2:0] Unit[]; + string FmaRneTests[]; + string FmaRuTests[]; + string FmaRdTests[]; + string FmaRzTests[]; + string FmaRnmTests[]; + logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rne, rz, ru, rd, rnm + logic [1:0] Fmt[]; + logic [1:0] FmaFmt[]; + + + logic clk=0; + logic [31:0] TestNum=0; + logic [31:0] OpCtrlNum=0; + logic [31:0] errors=0; + logic [31:0] VectorNum=0; + logic [31:0] FrmNum=0; + logic [31:0] FmaNum=0; + logic [`FLEN*4+7:0] TestVectors[46464:0]; + logic [`FLEN*4+7:0] FmaRneVectors[6133248:0]; + logic [`FLEN*4+7:0] FmaRuVectors[6133248:0]; + logic [`FLEN*4+7:0] FmaRdVectors[6133248:0]; + logic [`FLEN*4+7:0] FmaRzVectors[6133248:0]; + logic [`FLEN*4+7:0] FmaRnmVectors[6133248:0]; + + logic [1:0] FmaFmtVal, FmtVal; + logic [2:0] UnitVal, OpCtrlVal, FrmVal; + logic NaNGood; + logic FmaRneNaNGood, FmaRzNaNGood, FmaRuNaNGood, FmaRdNaNGood, FmaRnmNaNGood; + logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRneX, FmaRneY, FmaRneZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRzX, FmaRzY, FmaRzZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRuX, FmaRuY, FmaRuZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRdX, FmaRdY, FmaRdZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRnmX, FmaRnmY, FmaRnmZ; // inputs read from TestFloat + logic [`XLEN-1:0] SrcA; // integer input + logic [`FLEN-1:0] Ans; // result from TestFloat + logic [`FLEN-1:0] FmaRneAns, FmaRzAns, FmaRuAns, FmaRdAns, FmaRnmAns; // flags read form testfloat + logic [`FLEN-1:0] Res; + logic [`FLEN-1:0] FmaRneRes, FmaRzRes, FmaRuRes, FmaRdRes, FmaRnmRes; // result from Units + logic [4:0] AnsFlags; // flags read form testfloat + logic [4:0] FmaRneAnsFlags, FmaRzAnsFlags, FmaRuAnsFlags, FmaRdAnsFlags, FmaRnmAnsFlags; // flags read form testfloat + logic [4:0] ResFlags; // Res's flags + logic [4:0] FmaRneResFlags, FmaRzResFlags, FmaRuResFlags, FmaRdResFlags, FmaRnmResFlags; // flags read form testfloat + logic [2:0] FrmE; // rounding mode + logic [`FPSIZES/3:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad + logic [3:0] FpuUnit; // Which unit is being tested + logic [`FLEN-1:0] FMAResM, DivResM, CmpResE, CvtResE, CvtFpResE; // Ress + logic [4:0] FMAFlgM, CvtFpFlgM, DivFlgM, CvtIntFlgM, CmpFlgM; // FMA's outputed flags + logic CmpNVE; + logic ResNaN, FmaRneResNaN, FmaRzResNaN, FmaRuResNaN, FmaRdResNaN, FmaRnmResNaN; // is the outputed result NaN + logic AnsNaN, FmaRneAnsNaN, FmaRzAnsNaN, FmaRuAnsNaN, FmaRdAnsNaN, FmaRnmAnsNaN; // is the correct answer NaN + logic [`NE+1:0] ProdExpE, FmaRneProdExp, FmaRzProdExp, FmaRuProdExp, FmaRdProdExp, FmaRnmProdExp; + logic AddendStickyE, FmaRneAddendSticky, FmaRzAddendSticky, FmaRuAddendSticky, FmaRdAddendSticky, FmaRnmAddendSticky; + logic KillProdE, FmaRneKillProd, FmaRzKillProd, FmaRuKillProd, FmaRdKillProd, FmaRnmKillProd; + logic XSgn, YSgn, ZSgn; + logic FmaRneXSgn, FmaRneYSgn, FmaRneZSgn; + logic FmaRzXSgn, FmaRzYSgn, FmaRzZSgn; + logic FmaRuXSgn, FmaRuYSgn, FmaRuZSgn; + logic FmaRdXSgn, FmaRdYSgn, FmaRdZSgn; + logic FmaRnmXSgn, FmaRnmYSgn, FmaRnmZSgn; + logic [`NE-1:0] XExp, YExp, ZExp; + logic [`NE-1:0] FmaRneXExp, FmaRneYExp, FmaRneZExp; + logic [`NE-1:0] FmaRzXExp, FmaRzYExp, FmaRzZExp; + logic [`NE-1:0] FmaRuXExp, FmaRuYExp, FmaRuZExp; + logic [`NE-1:0] FmaRdXExp, FmaRdYExp, FmaRdZExp; + logic [`NE-1:0] FmaRnmXExp, FmaRnmYExp, FmaRnmZExp; + logic [`NF:0] XMan, YMan, ZMan; + logic [`NF:0] FmaRneXMan, FmaRneYMan, FmaRneZMan; + logic [`NF:0] FmaRzXMan, FmaRzYMan, FmaRzZMan; + logic [`NF:0] FmaRuXMan, FmaRuYMan, FmaRuZMan; + logic [`NF:0] FmaRdXMan, FmaRdYMan, FmaRdZMan; + logic [`NF:0] FmaRnmXMan, FmaRnmYMan, FmaRnmZMan; + logic XNorm; + logic XExpMaxE; + logic XNaN, YNaN, ZNaN; + logic FmaRneXNaN, FmaRneYNaN, FmaRneZNaN; + logic FmaRzXNaN, FmaRzYNaN, FmaRzZNaN; + logic FmaRuXNaN, FmaRuYNaN, FmaRuZNaN; + logic FmaRdXNaN, FmaRdYNaN, FmaRdZNaN; + logic FmaRnmXNaN, FmaRnmYNaN, FmaRnmZNaN; + logic XSNaN, YSNaN, ZSNaN; + logic FmaRneXSNaN, FmaRneYSNaN, FmaRneZSNaN; + logic FmaRzXSNaN, FmaRzYSNaN, FmaRzZSNaN; + logic FmaRuXSNaN, FmaRuYSNaN, FmaRuZSNaN; + logic FmaRdXSNaN, FmaRdYSNaN, FmaRdZSNaN; + logic FmaRnmXSNaN, FmaRnmYSNaN, FmaRnmZSNaN; + logic XDenorm, YDenorm, ZDenorm; + logic FmaRneXDenorm, FmaRneYDenorm, FmaRneZDenorm; + logic FmaRzXDenorm, FmaRzYDenorm, FmaRzZDenorm; + logic FmaRuXDenorm, FmaRuYDenorm, FmaRuZDenorm; + logic FmaRdXDenorm, FmaRdYDenorm, FmaRdZDenorm; + logic FmaRnmXDenorm, FmaRnmYDenorm, FmaRnmZDenorm; + logic XInf, YInf, ZInf; + logic FmaRneXInf, FmaRneYInf, FmaRneZInf; + logic FmaRzXInf, FmaRzYInf, FmaRzZInf; + logic FmaRuXInf, FmaRuYInf, FmaRuZInf; + logic FmaRdXInf, FmaRdYInf, FmaRdZInf; + logic FmaRnmXInf, FmaRnmYInf, FmaRnmZInf; + logic XZero, YZero, ZZero; + logic FmaRneXZero, FmaRneYZero, FmaRneZZero; + logic FmaRzXZero, FmaRzYZero, FmaRzZZero; + logic FmaRuXZero, FmaRuYZero, FmaRuZZero; + logic FmaRdXZero, FmaRdYZero, FmaRdZZero; + logic FmaRnmXZero, FmaRnmYZero, FmaRnmZZero; + logic XExpMax, YExpMax, ZExpMax, Mult; + logic [3*`NF+5:0] SumE, FmaRneSum, FmaRzSum, FmaRuSum, FmaRdSum, FmaRnmSum; + logic InvZE, FmaRneInvZ, FmaRzInvZ, FmaRuInvZ, FmaRdInvZ, FmaRnmInvZ; + logic NegSumE, FmaRneNegSum, FmaRzNegSum, FmaRuNegSum, FmaRdNegSum, FmaRnmNegSum; + logic ZSgnEffE, FmaRneZSgnEff, FmaRzZSgnEff, FmaRuZSgnEff, FmaRdZSgnEff, FmaRnmZSgnEff; + logic PSgnE, FmaRnePSgn, FmaRzPSgn, FmaRuPSgn, FmaRdPSgn, FmaRnmPSgn; + logic [$clog2(3*`NF+7)-1:0] NormCntE, FmaRneNormCnt, FmaRzNormCnt, FmaRuNormCnt, FmaRdNormCnt, FmaRnmNormCnt; + + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||| ||||||| ||| ||||||| |||||||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||| ||||||| ||| ||||||| |||||||| ||||||||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // select tests relevent to the specified configuration + // cvtint - test integer conversion unit (fcvtint) + // cvtfp - test floating-point conversion unit (fcvtfp) + // cmp - test comparison unit's LT, LE, EQ opperations (fcmp) + // add - test addition + // sub - test subtraction + // div - test division + // sqrt - test square root + // all - test all of the above + initial begin + $display("TEST is %s", TEST); + if (`Q_SUPPORTED) begin // if Quad percision is supported + if (TEST === "cvtint"| TEST === "all") begin // if testing integer conversion + // add the 128-bit cvtint tests to the to-be-tested list + Tests = {Tests, f128rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b11}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions + Tests = {Tests, f128rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if the floating-point conversions are being tested + if(`D_SUPPORTED) begin // if double precision is supported + // add the 128 <-> 64 bit conversions to the to-be-tested list + Tests = {Tests, f128f64cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b01, 3'b11}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if(`F_SUPPORTED) begin // if single precision is supported + // add the 128 <-> 32 bit conversions to the to-be-tested list + Tests = {Tests, f128f32cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b00, 3'b11}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if(`ZFH_SUPPORTED) begin // if half precision is supported + // add the 128 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f128f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b11}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested + // add the compare tests/op-ctrls/unit/fmt + Tests = {Tests, f128cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the addition tests/op-ctrls/unit/fmt + Tests = {Tests, f128add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + // add the subtraction tests/op-ctrls/unit/fmt + Tests = {Tests, f128sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the multiply tests/op-ctrls/unit/fmt + Tests = {Tests, f128mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the divide tests/op-ctrls/unit/fmt + Tests = {Tests, f128div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested + // add the square-root tests/op-ctrls/unit/fmt + Tests = {Tests, f128sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested + // add each rounding mode to it's own list of tests + // - fma tests are very long, so run all rounding modes in parallel + FmaRneTests = {FmaRneTests, "f128_mulAdd_rne.tv"}; + FmaRzTests = {FmaRzTests, "f128_mulAdd_rz.tv"}; + FmaRuTests = {FmaRuTests, "f128_mulAdd_ru.tv"}; + FmaRdTests = {FmaRdTests, "f128_mulAdd_rd.tv"}; + FmaRnmTests = {FmaRnmTests, "f128_mulAdd_rnm.tv"}; + // add the format for the Fma + for(int i = 0; i<5; i++) begin + FmaFmt = {FmaFmt, 2'b11}; + end + end + end + if (`D_SUPPORTED) begin // if double precision is supported + if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested + Tests = {Tests, f64rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b01}; + end + if (`XLEN == 64) begin // if 64-bit integers are being supported + Tests = {Tests, f64rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested + if(`F_SUPPORTED) begin // if single precision is supported + // add the 64 <-> 32 bit conversions to the to-be-tested list + Tests = {Tests, f64f32cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b00, 3'b01}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if(`ZFH_SUPPORTED) begin // if half precision is supported + // add the 64 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f64f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b01}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested + // add each rounding mode to it's own list of tests + // - fma tests are very long, so run all rounding modes in parallel + FmaRneTests = {FmaRneTests, "f64_mulAdd_rne.tv"}; + FmaRzTests = {FmaRzTests, "f64_mulAdd_rz.tv"}; + FmaRuTests = {FmaRuTests, "f64_mulAdd_ru.tv"}; + FmaRdTests = {FmaRdTests, "f64_mulAdd_rd.tv"}; + FmaRnmTests = {FmaRnmTests, "f64_mulAdd_rnm.tv"}; + for(int i = 0; i<5; i++) begin + FmaFmt = {FmaFmt, 2'b01}; + end + end + end + if (`F_SUPPORTED) begin // if single precision being supported + if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested + Tests = {Tests, f32rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b00}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported + Tests = {Tests, f32rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested + if(`ZFH_SUPPORTED) begin + // add the 32 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f32f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b00}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiply is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested + // add each rounding mode to it's own list of tests + // - fma tests are very long, so run all rounding modes in parallel + FmaRneTests = {FmaRneTests, "f32_mulAdd_rne.tv"}; + FmaRzTests = {FmaRzTests, "f32_mulAdd_rz.tv"}; + FmaRuTests = {FmaRuTests, "f32_mulAdd_ru.tv"}; + FmaRdTests = {FmaRdTests, "f32_mulAdd_rd.tv"}; + FmaRnmTests = {FmaRnmTests, "f32_mulAdd_rnm.tv"}; + for(int i = 0; i<5; i++) begin + FmaFmt = {FmaFmt, 2'b00}; + end + end + end + if (`ZFH_SUPPORTED) begin // if half precision supported + if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested + Tests = {Tests, f16rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported + Tests = {Tests, f16rv64cvtint, f16rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested + // add each rounding mode to it's own list of tests + // - fma tests are very long, so run all rounding modes in parallel + FmaRneTests = {FmaRneTests, "f16_mulAdd_rne.tv"}; + FmaRzTests = {FmaRzTests, "f16_mulAdd_rz.tv"}; + FmaRuTests = {FmaRuTests, "f16_mulAdd_ru.tv"}; + FmaRdTests = {FmaRdTests, "f16_mulAdd_rd.tv"}; + FmaRnmTests = {FmaRnmTests, "f16_mulAdd_rnm.tv"}; + for(int i = 0; i<5; i++) begin + FmaFmt = {FmaFmt, 2'b10}; + end + end + end + + // check if nothing is being tested + if (Tests.size() == 0 & FmaRneTests.size() == 0 & FmaRuTests.size() == 0 & FmaRdTests.size() == 0 & FmaRzTests.size() == 0 & FmaRnmTests.size() == 0) begin + $display("TEST %s not supported in this configuration", TEST); + $stop; + end + end + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||||| |||||||| ||||||||| ||||||| ||||||||| |||||||| ||||||| ||||||||| + // ||| ||| ||| ||| ||| || || ||| ||| ||| ||| + // |||||||| |||||||| ||||||||| || || ||| |||||||| ||||||| ||| + // ||| || ||| ||| ||| || || ||| ||| ||| ||| + // ||| ||| |||||||| ||| ||| ||||||| ||| |||||||| ||||||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // Read the first test + initial begin + $display("\n\nRunning %s vectors", Tests[TestNum]); + $readmemh({`PATH, Tests[TestNum]}, TestVectors); + $readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors); + $readmemh({`PATH, FmaRuTests[TestNum]}, FmaRuVectors); + $readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors); + $readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors); + $readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors); + // set the test index to 0 + TestNum = 0; + end + + // set a the signals for all tests + always_comb FmaFmtVal = FmaFmt[FmaNum]; + always_comb UnitVal = Unit[TestNum]; + always_comb FmtVal = Fmt[TestNum]; + always_comb OpCtrlVal = OpCtrl[OpCtrlNum]; + always_comb FrmVal = Frm[FrmNum]; + assign Mult = OpCtrlVal === 3'b100; + + // modify the format signal if only 2 percisions supported + // - 1 for the larger precision + // - 0 for the smaller precision + always_comb begin + if(`FPSIZES/3 === 1) ModFmt = FmtVal; + else ModFmt = FmtVal === `FMT; + if(`FPSIZES/3 === 1) FmaModFmt = FmaFmtVal; + else FmaModFmt = FmaFmtVal === `FMT; + end + + // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlags) from the current test vector + readfmavectors readfmarnevectors (.clk, .Frm(`RNE), .TestVector(FmaRneVectors[VectorNum]), .VectorNum, .Ans(FmaRneAns), .AnsFlags(FmaRneAnsFlags), + .XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn), .FmaNum, + .XExpE(FmaRneXExp), .YExpE(FmaRneYExp), .ZExpE(FmaRneZExp), + .XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan), + .XNaNE(FmaRneXNaN), .YNaNE(FmaRneYNaN), .ZNaNE(FmaRneZNaN), + .XSNaNE(FmaRneXSNaN), .YSNaNE(FmaRneYSNaN), .ZSNaNE(FmaRneZSNaN), + .XDenormE(FmaRneXDenorm), .YDenormE(FmaRneYDenorm), .ZDenormE(FmaRneZDenorm), + .XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero), + .XInfE(FmaRneXInf), .YInfE(FmaRneYInf), .ZInfE(FmaRneZInf), .FmaModFmt, .FmaFmt(FmaFmtVal), + .X(FmaRneX), .Y(FmaRneY), .Z(FmaRneZ)); + readfmavectors readfmarzvectors (.clk, .Frm(`RZ), .TestVector(FmaRzVectors[VectorNum]), .VectorNum, .Ans(FmaRzAns), .AnsFlags(FmaRzAnsFlags), + .XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), .FmaNum, .FmaModFmt, + .XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp), + .XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan), + .XNaNE(FmaRzXNaN), .YNaNE(FmaRzYNaN), .ZNaNE(FmaRzZNaN), + .XSNaNE(FmaRzXSNaN), .YSNaNE(FmaRzYSNaN), .ZSNaNE(FmaRzZSNaN), + .XDenormE(FmaRzXDenorm), .YDenormE(FmaRzYDenorm), .ZDenormE(FmaRzZDenorm), + .XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero), + .XInfE(FmaRzXInf), .YInfE(FmaRzYInf), .ZInfE(FmaRzZInf), .FmaFmt(FmaFmtVal), + .X(FmaRzX), .Y(FmaRzY), .Z(FmaRzZ)); + readfmavectors readfmaruvectors (.clk, .Frm(`RU), .TestVector(FmaRuVectors[VectorNum]), .VectorNum, .Ans(FmaRuAns), .AnsFlags(FmaRuAnsFlags), + .XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), .FmaNum, .FmaModFmt, + .XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp), + .XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan), + .XNaNE(FmaRuXNaN), .YNaNE(FmaRuYNaN), .ZNaNE(FmaRuZNaN), + .XSNaNE(FmaRuXSNaN), .YSNaNE(FmaRuYSNaN), .ZSNaNE(FmaRuZSNaN), + .XDenormE(FmaRuXDenorm), .YDenormE(FmaRuYDenorm), .ZDenormE(FmaRuZDenorm), + .XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero), + .XInfE(FmaRuXInf), .YInfE(FmaRuYInf), .ZInfE(FmaRuZInf), .FmaFmt(FmaFmtVal), + .X(FmaRuX), .Y(FmaRuY), .Z(FmaRuZ)); + readfmavectors readfmardvectors (.clk, .Frm(`RD), .TestVector(FmaRdVectors[VectorNum]), .VectorNum, .Ans(FmaRdAns), .AnsFlags(FmaRdAnsFlags), + .XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), .FmaNum, .FmaModFmt, + .XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp), + .XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan), + .XNaNE(FmaRdXNaN), .YNaNE(FmaRdYNaN), .ZNaNE(FmaRdZNaN), + .XSNaNE(FmaRdXSNaN), .YSNaNE(FmaRdYSNaN), .ZSNaNE(FmaRdZSNaN), + .XDenormE(FmaRdXDenorm), .YDenormE(FmaRdYDenorm), .ZDenormE(FmaRdZDenorm), + .XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero), + .XInfE(FmaRdXInf), .YInfE(FmaRdYInf), .ZInfE(FmaRdZInf), .FmaFmt(FmaFmtVal), + .X(FmaRdX), .Y(FmaRdY), .Z(FmaRdZ)); + readfmavectors readfmarnmvectors (.clk, .Frm(`RNM), .TestVector(FmaRnmVectors[VectorNum]), .VectorNum, .Ans(FmaRnmAns), .AnsFlags(FmaRnmAnsFlags), + .XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), .FmaNum, .FmaModFmt, + .XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp), + .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), + .XNaNE(FmaRnmXNaN), .YNaNE(FmaRnmYNaN), .ZNaNE(FmaRnmZNaN), + .XSNaNE(FmaRnmXSNaN), .YSNaNE(FmaRnmYSNaN), .ZSNaNE(FmaRnmZSNaN), + .XDenormE(FmaRnmXDenorm), .YDenormE(FmaRnmYDenorm), .ZDenormE(FmaRnmZDenorm), + .XZeroE(FmaRnmXZero), .YZeroE(FmaRnmYZero), .ZZeroE(FmaRnmZZero), + .XInfE(FmaRnmXInf), .YInfE(FmaRnmYInf), .ZInfE(FmaRnmZInf), .FmaFmt(FmaFmtVal), + .X(FmaRnmX), .Y(FmaRnmY), .Z(FmaRnmZ)); + readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlags(AnsFlags), .SrcA, + .XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), .Unit (UnitVal), + .XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), .TestNum, .OpCtrl(OpCtrlVal), + .XManE(XMan), .YManE(YMan), .ZManE(ZMan), + .XNaNE(XNaN), .YNaNE(YNaN), .ZNaNE(ZNaN), + .XSNaNE(XSNaN), .YSNaNE(YSNaN), .ZSNaNE(ZSNaN), + .XDenormE(XDenorm), .YDenormE(YDenorm), .ZDenormE(ZDenorm), + .XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero), + .XInfE(XInf), .YInfE(YInf), .ZInfE(ZInf),.XNormE(XNorm), .XExpMaxE(XExpMax), + .X, .Y, .Z); + + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||| ||| ||| ||||||||| + // ||| ||| ||| ||| ||| + // ||| ||| ||| ||| ||| + // ||| ||| ||| ||| ||| + // ||||||| ||||||||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // instantiate devices under test + // - one fma for each precison + // - all the units for the other tests (including fma for add/sub/mul) + fma1 fma1rne(.XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn), + .XExpE(FmaRneXExp), .YExpE(FmaRneYExp), .ZExpE(FmaRneZExp), + .XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan), + .XDenormE(FmaRneXDenorm), .YDenormE(FmaRneYDenorm), .ZDenormE(FmaRneZDenorm), + .XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRneSum), .NegSumE(FmaRneNegSum), .InvZE(FmaRneInvZ), + .NormCntE(FmaRneNormCnt), .ZSgnEffE(FmaRneZSgnEff), .PSgnE(FmaRnePSgn), + .ProdExpE(FmaRneProdExp), .AddendStickyE(FmaRneAddendSticky), .KillProdE(FmaRneSumKillProd)); + fma2 fma2rne(.XSgnM(FmaRneXSgn), .YSgnM(FmaRneYSgn), + .ZExpM(FmaRneZExp), + .XManM(FmaRneXMan), .YManM(FmaRneYMan), .ZManM(FmaRneZMan), + .XNaNM(FmaRneXNaN), .YNaNM(FmaRneYNaN), .ZNaNM(FmaRneZNaN), + .XZeroM(FmaRneXZero), .YZeroM(FmaRneYZero), .ZZeroM(FmaRneZZero), + .XInfM(FmaRneXInf), .YInfM(FmaRneYInf), .ZInfM(FmaRneZInf), + .XSNaNM(FmaRneXSNaN), .YSNaNM(FmaRneYSNaN), .ZSNaNM(FmaRneZSNaN), + .KillProdM(FmaRneSumKillProd), .AddendStickyM(FmaRneAddendSticky), .ProdExpM(FmaRneProdExp), + .SumM((FmaRneSum)), .NegSumM(FmaRneNegSum), .InvZM(FmaRneInvZ), .NormCntM(FmaRneNormCnt), .ZSgnEffM(FmaRneZSgnEff), + .PSgnM(FmaRnePSgn), .FmtM(FmaModFmt), .FrmM(`RNE), + .FMAFlgM(FmaRneResFlags), .FMAResM(FmaRneRes), .Mult(1'b0)); + fma1 fma1rz(.XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), + .XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp), + .XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan), + .XDenormE(FmaRzXDenorm), .YDenormE(FmaRzYDenorm), .ZDenormE(FmaRzZDenorm), + .XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRzSum), .NegSumE(FmaRzNegSum), .InvZE(FmaRzInvZ), + .NormCntE(FmaRzNormCnt), .ZSgnEffE(FmaRzZSgnEff), .PSgnE(FmaRzPSgn), + .ProdExpE(FmaRzProdExp), .AddendStickyE(FmaRzAddendSticky), .KillProdE(FmaRzSumKillProd)); + fma2 fma2rz(.XSgnM(FmaRzXSgn), .YSgnM(FmaRzYSgn), + .ZExpM(FmaRzZExp), + .XManM(FmaRzXMan), .YManM(FmaRzYMan), .ZManM(FmaRzZMan), + .XNaNM(FmaRzXNaN), .YNaNM(FmaRzYNaN), .ZNaNM(FmaRzZNaN), + .XZeroM(FmaRzXZero), .YZeroM(FmaRzYZero), .ZZeroM(FmaRzZZero), + .XInfM(FmaRzXInf), .YInfM(FmaRzYInf), .ZInfM(FmaRzZInf), + .XSNaNM(FmaRzXSNaN), .YSNaNM(FmaRzYSNaN), .ZSNaNM(FmaRzZSNaN), + .KillProdM(FmaRzSumKillProd), .AddendStickyM(FmaRzAddendSticky), .ProdExpM(FmaRzProdExp), + .SumM((FmaRzSum)), .NegSumM(FmaRzNegSum), .InvZM(FmaRzInvZ), .NormCntM(FmaRzNormCnt), .ZSgnEffM(FmaRzZSgnEff), + .PSgnM(FmaRzPSgn), .FmtM(FmaModFmt), .FrmM(`RZ), + .FMAFlgM(FmaRzResFlags), .FMAResM(FmaRzRes), .Mult(1'b0)); + fma1 fma1ru(.XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), + .XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp), + .XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan), + .XDenormE(FmaRuXDenorm), .YDenormE(FmaRuYDenorm), .ZDenormE(FmaRuZDenorm), + .XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRuSum), .NegSumE(FmaRuNegSum), .InvZE(FmaRuInvZ), + .NormCntE(FmaRuNormCnt), .ZSgnEffE(FmaRuZSgnEff), .PSgnE(FmaRuPSgn), + .ProdExpE(FmaRuProdExp), .AddendStickyE(FmaRuAddendSticky), .KillProdE(FmaRuSumKillProd)); + fma2 fma2ru(.XSgnM(FmaRuXSgn), .YSgnM(FmaRuYSgn), + .ZExpM(FmaRuZExp), + .XManM(FmaRuXMan), .YManM(FmaRuYMan), .ZManM(FmaRuZMan), + .XNaNM(FmaRuXNaN), .YNaNM(FmaRuYNaN), .ZNaNM(FmaRuZNaN), + .XZeroM(FmaRuXZero), .YZeroM(FmaRuYZero), .ZZeroM(FmaRuZZero), + .XInfM(FmaRuXInf), .YInfM(FmaRuYInf), .ZInfM(FmaRuZInf), + .XSNaNM(FmaRuXSNaN), .YSNaNM(FmaRuYSNaN), .ZSNaNM(FmaRuZSNaN), + .KillProdM(FmaRuSumKillProd), .AddendStickyM(FmaRuAddendSticky), .ProdExpM(FmaRuProdExp), + .SumM((FmaRuSum)), .NegSumM(FmaRuNegSum), .InvZM(FmaRuInvZ), .NormCntM(FmaRuNormCnt), .ZSgnEffM(FmaRuZSgnEff), + .PSgnM(FmaRuPSgn), .FmtM(FmaModFmt), .FrmM(`RU), + .FMAFlgM(FmaRuResFlags), .FMAResM(FmaRuRes), .Mult(1'b0)); + fma1 fma1rd(.XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), + .XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp), + .XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan), + .XDenormE(FmaRdXDenorm), .YDenormE(FmaRdYDenorm), .ZDenormE(FmaRdZDenorm), + .XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRdSum), .NegSumE(FmaRdNegSum), .InvZE(FmaRdInvZ), + .NormCntE(FmaRdNormCnt), .ZSgnEffE(FmaRdZSgnEff), .PSgnE(FmaRdPSgn), + .ProdExpE(FmaRdProdExp), .AddendStickyE(FmaRdAddendSticky), .KillProdE(FmaRdSumKillProd)); + fma2 fma2rd(.XSgnM(FmaRdXSgn), .YSgnM(FmaRdYSgn), + .ZExpM(FmaRdZExp), + .XManM(FmaRdXMan), .YManM(FmaRdYMan), .ZManM(FmaRdZMan), + .XNaNM(FmaRdXNaN), .YNaNM(FmaRdYNaN), .ZNaNM(FmaRdZNaN), + .XZeroM(FmaRdXZero), .YZeroM(FmaRdYZero), .ZZeroM(FmaRdZZero), + .XInfM(FmaRdXInf), .YInfM(FmaRdYInf), .ZInfM(FmaRdZInf), + .XSNaNM(FmaRdXSNaN), .YSNaNM(FmaRdYSNaN), .ZSNaNM(FmaRdZSNaN), + .KillProdM(FmaRdSumKillProd), .AddendStickyM(FmaRdAddendSticky), .ProdExpM(FmaRdProdExp), + .SumM((FmaRdSum)), .NegSumM(FmaRdNegSum), .InvZM(FmaRdInvZ), .NormCntM(FmaRdNormCnt), .ZSgnEffM(FmaRdZSgnEff), + .PSgnM(FmaRdPSgn), .FmtM(FmaModFmt), .FrmM(`RD), + .FMAFlgM(FmaRdResFlags), .FMAResM(FmaRdRes), .Mult(1'b0)); + fma1 fma1rnm(.XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), + .XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp), + .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), + .XDenormE(FmaRnmXDenorm), .YDenormE(FmaRnmYDenorm), .ZDenormE(FmaRnmZDenorm), + .XZeroE(FmaRnmXZero), .YZeroE(FmaRnmYZero), .ZZeroE(FmaRnmZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRnmSum), .NegSumE(FmaRnmNegSum), .InvZE(FmaRnmInvZ), + .NormCntE(FmaRnmNormCnt), .ZSgnEffE(FmaRnmZSgnEff), .PSgnE(FmaRnmPSgn), + .ProdExpE(FmaRnmProdExp), .AddendStickyE(FmaRnmAddendSticky), .KillProdE(FmaRnmSumKillProd)); + fma2 fma2rnm(.XSgnM(FmaRnmXSgn), .YSgnM(FmaRnmYSgn), + .ZExpM(FmaRnmZExp), + .XManM(FmaRnmXMan), .YManM(FmaRnmYMan), .ZManM(FmaRnmZMan), + .XNaNM(FmaRnmXNaN), .YNaNM(FmaRnmYNaN), .ZNaNM(FmaRnmZNaN), + .XZeroM(FmaRnmXZero), .YZeroM(FmaRnmYZero), .ZZeroM(FmaRnmZZero), + .XInfM(FmaRnmXInf), .YInfM(FmaRnmYInf), .ZInfM(FmaRnmZInf), + .XSNaNM(FmaRnmXSNaN), .YSNaNM(FmaRnmYSNaN), .ZSNaNM(FmaRnmZSNaN), + .KillProdM(FmaRnmSumKillProd), .AddendStickyM(FmaRnmAddendSticky), .ProdExpM(FmaRnmProdExp), + .SumM((FmaRnmSum)), .NegSumM(FmaRnmNegSum), .InvZM(FmaRnmInvZ), .NormCntM(FmaRnmNormCnt), .ZSgnEffM(FmaRnmZSgnEff), + .PSgnM(FmaRnmPSgn), .FmtM(FmaModFmt), .FrmM(`RNM), + .FMAFlgM(FmaRnmResFlags), .FMAResM(FmaRnmRes), .Mult(1'b0)); + fma1 fma1(.XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), + .XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), + .XManE(XMan), .YManE(YMan), .ZManE(ZMan), + .XDenormE(XDenorm), .YDenormE(YDenorm), .ZDenormE(ZDenorm), + .XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero), + .FOpCtrlE(3'b0), .FmtE(ModFmt), .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, + .ProdExpE, .AddendStickyE, .KillProdE); + fma2 fma2(.XSgnM(XSgn), .YSgnM(YSgn), + .ZExpM(ZExp), + .XManM(XMan), .YManM(YMan), .ZManM(ZMan), + .XNaNM(XNaN), .YNaNM(YNaN), .ZNaNM(ZNaN), + .XZeroM(XZero), .YZeroM(YZero), .ZZeroM(ZZero), + .XInfM(XInf), .YInfM(YInf), .ZInfM(ZInf), + .XSNaNM(XSNaN), .YSNaNM(YSNaN), .ZSNaNM(ZSNaN), + .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), + .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(ModFmt), .FrmM(FrmVal), + .FMAFlgM, .FMAResM, .Mult); + // fcvtfp fcvtfp (.XExpE(XExp), .XManE(XMan), .XSgnE(XSgn), .XZeroE(XZero), .XDenormE(XDenorm), .XInfE(XInf), + // .XNaNE(XNaN), .XSNaNE(XSNaN), .FrmE(Frmal), .FmtE(ModFmt), .CvtFpResE, .CvtFpFlgE); + // fcmp fcmp (.FmtE(ModFmt), .FOpCtrlE, .XSgnE(XSgn), .YSgnE(YSgn), .XExpE(XExp), .YExpE(YExp), + // .XManE(XMan), .YManE(YMan), .XZeroE(XZero), .YZeroE(YZero), + // .XNaNE(XNaN), .YNaNE(YNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .FSrcXE(X), .FSrcYE(Y), .CmpNVE, .CmpResE); + // fcvtint fcvtint (.XSgnE(XSgn), .XExpE(XExp), .XManE(XMan), .XZeroE(XZero), .XNaNE(XNaN), .XInfE(XInf), + // .XDenormE(XDenorm), .ForwardedSrcAE(SrcA), .FOpCtrlE, .FmtE(ModFmt), .FrmE(Frmal), + // .CvtResE, .CvtFlgE); + // *** integrade divide and squareroot + // fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmVal[1:0]), .op_type(FOpCtrlQ), + // .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1), + // .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload, + // .FDivBusyE, .done(FDivSqrtDoneE), .AS_Res(FDivResM), .Flags(FDivFlgM)); + + // produce clock + always begin + clk = 1; #5; clk = 0; #5; + end + +/////////////////////////////////////////////////////////////////////////////////////////////// + +// ||||| ||| |||||||||| ||||| ||| +// ||||||| ||| ||| ||| ||||||| ||| +// |||| ||| ||| |||||||||| |||| ||| ||| +// |||| ||| ||| ||| ||| |||| ||| ||| +// |||| ||| ||| ||| ||| |||| ||| ||| +// |||| |||||| ||| ||| |||| |||||| + +/////////////////////////////////////////////////////////////////////////////////////////////// + + //Check if answer is a NaN + always_comb begin + case (FmaFmtVal) + 4'b11: begin // quad + FmaRneAnsNaN = &FmaRneAns[`Q_LEN-2:`Q_NF]&(|FmaRneAns[`Q_NF-1:0]); + FmaRneResNaN = &FmaRneRes[`Q_LEN-2:`Q_NF]&(|FmaRneRes[`Q_NF-1:0]); + FmaRzAnsNaN = &FmaRzAns[`Q_LEN-2:`Q_NF]&(|FmaRzAns[`Q_NF-1:0]); + FmaRzResNaN = &FmaRzRes[`Q_LEN-2:`Q_NF]&(|FmaRzRes[`Q_NF-1:0]); + FmaRuAnsNaN = &FmaRuAns[`Q_LEN-2:`Q_NF]&(|FmaRuAns[`Q_NF-1:0]); + FmaRuResNaN = &FmaRuRes[`Q_LEN-2:`Q_NF]&(|FmaRuRes[`Q_NF-1:0]); + FmaRdAnsNaN = &FmaRdAns[`Q_LEN-2:`Q_NF]&(|FmaRdAns[`Q_NF-1:0]); + FmaRdResNaN = &FmaRdRes[`Q_LEN-2:`Q_NF]&(|FmaRdRes[`Q_NF-1:0]); + FmaRnmAnsNaN = &FmaRnmAns[`Q_LEN-2:`Q_NF]&(|FmaRnmAns[`Q_NF-1:0]); + FmaRnmResNaN = &FmaRnmRes[`Q_LEN-2:`Q_NF]&(|FmaRnmRes[`Q_NF-1:0]); + end + 4'b01: begin // double + FmaRneAnsNaN = &FmaRneAns[`D_LEN-2:`D_NF]&(|FmaRneAns[`D_NF-1:0]); + FmaRneResNaN = &FmaRneRes[`D_LEN-2:`D_NF]&(|FmaRneRes[`D_NF-1:0]); + FmaRzAnsNaN = &FmaRzAns[`D_LEN-2:`D_NF]&(|FmaRzAns[`D_NF-1:0]); + FmaRzResNaN = &FmaRzRes[`D_LEN-2:`D_NF]&(|FmaRzRes[`D_NF-1:0]); + FmaRuAnsNaN = &FmaRuAns[`D_LEN-2:`D_NF]&(|FmaRuAns[`D_NF-1:0]); + FmaRuResNaN = &FmaRuRes[`D_LEN-2:`D_NF]&(|FmaRuRes[`D_NF-1:0]); + FmaRdAnsNaN = &FmaRdAns[`D_LEN-2:`D_NF]&(|FmaRdAns[`D_NF-1:0]); + FmaRdResNaN = &FmaRdRes[`D_LEN-2:`D_NF]&(|FmaRdRes[`D_NF-1:0]); + FmaRnmAnsNaN = &FmaRnmAns[`D_LEN-2:`D_NF]&(|FmaRnmAns[`D_NF-1:0]); + FmaRnmResNaN = &FmaRnmRes[`D_LEN-2:`D_NF]&(|FmaRnmRes[`D_NF-1:0]); + end + 4'b00: begin // single + FmaRneAnsNaN = &FmaRneAns[`S_LEN-2:`S_NF]&(|FmaRneAns[`S_NF-1:0]); + FmaRneResNaN = &FmaRneRes[`S_LEN-2:`S_NF]&(|FmaRneRes[`S_NF-1:0]); + FmaRzAnsNaN = &FmaRzAns[`S_LEN-2:`S_NF]&(|FmaRzAns[`S_NF-1:0]); + FmaRzResNaN = &FmaRzRes[`S_LEN-2:`S_NF]&(|FmaRzRes[`S_NF-1:0]); + FmaRuAnsNaN = &FmaRuAns[`S_LEN-2:`S_NF]&(|FmaRuAns[`S_NF-1:0]); + FmaRuResNaN = &FmaRuRes[`S_LEN-2:`S_NF]&(|FmaRuRes[`S_NF-1:0]); + FmaRdAnsNaN = &FmaRdAns[`S_LEN-2:`S_NF]&(|FmaRdAns[`S_NF-1:0]); + FmaRdResNaN = &FmaRdRes[`S_LEN-2:`S_NF]&(|FmaRdRes[`S_NF-1:0]); + FmaRnmAnsNaN = &FmaRnmAns[`S_LEN-2:`S_NF]&(|FmaRnmAns[`S_NF-1:0]); + FmaRnmResNaN = &FmaRnmRes[`S_LEN-2:`S_NF]&(|FmaRnmRes[`S_NF-1:0]); + end + 4'b10: begin // half + FmaRneAnsNaN = &FmaRneAns[`H_LEN-2:`H_NF]&(|FmaRneAns[`H_NF-1:0]); + FmaRneResNaN = &FmaRneRes[`H_LEN-2:`H_NF]&(|FmaRneRes[`H_NF-1:0]); + FmaRzAnsNaN = &FmaRzAns[`H_LEN-2:`H_NF]&(|FmaRzAns[`H_NF-1:0]); + FmaRzResNaN = &FmaRzRes[`H_LEN-2:`H_NF]&(|FmaRzRes[`H_NF-1:0]); + FmaRuAnsNaN = &FmaRuAns[`H_LEN-2:`H_NF]&(|FmaRuAns[`H_NF-1:0]); + FmaRuResNaN = &FmaRuRes[`H_LEN-2:`H_NF]&(|FmaRuRes[`H_NF-1:0]); + FmaRdAnsNaN = &FmaRdAns[`H_LEN-2:`H_NF]&(|FmaRdAns[`H_NF-1:0]); + FmaRdResNaN = &FmaRdRes[`H_LEN-2:`H_NF]&(|FmaRdRes[`H_NF-1:0]); + FmaRnmAnsNaN = &FmaRnmAns[`H_LEN-2:`H_NF]&(|FmaRnmAns[`H_NF-1:0]); + FmaRnmResNaN = &FmaRnmRes[`H_LEN-2:`H_NF]&(|FmaRnmRes[`H_NF-1:0]); + end + endcase + end + always_comb begin //***need for other units??? + if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin + AnsNaN = 1'b0; + ResNaN = 1'b0; + end + else begin + case (FmtVal) + 4'b11: begin // quad + AnsNaN = &Ans[`FLEN-2:`NF]&(|Ans[`NF-1:0]); + ResNaN = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); + end + 4'b01: begin // double + AnsNaN = &Ans[`LEN1-2:`NF1]&(|Ans[`NF1-1:0]); + ResNaN = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); + end + 4'b00: begin // single + AnsNaN = &Ans[`LEN2-2:`NF2]&(|Ans[`NF2-1:0]); + ResNaN = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]); + end + 4'b10: begin // half + AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); + ResNaN = &FMAResM[`H_LEN-2:`H_NF]&(|FMAResM[`H_NF-1:0]); + end + endcase + end + end + + + // check results on falling edge of clk + always @(negedge clk) begin + case (UnitVal) + `FMAUNIT: Res = FMAResM; + `DIVUNIT: Res = DivResM; + `CMPUNIT: Res = CmpResE; + `CVTINTUNIT: Res = CvtResE; + `CVTFPUNIT: Res = CvtFpResE; + endcase + case (UnitVal) + `FMAUNIT: ResFlags = FMAFlgM; + `DIVUNIT: ResFlags = DivFlgM; + `CMPUNIT: ResFlags = CmpFlgM; + `CVTINTUNIT: ResFlags = CvtIntFlgM; + `CVTFPUNIT: ResFlags = CvtFpFlgM; + endcase + + case (FmaFmtVal) + 4'b11: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRneXNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneX[`Q_LEN-2:`Q_NF],1'b1,FmaRneX[`Q_NF-2:0]})) | + (FmaRneYNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneY[`Q_LEN-2:`Q_NF],1'b1,FmaRneY[`Q_NF-2:0]})) | + (FmaRneZNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneZ[`Q_LEN-2:`Q_NF],1'b1,FmaRneZ[`Q_NF-2:0]}))); + 4'b01: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRneXNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneX[`D_LEN-2:`D_NF],1'b1,FmaRneX[`D_NF-2:0]})) | + (FmaRneYNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneY[`D_LEN-2:`D_NF],1'b1,FmaRneY[`D_NF-2:0]})) | + (FmaRneZNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneZ[`D_LEN-2:`D_NF],1'b1,FmaRneZ[`D_NF-2:0]}))); + 4'b00: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRneXNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneX[`S_LEN-2:`S_NF],1'b1,FmaRneX[`S_NF-2:0]})) | + (FmaRneYNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneY[`S_LEN-2:`S_NF],1'b1,FmaRneY[`S_NF-2:0]})) | + (FmaRneZNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneZ[`S_LEN-2:`S_NF],1'b1,FmaRneZ[`S_NF-2:0]}))); + 4'b10: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRneXNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneX[`H_LEN-2:`H_NF],1'b1,FmaRneX[`H_NF-2:0]})) | + (FmaRneYNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneY[`H_LEN-2:`H_NF],1'b1,FmaRneY[`H_NF-2:0]})) | + (FmaRneZNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneZ[`H_LEN-2:`H_NF],1'b1,FmaRneZ[`H_NF-2:0]}))); + endcase + case (FmaFmtVal) + 4'b11: FmaRzNaNGood = ((FmaRzAnsFlags[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRzXNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzX[`Q_LEN-2:`Q_NF],1'b1,FmaRzX[`Q_NF-2:0]})) | + (FmaRzYNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzY[`Q_LEN-2:`Q_NF],1'b1,FmaRzY[`Q_NF-2:0]})) | + (FmaRzZNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzZ[`Q_LEN-2:`Q_NF],1'b1,FmaRzZ[`Q_NF-2:0]}))); + 4'b01: FmaRzNaNGood = ((FmaRzAnsFlags[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRzXNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzX[`D_LEN-2:`D_NF],1'b1,FmaRzX[`D_NF-2:0]})) | + (FmaRzYNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzY[`D_LEN-2:`D_NF],1'b1,FmaRzY[`D_NF-2:0]})) | + (FmaRzZNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzZ[`D_LEN-2:`D_NF],1'b1,FmaRzZ[`D_NF-2:0]}))); + 4'b00: FmaRzNaNGood = ((FmaRzAnsFlags[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRzXNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzX[`S_LEN-2:`S_NF],1'b1,FmaRzX[`S_NF-2:0]})) | + (FmaRzYNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzY[`S_LEN-2:`S_NF],1'b1,FmaRzY[`S_NF-2:0]})) | + (FmaRzZNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzZ[`S_LEN-2:`S_NF],1'b1,FmaRzZ[`S_NF-2:0]}))); + 4'b10: FmaRzNaNGood = ((FmaRzAnsFlags[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRzXNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzX[`H_LEN-2:`H_NF],1'b1,FmaRzX[`H_NF-2:0]})) | + (FmaRzYNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzY[`H_LEN-2:`H_NF],1'b1,FmaRzY[`H_NF-2:0]})) | + (FmaRzZNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzZ[`H_LEN-2:`H_NF],1'b1,FmaRzZ[`H_NF-2:0]}))); + endcase + case (FmaFmtVal) + 4'b11: FmaRuNaNGood = ((FmaRuAnsFlags[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRuXNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuX[`Q_LEN-2:`Q_NF],1'b1,FmaRuX[`Q_NF-2:0]})) | + (FmaRuYNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuY[`Q_LEN-2:`Q_NF],1'b1,FmaRuY[`Q_NF-2:0]})) | + (FmaRuZNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuZ[`Q_LEN-2:`Q_NF],1'b1,FmaRuZ[`Q_NF-2:0]}))); + 4'b01: FmaRuNaNGood = ((FmaRuAnsFlags[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRuAnsFlags[4]&(FmaRuRes[`Q_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF{1'b0}}})) | + (FmaRuXNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuX[`D_LEN-2:`D_NF],1'b1,FmaRuX[`D_NF-2:0]})) | + (FmaRuYNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuY[`D_LEN-2:`D_NF],1'b1,FmaRuY[`D_NF-2:0]})) | + (FmaRuZNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuZ[`D_LEN-2:`D_NF],1'b1,FmaRuZ[`D_NF-2:0]}))); + 4'b00: FmaRuNaNGood = ((FmaRuAnsFlags[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRuXNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuX[`S_LEN-2:`S_NF],1'b1,FmaRuX[`S_NF-2:0]})) | + (FmaRuYNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuY[`S_LEN-2:`S_NF],1'b1,FmaRuY[`S_NF-2:0]})) | + (FmaRuZNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuZ[`S_LEN-2:`S_NF],1'b1,FmaRuZ[`S_NF-2:0]}))); + 4'b10: FmaRuNaNGood = ((FmaRuAnsFlags[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRuXNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuX[`H_LEN-2:`H_NF],1'b1,FmaRuX[`H_NF-2:0]})) | + (FmaRuYNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuY[`H_LEN-2:`H_NF],1'b1,FmaRuY[`H_NF-2:0]})) | + (FmaRuZNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuZ[`H_LEN-2:`H_NF],1'b1,FmaRuZ[`H_NF-2:0]}))); + endcase + case (FmaFmtVal) + 4'b11: FmaRdNaNGood = ((FmaRdAnsFlags[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRdXNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdX[`Q_LEN-2:`Q_NF],1'b1,FmaRdX[`Q_NF-2:0]})) | + (FmaRdYNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdY[`Q_LEN-2:`Q_NF],1'b1,FmaRdY[`Q_NF-2:0]})) | + (FmaRdZNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdZ[`Q_LEN-2:`Q_NF],1'b1,FmaRdZ[`Q_NF-2:0]}))); + 4'b01: FmaRdNaNGood = ((FmaRdAnsFlags[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRdXNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdX[`D_LEN-2:`D_NF],1'b1,FmaRdX[`D_NF-2:0]})) | + (FmaRdYNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdY[`D_LEN-2:`D_NF],1'b1,FmaRdY[`D_NF-2:0]})) | + (FmaRdZNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdZ[`D_LEN-2:`D_NF],1'b1,FmaRdZ[`D_NF-2:0]}))); + 4'b00: FmaRdNaNGood = ((FmaRdAnsFlags[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRdXNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdX[`S_LEN-2:`S_NF],1'b1,FmaRdX[`S_NF-2:0]})) | + (FmaRdYNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdY[`S_LEN-2:`S_NF],1'b1,FmaRdY[`S_NF-2:0]})) | + (FmaRdZNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdZ[`S_LEN-2:`S_NF],1'b1,FmaRdZ[`S_NF-2:0]}))); + 4'b10: FmaRdNaNGood = ((FmaRdAnsFlags[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRdXNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdX[`H_LEN-2:`H_NF],1'b1,FmaRdX[`H_NF-2:0]})) | + (FmaRdYNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdY[`H_LEN-2:`H_NF],1'b1,FmaRdY[`H_NF-2:0]})) | + (FmaRdZNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdZ[`H_LEN-2:`H_NF],1'b1,FmaRdZ[`H_NF-2:0]}))); + endcase + case (FmaFmtVal) + 4'b11: FmaRnmNaNGood =((FmaRnmAnsFlags[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRnmXNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmX[`Q_LEN-2:`Q_NF],1'b1,FmaRnmX[`Q_NF-2:0]})) | + (FmaRnmYNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmY[`Q_LEN-2:`Q_NF],1'b1,FmaRnmY[`Q_NF-2:0]})) | + (FmaRnmZNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmZ[`Q_LEN-2:`Q_NF],1'b1,FmaRnmZ[`Q_NF-2:0]}))); + 4'b01: FmaRnmNaNGood =((FmaRnmAnsFlags[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRnmXNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmX[`D_LEN-2:`D_NF],1'b1,FmaRnmX[`D_NF-2:0]})) | + (FmaRnmYNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmY[`D_LEN-2:`D_NF],1'b1,FmaRnmY[`D_NF-2:0]})) | + (FmaRnmZNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmZ[`D_LEN-2:`D_NF],1'b1,FmaRnmZ[`D_NF-2:0]}))); + 4'b00: FmaRnmNaNGood =((FmaRnmAnsFlags[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRnmXNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmX[`S_LEN-2:`S_NF],1'b1,FmaRnmX[`S_NF-2:0]})) | + (FmaRnmYNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmY[`S_LEN-2:`S_NF],1'b1,FmaRnmY[`S_NF-2:0]})) | + (FmaRnmZNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmZ[`S_LEN-2:`S_NF],1'b1,FmaRnmZ[`S_NF-2:0]}))); + 4'b10: FmaRnmNaNGood =((FmaRnmAnsFlags[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRnmXNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmX[`H_LEN-2:`H_NF],1'b1,FmaRnmX[`H_NF-2:0]})) | + (FmaRnmYNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmY[`H_LEN-2:`H_NF],1'b1,FmaRnmY[`H_NF-2:0]})) | + (FmaRnmZNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmZ[`H_LEN-2:`H_NF],1'b1,FmaRnmZ[`H_NF-2:0]}))); + endcase + if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) + case (FmtVal) + 4'b11: NaNGood = ((AnsFlags[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); + 4'b01: NaNGood = ((AnsFlags[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); + 4'b00: NaNGood = ((AnsFlags[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); + 4'b10: NaNGood = ((AnsFlags[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); + endcase + else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format + case (OpCtrlVal[1:0]) + 2'b11: NaNGood = ((AnsFlags[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); + 2'b01: NaNGood = ((AnsFlags[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); + 2'b00: NaNGood = ((AnsFlags[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); + 2'b10: NaNGood = ((AnsFlags[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); + endcase + else NaNGood = 1'b0; + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||||| ||||||| ||| |||||| + // ||| ||| ||| ||| ||| ||| ||| + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlags === AnsFlags | AnsFlags === 5'bx))) begin + errors += 1; + $display("There is an error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlags, Ans, AnsFlags); + $stop; + end + if(~((FmaRneRes === FmaRneAns | FmaRneNaNGood | FmaRneNaNGood === 1'bx) & (FmaRneResFlags === FmaRneAnsFlags | FmaRneAnsFlags === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RNE"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRneX, FmaRneY, FmaRneZ, FmaRneRes, FmaRneResFlags, FmaRneAns, FmaRneAnsFlags); + $stop; + end + if(~((FmaRzRes === FmaRzAns | FmaRzNaNGood | FmaRzNaNGood === 1'bx) & (FmaRzResFlags === FmaRzAnsFlags | FmaRzAnsFlags === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RZ"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRzX, FmaRzY, FmaRzZ, FmaRzRes, FmaRzResFlags, FmaRzAns, FmaRzAnsFlags); + $stop; + end + if(~((FmaRuRes === FmaRuAns | FmaRuNaNGood | FmaRuNaNGood === 1'bx) & (FmaRuResFlags === FmaRuAnsFlags | FmaRuAnsFlags === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RU"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRuX, FmaRuY, FmaRuZ, FmaRuRes, FmaRuResFlags, FmaRuAns, FmaRuAnsFlags); + $stop; + end + if(~((FmaRdRes === FmaRdAns | FmaRdNaNGood | FmaRdNaNGood === 1'bx) & (FmaRdResFlags === FmaRdAnsFlags | FmaRdAnsFlags === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RD"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRdX, FmaRdY, FmaRdZ, FmaRdRes, FmaRdResFlags, FmaRdAns, FmaRdAnsFlags); + $stop; + end + if(~((FmaRnmRes === FmaRnmAns | FmaRnmNaNGood | FmaRnmNaNGood === 1'bx) & (FmaRnmResFlags === FmaRnmAnsFlags | FmaRnmAnsFlags === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RNM"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRnmX, FmaRnmY, FmaRnmZ, FmaRnmRes, FmaRnmResFlags, FmaRnmAns, FmaRnmAnsFlags); + $stop; + end + VectorNum += 1; // increment test + if (TestVectors[VectorNum][0] === 1'bx & + FmaRneVectors[VectorNum][0] === 1'bx & + FmaRzVectors[VectorNum][0] === 1'bx & + FmaRuVectors[VectorNum][0] === 1'bx & + FmaRdVectors[VectorNum][0] === 1'bx & + FmaRnmVectors[VectorNum][0] === 1'bx) begin // if reached the end of file + if (errors) begin // if there were errors + $display("%s completed with %d Tests and %d errors", Tests[VectorNum], VectorNum, errors); + $stop; + end + + TestNum += 1; + // read next files + $readmemh({`PATH, Tests[TestNum]}, TestVectors); + $readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors); + $readmemh({`PATH, FmaRuTests[TestNum]}, FmaRuVectors); + $readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors); + $readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors); + $readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors); + FmaNum += 1; + VectorNum = 0; + if(FrmNum === 4) OpCtrlNum += 1; + if(FrmNum < 4) FrmNum += 1; + else FrmNum = 0; + // if no more Tests - finish + if(Tests[TestNum] === "" & + FmaRneTests[TestNum] === "" & + FmaRzTests[TestNum] === "" & + FmaRuTests[TestNum] === "" & + FmaRdTests[TestNum] === "" & + FmaRnmTests[TestNum] === "") begin + $display("\nAll Tests completed with %d errors\n", errors); + $stop; + end + + $display("Running %s vectors", Tests[TestNum]); + end + end +endmodule + + + + + + + + + + + + + +module readfmavectors ( + input logic clk, + input logic [2:0] Frm, + input logic [`FPSIZES/3:0] FmaModFmt, + input logic [1:0] FmaFmt, + input logic [`FLEN*4+7:0] TestVector, + input logic [31:0] VectorNum, + input logic [31:0] FmaNum, + output logic [`FLEN-1:0] Ans, + output logic [4:0] AnsFlags, + output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ + output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) + output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN + output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN + output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero + output logic XInfE, YInfE, ZInfE, // is XYZ infinity + output logic [`FLEN-1:0] X, Y, Z +); + + logic XNormE, XExpMaxE; // signals the unpacker outputs but isn't used in FMA + // apply test vectors on rising edge of clk + // Format of vectors Inputs(1/2/3)_AnsFlags + always @(posedge clk) begin + #1; + AnsFlags = TestVector[4:0]; + case (FmaFmt) + 2'b11: begin // quad + X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)]; + Y = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Z = TestVector[8+2*(`Q_LEN)-1:8+`Q_LEN]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+4*(`D_LEN)-1:8+3*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+`D_LEN]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+4*(`S_LEN)-1:8+3*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+`S_LEN]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+4*(`H_LEN)-1:8+3*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+`H_LEN]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + + unpack unpack(.X, .Y, .Z, .FmtE(FmaModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, + .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, + .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, + .XExpMaxE); +endmodule + + + + + + + + + + + + + + + + + +module readvectors ( + input logic clk, + input logic [`FLEN*4+7:0] TestVector, + input logic [`FPSIZES/3:0] ModFmt, + input logic [1:0] Fmt, + input logic [2:0] Unit, + input logic [31:0] VectorNum, + input logic [31:0] TestNum, + input logic [2:0] OpCtrl, + output logic [`FLEN-1:0] Ans, + output logic [`XLEN-1:0] SrcA, + output logic [4:0] AnsFlags, + output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ + output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) + output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN + output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN + output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero + output logic XInfE, YInfE, ZInfE, // is XYZ infinity + output logic XNormE, XExpMaxE, + output logic [`FLEN-1:0] X, Y, Z +); + + // apply test vectors on rising edge of clk + // Format of vectors Inputs(1/2/3)_AnsFlags + always @(posedge clk) begin + #1; + AnsFlags = TestVector[4:0]; + case (Unit) + `FMAUNIT: + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, `Q_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, `D_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; + else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, `S_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; + else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, `H_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; + else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + `DIVUNIT: + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + `CMPUNIT: + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Y = TestVector[8+(`Q_LEN)-1:9]; + Ans = TestVector[8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN)-1:9]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN)-1:9]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN)-1:9]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8]}; + end + endcase + `CVTFPUNIT: + case (Fmt) + 2'b11: begin // quad + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`Q_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`Q_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`Q_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`Q_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b01: begin // double + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b00: begin // single + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b10: begin // half + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + endcase + + `CVTINTUNIT: + case (Fmt) + 2'b11: begin // quad + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2], OpCtrl[0]}) + 2'b11: begin // long -> quad + SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // int -> quad + // correctly sign extend the integer depending on if it's a signed/unsigned test + SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b10: begin // quad -> long + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // double -> long + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; + Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + end + endcase + end + 2'b01: begin // double + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2], OpCtrl[0]}) + 2'b11: begin // long -> double + SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]; + Ans = TestVector[8+(`D_LEN-1):8]; + end + 2'b01: begin // int -> double + // correctly sign extend the integer depending on if it's a signed/unsigned test + SrcA = {{`XLEN-32{TestVector[8+`D_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]}; + Ans = TestVector[8+(`D_LEN-1):8]; + end + 2'b10: begin // double -> long + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // double -> int + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; + Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + end + endcase + end + 2'b00: begin // single + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2], OpCtrl[0]}) + 2'b11: begin // long -> single + SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]; + Ans = TestVector[8+(`S_LEN-1):8]; + end + 2'b01: begin // int -> single + // correctly sign extend the integer depending on if it's a signed/unsigned test + SrcA = {{`XLEN-32{TestVector[8+`S_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]}; + Ans = TestVector[8+(`S_LEN-1):8]; + end + 2'b10: begin // single -> long + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // single -> int + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; + Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + end + endcase + end + 2'b10: begin // half + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2], OpCtrl[0]}) + 2'b11: begin // long -> half + SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]; + Ans = TestVector[8+(`H_LEN-1):8]; + end + 2'b01: begin // int -> half + // correctly sign extend the integer depending on if it's a signed/unsigned test + SrcA = {{`XLEN-32{TestVector[8+`H_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]}; + Ans = TestVector[8+(`H_LEN-1):8]; + end + 2'b10: begin // half -> long + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // half -> int + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; + Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}}, TestVector[8+(`XLEN-1):8]}; + end + endcase + end + endcase + endcase + end + + unpack unpack(.X, .Y, .Z, .FmtE(ModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, + .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, + .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, + .XExpMaxE); +endmodule \ No newline at end of file diff --git a/pipelined/testbench/tests-fp.vh b/pipelined/testbench/tests-fp.vh new file mode 100644 index 000000000..d285454bb --- /dev/null +++ b/pipelined/testbench/tests-fp.vh @@ -0,0 +1,587 @@ +/////////////////////////////////////////// +// tests.vh +// +// Written: David_Harris@hmc.edu 7 October 2021 +// Modified: +// +// Purpose: List of tests to apply +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + +`define PATH "../../tests/fp/vectors/" +`define ADD_OPCTRL 3'b110 +`define MUL_OPCTRL 3'b100 +`define SUB_OPCTRL 3'b111 +`define FADD_OPCTRL 3'b000 +`define DIV_OPCTRL 3'b000 +`define SQRT_OPCTRL 3'b001 +`define LE_OPCTRL 3'b011 +`define LT_OPCTRL 3'b001 +`define EQ_OPCTRL 3'b010 +`define TO_UI_OPCTRL 3'b011 +`define TO_I_OPCTRL 3'b001 +`define TO_UL_OPCTRL 3'b111 +`define TO_L_OPCTRL 3'b101 +`define FROM_UI_OPCTRL 3'b010 +`define FROM_I_OPCTRL 3'b000 +`define FROM_UL_OPCTRL 3'b110 +`define FROM_L_OPCTRL 3'b100 +`define RNE 3'b000 +`define RZ 3'b001 +`define RU 3'b011 +`define RD 3'b010 +`define RNM 3'b100 +`define FMAUNIT 0 +`define DIVUNIT 1 +`define CVTINTUNIT 2 +`define CVTFPUNIT 3 +`define CMPUNIT 4 + +string f16rv32cvtint[] = '{ + "f16_to_i32_rne.tv", + "f16_to_i32_rz.tv", + "f16_to_i32_ru.tv", + "f16_to_i32_rd.tv", + "f16_to_i32_rnm.tv", + "f16_to_ui32_rne.tv", + "f16_to_ui32_rz.tv", + "f16_to_ui32_ru.tv", + "f16_to_ui32_rd.tv", + "f16_to_ui32_rnm.tv", + "ui32_to_f16_rne.tv", + "ui32_to_f16_rz.tv", + "ui32_to_f16_ru.tv", + "ui32_to_f16_rd.tv", + "ui32_to_f16_rnm.tv", + "i32_to_f16_rne.tv", + "i32_to_f16_rz.tv", + "i32_to_f16_ru.tv", + "i32_to_f16_rd.tv", + "i32_to_f16_rnm.tv" +}; + +string f16rv64cvtint[] = '{ + "f16_to_ui64_rne.tv", + "f16_to_ui64_rz.tv", + "f16_to_ui64_ru.tv", + "f16_to_ui64_rd.tv", + "f16_to_ui64_rnm.tv", + "f16_to_i64_rne.tv", + "f16_to_i64_rz.tv", + "f16_to_i64_ru.tv", + "f16_to_i64_rd.tv", + "f16_to_i64_rnm.tv", + "ui64_to_f16_rne.tv", + "ui64_to_f16_rz.tv", + "ui64_to_f16_ru.tv", + "ui64_to_f16_rd.tv", + "ui64_to_f16_rnm.tv", + "i64_to_f16_rne.tv", + "i64_to_f16_rz.tv", + "i64_to_f16_ru.tv", + "i64_to_f16_rd.tv", + "i64_to_f16_rnm.tv" +}; + +string f32rv32cvtint[] = '{ + "ui32_to_f32_rne.tv", + "ui32_to_f32_rz.tv", + "ui32_to_f32_ru.tv", + "ui32_to_f32_rd.tv", + "ui32_to_f32_rnm.tv", + "i32_to_f32_rne.tv", + "i32_to_f32_rz.tv", + "i32_to_f32_ru.tv", + "i32_to_f32_rd.tv", + "i32_to_f32_rnm.tv", + "f32_to_ui32_rne.tv", + "f32_to_ui32_rz.tv", + "f32_to_ui32_ru.tv", + "f32_to_ui32_rd.tv", + "f32_to_ui32_rnm.tv", + "f32_to_i32_rne.tv", + "f32_to_i32_rz.tv", + "f32_to_i32_ru.tv", + "f32_to_i32_rd.tv", + "f32_to_i32_rnm.tv" +}; + +string f32rv64cvtint[] = '{ + "ui64_to_f32_rne.tv", + "ui64_to_f32_rz.tv", + "ui64_to_f32_ru.tv", + "ui64_to_f32_rd.tv", + "ui64_to_f32_rnm.tv", + "i64_to_f32_rne.tv", + "i64_to_f32_rz.tv", + "i64_to_f32_ru.tv", + "i64_to_f32_rd.tv", + "i64_to_f32_rnm.tv", + "f32_to_ui64_rne.tv", + "f32_to_ui64_rz.tv", + "f32_to_ui64_ru.tv", + "f32_to_ui64_rd.tv", + "f32_to_ui64_rnm.tv", + "f32_to_i64_rne.tv", + "f32_to_i64_rz.tv", + "f32_to_i64_ru.tv", + "f32_to_i64_rd.tv", + "f32_to_i64_rnm.tv" +}; + + +string f64rv32cvtint[] = '{ + "ui32_to_f64_rne.tv", + "ui32_to_f64_rz.tv", + "ui32_to_f64_ru.tv", + "ui32_to_f64_rd.tv", + "ui32_to_f64_rnm.tv", + "i32_to_f64_rne.tv", + "i32_to_f64_rz.tv", + "i32_to_f64_ru.tv", + "i32_to_f64_rd.tv", + "i32_to_f64_rnm.tv", + "f64_to_ui32_rne.tv", + "f64_to_ui32_rz.tv", + "f64_to_ui32_ru.tv", + "f64_to_ui32_rd.tv", + "f64_to_ui32_rnm.tv", + "f64_to_i32_rne.tv", + "f64_to_i32_rz.tv", + "f64_to_i32_ru.tv", + "f64_to_i32_rd.tv", + "f64_to_i32_rnm.tv" +}; + +string f64rv64cvtint[] = '{ + "ui64_to_f64_rne.tv", + "ui64_to_f64_rz.tv", + "ui64_to_f64_ru.tv", + "ui64_to_f64_rd.tv", + "ui64_to_f64_rnm.tv", + "i64_to_f64_rne.tv", + "i64_to_f64_rz.tv", + "i64_to_f64_ru.tv", + "i64_to_f64_rd.tv", + "i64_to_f64_rnm.tv", + "f64_to_ui64_rne.tv", + "f64_to_ui64_rz.tv", + "f64_to_ui64_ru.tv", + "f64_to_ui64_rd.tv", + "f64_to_ui64_rnm.tv", + "f64_to_i64_rne.tv", + "f64_to_i64_rz.tv", + "f64_to_i64_ru.tv", + "f64_to_i64_rd.tv", + "f64_to_i64_rnm.tv" +}; + +string f128rv64cvtint[] = '{ + "ui64_to_f128_rne.tv", + "ui64_to_f128_rz.tv", + "ui64_to_f128_ru.tv", + "ui64_to_f128_rd.tv", + "ui64_to_f128_rnm.tv", + "i64_to_f128_rne.tv", + "i64_to_f128_rz.tv", + "i64_to_f128_ru.tv", + "i64_to_f128_rd.tv", + "i64_to_f128_rnm.tv", + "f128_to_ui64_rne.tv", + "f128_to_ui64_rz.tv", + "f128_to_ui64_ru.tv", + "f128_to_ui64_rd.tv", + "f128_to_ui64_rnm.tv", + "f128_to_i64_rne.tv", + "f128_to_i64_rz.tv", + "f128_to_i64_ru.tv", + "f128_to_i64_rd.tv", + "f128_to_i64_rnm.tv" +}; + +string f128rv32cvtint[] = '{ + "ui32_to_f128_rne.tv", + "ui32_to_f128_rz.tv", + "ui32_to_f128_ru.tv", + "ui32_to_f128_rd.tv", + "ui32_to_f128_rnm.tv", + "i32_to_f128_rne.tv", + "i32_to_f128_rz.tv", + "i32_to_f128_ru.tv", + "i32_to_f128_rd.tv", + "i32_to_f128_rnm.tv", + "f128_to_ui32_rne.tv", + "f128_to_ui32_rz.tv", + "f128_to_ui32_ru.tv", + "f128_to_ui32_rd.tv", + "f128_to_ui32_rnm.tv", + "f128_to_i32_rne.tv", + "f128_to_i32_rz.tv", + "f128_to_i32_ru.tv", + "f128_to_i32_rd.tv", + "f128_to_i32_rnm.tv" +}; + + +string f32f16cvt[] = '{ + "f32_to_f16_rne.tv", + "f32_to_f16_rz.tv", + "f32_to_f16_ru.tv", + "f32_to_f16_rd.tv", + "f32_to_f16_rnm.tv", + "f16_to_f32_rne.tv", + "f16_to_f32_rz.tv", + "f16_to_f32_ru.tv", + "f16_to_f32_rd.tv", + "f16_to_f32_rnm.tv" +}; + +string f64f16cvt[] = '{ + "f64_to_f16_rne.tv", + "f64_to_f16_rz.tv", + "f64_to_f16_ru.tv", + "f64_to_f16_rd.tv", + "f64_to_f16_rnm.tv", + "f16_to_f64_rne.tv", + "f16_to_f64_rz.tv", + "f16_to_f64_ru.tv", + "f16_to_f64_rd.tv", + "f16_to_f64_rnm.tv" +}; + +string f128f16cvt[] = '{ + "f128_to_f16_rne.tv", + "f128_to_f16_rz.tv", + "f128_to_f16_ru.tv", + "f128_to_f16_rd.tv", + "f128_to_f16_rnm.tv", + "f16_to_f128_rne.tv", + "f16_to_f128_rz.tv", + "f16_to_f128_ru.tv", + "f16_to_f128_rd.tv", + "f16_to_f128_rnm.tv" +}; + +string f64f32cvt[] = '{ + "f64_to_f32_rne.tv", + "f64_to_f32_rz.tv", + "f64_to_f32_ru.tv", + "f64_to_f32_rd.tv", + "f64_to_f32_rnm.tv", + "f32_to_f64_rne.tv", + "f32_to_f64_rz.tv", + "f32_to_f64_ru.tv", + "f32_to_f64_rd.tv", + "f32_to_f64_rnm.tv" +}; + + +string f128f32cvt[] = '{ + "f128_to_f32_rne.tv", + "f128_to_f32_rz.tv", + "f128_to_f32_ru.tv", + "f128_to_f32_rd.tv", + "f128_to_f32_rnm.tv", + "f32_to_f128_rne.tv", + "f32_to_f128_rz.tv", + "f32_to_f128_ru.tv", + "f32_to_f128_rd.tv", + "f32_to_f128_rnm.tv" +}; + + +string f128f64cvt[] = '{ + "f64_to_f128_rne.tv", + "f64_to_f128_rz.tv", + "f64_to_f128_ru.tv", + "f64_to_f128_rd.tv", + "f64_to_f128_rnm.tv", + "f128_to_f64_rne.tv", + "f128_to_f64_rz.tv", + "f128_to_f64_ru.tv", + "f128_to_f64_rd.tv", + "f128_to_f64_rnm.tv" +}; + +string f16add[] = '{ + "f16_add_rne.tv", + "f16_add_rz.tv", + "f16_add_ru.tv", + "f16_add_rd.tv", + "f16_add_rnm.tv" +}; + +string f32add[] = '{ + "f32_add_rne.tv", + "f32_add_rz.tv", + "f32_add_ru.tv", + "f32_add_rd.tv", + "f32_add_rnm.tv" +}; + +string f64add[] = '{ + "f64_add_rne.tv", + "f64_add_rz.tv", + "f64_add_ru.tv", + "f64_add_rd.tv", + "f64_add_rnm.tv" +}; + +string f128add[] = '{ + "f128_add_rne.tv", + "f128_add_rz.tv", + "f128_add_ru.tv", + "f128_add_rd.tv", + "f128_add_rnm.tv" +}; + +string f16sub[] = '{ + "f16_sub_rne.tv", + "f16_sub_rz.tv", + "f16_sub_ru.tv", + "f16_sub_rd.tv", + "f16_sub_rnm.tv" +}; + +string f32sub[] = '{ + "f32_sub_rne.tv", + "f32_sub_rz.tv", + "f32_sub_ru.tv", + "f32_sub_rd.tv", + "f32_sub_rnm.tv" +}; + +string f64sub[] = '{ + "f64_sub_rne.tv", + "f64_sub_rz.tv", + "f64_sub_ru.tv", + "f64_sub_rd.tv", + "f64_sub_rnm.tv" +}; + +string f128sub[] = '{ + "f128_sub_rne.tv", + "f128_sub_rz.tv", + "f128_sub_ru.tv", + "f128_sub_rd.tv", + "f128_sub_rnm.tv" +}; + +string f16mul[] = '{ + "f16_mul_rne.tv", + "f16_mul_rz.tv", + "f16_mul_ru.tv", + "f16_mul_rd.tv", + "f16_mul_rnm.tv" +}; + +string f32mul[] = '{ + "f32_mul_rne.tv", + "f32_mul_rz.tv", + "f32_mul_ru.tv", + "f32_mul_rd.tv", + "f32_mul_rnm.tv" +}; + +string f64mul[] = '{ + "f64_mul_rne.tv", + "f64_mul_rz.tv", + "f64_mul_ru.tv", + "f64_mul_rd.tv", + "f64_mul_rnm.tv" +}; + +string f128mul[] = '{ + "f128_mul_rne.tv", + "f128_mul_rz.tv", + "f128_mul_ru.tv", + "f128_mul_rd.tv", + "f128_mul_rnm.tv" +}; + +string f16div[] = '{ + "f16_div_rne.tv", + "f16_div_rz.tv", + "f16_div_ru.tv", + "f16_div_rd.tv", + "f16_div_rnm.tv" +}; + +string f32div[] = '{ + "f32_div_rne.tv", + "f32_div_rz.tv", + "f32_div_ru.tv", + "f32_div_rd.tv", + "f32_div_rnm.tv" +}; + +string f64div[] = '{ + "f64_div_rne.tv", + "f64_div_rz.tv", + "f64_div_ru.tv", + "f64_div_rd.tv", + "f64_div_rnm.tv" +}; + +string f128div[] = '{ + "f128_div_rne.tv", + "f128_div_rz.tv", + "f128_div_ru.tv", + "f128_div_rd.tv", + "f128_div_rnm.tv" +}; + +string f16sqrt[] = '{ + "f16_sqrt_rne.tv", + "f16_sqrt_rz.tv", + "f16_sqrt_ru.tv", + "f16_sqrt_rd.tv", + "f16_sqrt_rnm.tv" +}; + +string f32sqrt[] = '{ + "f32_sqrt_rne.tv", + "f32_sqrt_rz.tv", + "f32_sqrt_ru.tv", + "f32_sqrt_rd.tv", + "f32_sqrt_rnm.tv" +}; + +string f64sqrt[] = '{ + "f64_sqrt_rne.tv", + "f64_sqrt_rz.tv", + "f64_sqrt_ru.tv", + "f64_sqrt_rd.tv", + "f64_sqrt_rnm.tv" +}; + +string f128sqrt[] = '{ + "f128_sqrt_rne.tv", + "f128_sqrt_rz.tv", + "f128_sqrt_ru.tv", + "f128_sqrt_rd.tv", + "f128_sqrt_rnm.tv" +}; + +string f16cmp[] = '{ + "f16_eq_rne.tv", + "f16_eq_rz.tv", + "f16_eq_ru.tv", + "f16_eq_rd.tv", + "f16_eq_rnm.tv", + "f16_le_rne.tv", + "f16_le_rz.tv", + "f16_le_ru.tv", + "f16_le_rd.tv", + "f16_le_rnm.tv", + "f16_lt_rne.tv", + "f16_lt_rz.tv", + "f16_lt_ru.tv", + "f16_lt_rd.tv", + "f16_lt_rnm.tv" +}; + +string f32cmp[] = '{ + "f32_eq_rne.tv", + "f32_eq_rz.tv", + "f32_eq_ru.tv", + "f32_eq_rd.tv", + "f32_eq_rnm.tv", + "f32_le_rne.tv", + "f32_le_rz.tv", + "f32_le_ru.tv", + "f32_le_rd.tv", + "f32_le_rnm.tv", + "f32_lt_rne.tv", + "f32_lt_rz.tv", + "f32_lt_ru.tv", + "f32_lt_rd.tv", + "f32_lt_rnm.tv" +}; + +string f64cmp[] = '{ + "f64_eq_rne.tv", + "f64_eq_rz.tv", + "f64_eq_ru.tv", + "f64_eq_rd.tv", + "f64_eq_rnm.tv", + "f64_le_rne.tv", + "f64_le_rz.tv", + "f64_le_ru.tv", + "f64_le_rd.tv", + "f64_le_rnm.tv", + "f64_lt_rne.tv", + "f64_lt_rz.tv", + "f64_lt_ru.tv", + "f64_lt_rd.tv", + "f64_lt_rnm.tv" +}; + +string f128cmp[] = '{ + "f128_eq_rne.tv", + "f128_eq_rz.tv", + "f128_eq_ru.tv", + "f128_eq_rd.tv", + "f128_eq_rnm.tv", + "f128_le_rne.tv", + "f128_le_rz.tv", + "f128_le_ru.tv", + "f128_le_rd.tv", + "f128_le_rnm.tv", + "f128_lt_rne.tv", + "f128_lt_rz.tv", + "f128_lt_ru.tv", + "f128_lt_rd.tv", + "f128_lt_rnm.tv" +}; + +string f16fma[] = '{ + "f16_mulAdd_rne.tv", + "f16_mulAdd_rz.tv", + "f16_mulAdd_ru.tv", + "f16_mulAdd_rd.tv", + "f16_mulAdd_rnm.tv" +}; + +string f32fma[] = '{ + "f32_mulAdd_rne.tv", + "f32_mulAdd_rz.tv", + "f32_mulAdd_ru.tv", + "f32_mulAdd_rd.tv", + "f32_mulAdd_rnm.tv" +}; + +string f64fma[] = '{ + "f64_mulAdd_rne.tv", + "f64_mulAdd_rz.tv", + "f64_mulAdd_ru.tv", + "f64_mulAdd_rd.tv", + "f64_mulAdd_rnm.tv" +}; + +string f128fma[] = '{ + "f128_mulAdd_rne.tv", + "f128_mulAdd_rz.tv", + "f128_mulAdd_ru.tv", + "f128_mulAdd_rd.tv", + "f128_mulAdd_rnm.tv" +}; + + + From 710905b239e2a43e49db93e31f93bdc73c8009db Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Thu, 19 May 2022 20:24:47 +0000 Subject: [PATCH 26/38] updated synth plotting and regression --- pipelined/src/ppa/ppa.sv | 3 +- synthDC/ppaAnalyze.py | 230 +++++++++++++++++++++++----------- synthDC/ppaData.csv | 264 +++++++++++++++++++++++++++++---------- synthDC/ppaFitting.csv | 26 ++-- synthDC/ppaSynth.py | 10 +- 5 files changed, 375 insertions(+), 158 deletions(-) diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 0207c99f7..32fc45e29 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -313,6 +313,7 @@ module ppa_shifter #(parameter WIDTH=32) ( assign Y = zshift[WIDTH-1:0]; endmodule +// just report one hot module ppa_prioritythermometer #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y); @@ -338,7 +339,7 @@ module ppa_priorityonehot #(parameter N = 8) ( assign y = a & nolower; endmodule -module ppa_prioriyencoder #(parameter N = 8) ( +module ppa_priorityencoder #(parameter N = 8) ( input logic [N-1:0] a, output logic [$clog2(N)-1:0] y); // Carefully crafted so design compiler will synthesize into a fast tree structure diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index edad94dd4..56e8b2f83 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -1,6 +1,8 @@ #!/usr/bin/python3 from distutils.log import error +from statistics import median import subprocess +import statistics import csv import re import matplotlib.pyplot as plt @@ -32,13 +34,17 @@ def getData(): for i in range(len(linesCPL)): line = linesCPL[i] mwm = wm.findall(line)[0][4:-4].split('_') + freq = int(f.findall(line)[0][1:-4]) + delay = float(cpl.findall(line)[0]) + area = float(da.findall(linesDA[i])[0]) + mod = mwm[0] + width = int(mwm[1]) + power = p.findall(linesP[i]) - oneSynth = [mwm[0], int(mwm[1])] - oneSynth += [int(f.findall(line)[0][1:-4])] - oneSynth += [float(cpl.findall(line)[0])] - oneSynth += [float(da.findall(linesDA[i])[0])] - oneSynth += [float(power[1])] - oneSynth += [float(power[2])] + lpower = float(power[2]) + denergy = float(power[1])/freq + + oneSynth = [mod, width, freq, delay, area, lpower, denergy] allSynths += [oneSynth] return allSynths @@ -47,133 +53,209 @@ def getVals(module, freq, var): global allSynths if (var == 'delay'): ind = 3 - units = " (ps)" + units = " (ns)" elif (var == 'area'): ind = 4 units = " (sq microns)" - elif (var == 'dpower'): - ind = 5 - units = " (mW)" elif (var == 'lpower'): - ind = 6 + ind = 5 units = " (nW)" + elif (var == 'denergy'): + ind = 6 + units = " (uJ)" #fix check math else: error widths = [] - ivar = [] + metric = [] for oneSynth in allSynths: if (oneSynth[0] == module) & (oneSynth[2] == freq): widths += [oneSynth[1]] - ivar += [oneSynth[ind]] - return widths, ivar, units + m = oneSynth[ind] + if (ind==6): m*=1000 + metric += [m] + return widths, metric, units def writeCSV(allSynths): file = open("ppaData.csv", "w") writer = csv.writer(file) - writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area', 'D Power (mW)', 'L Power (nW)']) + writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)']) for one in allSynths: writer.writerow(one) file.close() -def polyfitR2(x, y, deg): - ''' from internet, check math''' - z = np.polyfit(x, y, deg) - p = np.poly1d(z) - yhat = p(x) # or [p(z) for z in x] - ybar = np.sum(y)/len(y) # or sum(y)/len(y) - ssreg = np.sum((yhat-ybar)**2) # or sum([ (yihat - ybar)**2 for yihat in yhat]) - sstot = np.sum((y - ybar)**2) # or sum([ (yi - ybar)**2 for yi in y]) - r2 = ssreg / sstot - return p, r2 +def genLegend(fits, coefs, module, r2): -def plotPPA(module, freq, var): + coefsr = [str(round(c, 3)) for c in coefs] + + eq = '' + ind = 0 + if 'c' in fits: + eq += coefsr[ind] + ind += 1 + if 'l' in fits: + eq += " + " + coefsr[ind] + "*N" + ind += 1 + if 's' in fits: + eq += " + " + coefsr[ind] + "*N^2" + ind += 1 + if 'g' in fits: + eq += " + " + coefsr[ind] + "*log2(N)" + ind += 1 + if 'n' in fits: + eq += " + " + coefsr[ind] + "*Nlog2(N)" + ind += 1 + + legend_elements = [lines.Line2D([0], [0], color='orange', label=eq), + lines.Line2D([0], [0], color='steelblue', ls='', marker='o', label=' R^2='+ str(round(r2, 4)))] + return legend_elements + +def plotPPA(module, freq, var, ax=None, fits='clsgn'): ''' module: string module name - freq: int freq (GHz) - var: string 'delay' or 'area' + freq: int freq (MHz) + var: string delay, area, lpower, or denergy + fits: constant, linear, square, log2, Nlog2 plots chosen variable vs width for all matching syntheses with regression ''' - - # A = np.vstack([x, np.ones(len(x))]).T - # mcresid = np.linalg.lstsq(A, y, rcond=None) - # m, c = mcresid[0] - # resid = mcresid[1] - # r2 = 1 - resid / (y.size * y.var()) - # p, r2p = polyfitR2(x, y, 2) - # zlog = np.polyfit(np.log(x), y, 1) - # plog = np.poly1d(zlog) - # xplog = np.log(xp) - # _ = plt.plot(x, m*x + c, 'r', label='Linear fit R^2='+ str(r2)[1:7]) - # _ = plt.plot(xp, p(xp), label='Quadratic fit R^2='+ str(r2p)[:6]) - # _ = plt.plot(xp, plog(xplog), label = 'Log fit') - - widths, ivar, units = getVals(module, freq, var) - coefs, r2 = regress(widths, ivar) + widths, metric, units = getVals(module, freq, var) + coefs, r2, funcArr = regress(widths, metric, fits) xp = np.linspace(8, 140, 200) - pred = [coefs[0] + x*coefs[1] + np.log(x)*coefs[2] + x*np.log(x)*coefs[3] for x in xp] + pred = [] + for x in xp: + y = [func(x) for func in funcArr] + pred += [sum(np.multiply(coefs, y))] - r2p = round(r2[0], 4) - rcoefs = [round(c, 3) for c in coefs] + if ax is None: + singlePlot = True + ax = plt.gca() + else: + singlePlot = False - l = "{} + {}*N + {}*log(N) + {}*Nlog(N)".format(*rcoefs) - legend_elements = [lines.Line2D([0], [0], color='steelblue', label=module), - lines.Line2D([0], [0], color='orange', label=l), - lines.Line2D([0], [0], ls='', label=' R^2='+ str(r2p))] + ax.scatter(widths, metric) + ax.plot(xp, pred, color='orange') - _ = plt.plot(widths, ivar, 'o', label=module, markersize=10) - _ = plt.plot(xp, pred) - _ = plt.legend(handles=legend_elements) - _ = plt.xlabel("Width (bits)") - _ = plt.ylabel(str.title(var) + units) - _ = plt.title("Target frequency " + str(freq) + "MHz") + legend_elements = genLegend(fits, coefs, module, r2) + ax.legend(handles=legend_elements) + + ax.set_xticks(widths) + ax.set_xlabel("Width (bits)") + ax.set_ylabel(str.title(var) + units) + + if singlePlot: + ax.set_title(module + " (target " + str(freq) + "MHz)") + plt.show() + +def makePlots(mod, freq): + fig, axs = plt.subplots(2, 2) + plotPPA(mod, freq, 'delay', ax=axs[0,0], fits='cgl') + plotPPA(mod, freq, 'area', ax=axs[0,1], fits='clg') + plotPPA(mod, freq, 'lpower', ax=axs[1,0], fits='c') + plotPPA(mod, freq, 'denergy', ax=axs[1,1], fits='glc') + plt.suptitle(mod + " (target " + str(freq) + "MHz)") plt.show() -def makePlots(mod): - plotPPA(mod, 5000, 'delay') - plotPPA(mod, 5000, 'area') - plotPPA(mod, 10, 'area') - plotPPA(mod, 5000, 'lpower') - plotPPA(mod, 5000, 'dpower') +def regress(widths, var, fits='clsgn'): -def regress(widths, var): + funcArr = genFuncs(fits) mat = [] for w in widths: - row = [1, w, np.log(w), w*np.log(w)] + row = [] + for func in funcArr: + row += [func(w)] mat += [row] y = np.array(var, dtype=np.float) coefsResid = np.linalg.lstsq(mat, y, rcond=None) coefs = coefsResid[0] - resid = coefsResid[1] + try: + resid = coefsResid[1][0] + except: + resid = 0 r2 = 1 - resid / (y.size * y.var()) - return coefs, r2 + return coefs, r2, funcArr def makeCoefTable(): file = open("ppaFitting.csv", "w") writer = csv.writer(file) - writer.writerow(['Module', 'Metric', 'Freq', '1', 'N', 'log(N)', 'Nlog(N)', 'R^2']) + writer.writerow(['Module', 'Metric', 'Freq', '1', 'N', 'N^2', 'log2(N)', 'Nlog2(N)', 'R^2']) for mod in ['add', 'mult', 'comparator', 'shifter']: for comb in [['delay', 5000], ['area', 5000], ['area', 10]]: var = comb[0] freq = comb[1] - widths, ivar, units = getVals(mod, freq, var) - coefs, r2 = regress(widths, ivar) - row = [mod] + comb + np.ndarray.tolist(coefs) + [r2[0]] + widths, metric, units = getVals(mod, freq, var) + coefs, r2, funcArr = regress(widths, metric) + row = [mod] + comb + np.ndarray.tolist(coefs) + [r2] writer.writerow(row) file.close() +def genFuncs(fits='clsgn'): + funcArr = [] + if 'c' in fits: + funcArr += [lambda x: 1] + if 'l' in fits: + funcArr += [lambda x: x] + if 's' in fits: + funcArr += [lambda x: x**2] + if 'g' in fits: + funcArr += [lambda x: np.log2(x)] + if 'n' in fits: + funcArr += [lambda x: x*np.log2(x)] + return funcArr + +def noOutliers(freqs, delays, areas): + med = statistics.median(freqs) + f=[] + d=[] + a=[] + for i in range(len(freqs)): + norm = freqs[i]/med + if (norm > 0.25) & (norm<1.75): + f += [freqs[i]] + d += [delays[i]] + a += [areas[i]] + return f, d, a + +def freqPlot(mod, width): + freqs = [] + delays = [] + areas = [] + for oneSynth in allSynths: + if (mod == oneSynth[0]) & (width == oneSynth[1]): + freqs += [oneSynth[2]] + delays += [oneSynth[3]] + areas += [oneSynth[4]] + + freqs, delays, areas = noOutliers(freqs, delays, areas) + + adprod = np.multiply(areas, delays) + adsq = np.multiply(adprod, delays) + + f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True) + ax1.scatter(freqs, delays) + ax2.scatter(freqs, areas) + ax3.scatter(freqs, adprod) + ax4.scatter(freqs, adsq) + ax4.set_xlabel("Freq (MHz)") + ax1.set_ylabel('Delay (ns)') + ax2.set_ylabel('Area (sq microns)') + ax3.set_ylabel('Area * Delay') + ax4.set_ylabel('Area * Delay^2') + ax1.set_title(mod + '_' + str(width)) + plt.show() + allSynths = getData() - writeCSV(allSynths) +# makeCoefTable() -makePlots('shifter') +freqPlot('comparator', 8) -makeCoefTable() +# makePlots('shifter', 5000) +# plotPPA('comparator', 5000, 'delay', fits='cls') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 3ea5648b6..9e09c3403 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,67 +1,197 @@ -Module,Width,Target Freq,Delay,Area,D Power (mW),L Power (nW) -add,128,10,7.100851,1867.879976,0.00501,465.925 -add,128,5000,0.389771,7007.980119,3.309,2.77 -add,16,10,2.032906,221.479998,0.000575,55.29 -add,16,4000,0.249839,551.74001,0.239,302.479 -add,16,5000,0.228259,924.140017,0.519,641.631 -add,16,6000,0.225754,1120.140018,0.739,1.01 -add,32,10,4.160501,456.679995,0.00118,112.161 -add,32,4000,0.280842,1730.680031,0.735,849.828 -add,32,5000,0.2505,1933.540033,1.049,1.03 -add,32,6000,0.271774,1746.36003,1.138,955.901 -add,64,10,8.474034,927.079988,0.00246,230.083 -add,64,4000,0.323267,3758.300065,1.523,1.75 -add,64,5000,0.334061,3798.480071,1.917,2.18 -add,64,6000,0.328457,3749.480066,2.346,1.77 -add,8,10,0.940062,103.879999,0.000241,24.765 -add,8,5000,0.199689,197.960003,0.113,83.576 -comparator,128,10,0.842074,1997.240039,0.00087,243.506 -comparator,128,5000,0.260142,5215.56005,3.708,6.0 -comparator,16,10,0.576329,252.840005,0.000144,31.402 -comparator,16,4000,0.249312,280.280005,0.0581,55.248 -comparator,16,5000,0.199026,313.600006,0.0859,78.893 -comparator,16,6000,0.166568,422.380007,0.255,301.506 -comparator,32,10,0.765874,495.88001,0.000226,66.41 -comparator,32,4000,0.24995,608.580012,0.168,130.613 -comparator,32,5000,0.205372,919.240014,0.43,840.47 -comparator,32,6000,0.2012,1248.520016,0.928,1.48 -comparator,64,10,0.561562,1008.42002,0.000449,127.626 -comparator,64,4000,0.249905,1437.660027,0.462,558.66 -comparator,64,5000,0.219296,2738.120023,1.989,2.95 -comparator,64,6000,0.221138,2341.220025,1.343,2.59 -comparator,8,10,0.29577,118.580002,6.83e-05,16.053 -comparator,8,5000,0.195502,129.360003,0.0358,21.443 -mult,128,10,9.334627,180734.540854,0.428,1.8 -mult,128,5000,1.78322,314617.244472,997.34,1.63 -mult,16,10,4.730546,3869.040009,0.0107,641.517 -mult,16,4000,0.821111,9132.620147,14.407,8.03 -mult,16,5000,0.820059,9583.420143,20.175,8.5 -mult,16,6000,0.831308,8594.600132,21.106,7.15 -mult,32,10,7.575772,12412.680067,0.0229,1.18 -mult,32,4000,1.091389,31262.980534,65.471,2.49 -mult,32,5000,1.092153,31497.200524,79.554,2.58 -mult,32,6000,1.084816,33519.920555,103.798,2.91 -mult,64,10,4.7933,46798.920227,0.103,5.46 -mult,64,4000,1.411752,93087.261425,227.876,6.05 -mult,64,5000,1.404875,94040.801492,298.667,6.16 -mult,64,6000,1.415466,89931.661403,337.302,5.63 -mult,8,10,2.076433,1009.399998,0.00206,211.637 -mult,8,5000,0.552339,4261.040075,5.543,5.05 -mux2,1,10,0.060639,6.86,5.15e-06,1.19 -mux2,1,10,0.060639,6.86,5.15e-06,1.19 -shifter,128,10,2.758726,9722.580189,0.00789,720.698 -shifter,128,5000,0.401118,19106.080347,6.94,1.23 -shifter,16,10,1.237745,681.100013,0.000441,52.029 -shifter,16,5000,0.209586,2120.720031,1.025,2.15 -shifter,32,10,1.906335,1656.200032,0.00115,118.773 -shifter,32,4000,0.260606,3490.760054,1.282,2.57 -shifter,32,4000,0.260606,3490.760054,1.282,2.57 -shifter,32,4000,0.260606,3490.760054,1.282,2.57 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+mult,8,1818,0.581954,2672.460046,2.2,0.0008663366336633663 +mult,8,1855,0.605444,2332.40004,1.74,0.0007547169811320754 +mult,8,1891,0.605341,2405.90004,1.93,0.0007599153886832364 +mult,8,1927,0.574177,3273.200051,3.43,0.0009600415153087702 +mult,8,1964,0.585681,2746.940044,2.48,0.0008778004073319755 +mult,8,2182,0.550085,4360.02008,5.2,0.0011608615948670944 +mult,8,2545,0.564127,4034.66007,4.58,0.0011772102161100196 +mult,8,5000,0.552339,4261.040075,5.05,0.0011086 +mux2,1,10,0.060639,6.86,1.19,5.149999999999999e-07 +mux2,1,10,0.060639,6.86,1.19,5.149999999999999e-07 +shifter,128,10,2.758726,9722.580189,720.698,0.000789 +shifter,128,5000,0.401118,19106.080347,1.23,0.0013880000000000001 +shifter,16,10,1.237745,681.100013,52.029,4.41e-05 +shifter,16,5000,0.209586,2120.720031,2.15,0.000205 +shifter,32,10,1.906335,1656.200032,118.773,0.000115 +shifter,32,4000,0.260606,3490.760054,2.57,0.0003205 +shifter,32,4000,0.260606,3490.760054,2.57,0.0003205 +shifter,32,4000,0.260606,3490.760054,2.57,0.0003205 +shifter,32,5000,0.238962,4985.260077,4.9,0.0004978 +shifter,32,6000,0.241742,4312.000069,3.71,0.00040183333333333336 +shifter,32,6000,0.241742,4312.000069,3.71,0.00040183333333333336 +shifter,32,6000,0.241742,4312.000069,3.71,0.00040183333333333336 +shifter,64,10,2.919486,4346.300085,210.734,0.000297 +shifter,64,5000,0.358993,9471.700156,6.94,0.0009036 +shifter,8,10,0.622998,244.020005,26.943,1.9e-05 +shifter,8,5000,0.198885,495.88001,300.128,5.6999999999999996e-05 diff --git a/synthDC/ppaFitting.csv b/synthDC/ppaFitting.csv index 882977245..6b88ead61 100644 --- a/synthDC/ppaFitting.csv +++ b/synthDC/ppaFitting.csv @@ -1,13 +1,13 @@ -Module,Metric,Freq,1,N,log(N),Nlog(N),R^2 -add,delay,5000,0.23935453005464438,0.015973094945355207,-0.058207695467226296,-0.002593789781151714,0.9902532112478974 -add,area,5000,-1032.1274349672115,64.4386855922132,374.6678949053879,-3.2579193244904823,0.9999180068922152 -add,area,10,-13.720004131149423,14.699999256147343,3.6067390521177815e-06,9.312480709428003e-08,1.0 -mult,delay,5000,-0.21755360109289562,-0.00033127390710363004,0.36865114245083547,0.0004100845872014472,0.9999815499619515 -mult,area,5000,-29928.193338752997,-11370.538120558254,39122.3984379376,2592.313970431163,0.9998454828501703 -mult,area,10,-24112.991162714883,-8735.874000034026,30452.017533199683,1892.3032427172166,0.9999575675635335 -comparator,delay,5000,0.18302939890710385,-0.001793523907103751,0.00950014684425352,0.0004195522734073458,0.9999387049502957 -comparator,area,5000,1831.2076391201958,303.59984869227907,-1617.4342555852443,-44.475154143873425,0.9990603962758624 -comparator,area,10,-0.23027509289593326,18.299023530396347,-8.48304611908023,-0.4881808064440773,0.9999674500675539 -shifter,delay,5000,0.4107033934426204,0.03923479405737683,-0.19848886911558317,-0.006549393512462493,0.989283342171845 -shifter,area,5000,-3612.7138133224103,-65.6549821150965,1929.186263038338,35.02443853718661,0.9998392000511572 -shifter,area,10,806.0687632950834,120.52125970491868,-682.1783666753405,-5.1440062238735225,0.9998176364985187 +Module,Metric,Freq,1,N,N^2,log2(N),Nlog2(N),R^2 +add,delay,5000,-0.038978555556527635,-0.08911531250030817,-0.00012953428819478948,0.2083593333340971,0.013950093750045424,1.0 +add,area,5000,-1913.1778463362505,-268.21377075092175,-0.4100347526051751,1046.9667200022955,47.59125331263557,1.0 +add,area,10,-13.720001333167332,14.700000312552621,1.3021426840869221e-09,-1.3062278840780171e-10,-9.375775472819561e-08,1.0 +mult,delay,5000,-0.2915958888891911,-0.02828693750009581,-3.445876736121953e-05,0.32169033333357117,0.0044735312500140964,1.0 +mult,area,5000,27780.605184113756,10418.196477973508,26.857274703166343,-24448.387256089416,-1468.2850310678027,1.0 +mult,area,10,-6472.791005245042,-2075.5787013197305,8.20962684330778,5345.246556351299,313.5693677823146,1.0 +comparator,delay,5000,0.1903951111111219,0.000987500000002994,3.427951388890516e-06,3.333333324460974e-06,-0.00012593750000039925,1.0 +comparator,area,5000,-508.51109056188875,-579.7924890645068,-1.0888888741341944,969.5466443383111,101.5524983752957,1.0 +comparator,area,10,-155.6022268893253,-40.3637507501383,-0.07230902908001494,132.9533363336765,8.452500156270371,1.0 +shifter,delay,5000,0.06953233333235516,-0.08957893750031035,-0.00015877864583368578,0.16727300000076853,0.014763625000045773,1.0 +shifter,area,5000,-237.48663487568587,1208.7075255666841,1.5708073263938906,-1678.7400476770383,-166.69187856311666,1.0 +shifter,area,10,-1079.4155736731122,-591.3687615645423,-0.877491337241916,1211.9333560050677,103.11437703155087,1.0 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py index cf7e430b5..691b796c8 100755 --- a/synthDC/ppaSynth.py +++ b/synthDC/ppaSynth.py @@ -14,9 +14,13 @@ def deleteRedundant(LoT): bashCommand = synthStr.format(*synth) outputCPL = subprocess.check_output(['bash','-c', bashCommand]) -widths = ['1'] -modules = ['mux2'] -freqs = ['10'] +d = 0.26 +f = 1/d * 1000 +arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 20, 40] + +widths = ['128'] +modules = ['comparator'] +freqs = [str(round(f+f*x/100)) for x in arr] tech = 'sky90' From b0881495a9275c1a063ed5a23ced119e667bccee Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 19 May 2022 20:31:23 +0000 Subject: [PATCH 27/38] Bug fixed in unpacker and sub/add/mul tests pass TestFloat --- pipelined/regression/sim-fp-batch | 2 +- pipelined/src/fpu/fma.sv | 42 ++-- pipelined/src/fpu/fpu.sv | 3 +- pipelined/src/fpu/unpack.sv | 285 ++++++++++++++++++---------- pipelined/testbench/testbench-fp.sv | 53 +++--- 5 files changed, 239 insertions(+), 146 deletions(-) diff --git a/pipelined/regression/sim-fp-batch b/pipelined/regression/sim-fp-batch index 7e2c6a341..26085239d 100755 --- a/pipelined/regression/sim-fp-batch +++ b/pipelined/regression/sim-fp-batch @@ -7,4 +7,4 @@ # sqrt - test square root # all - test everything -vsim -c -do "do fp.do rv64fp fma" \ No newline at end of file +vsim -c -do "do fp.do rv64fp mul" \ No newline at end of file diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 69d6fc8ee..71d990371 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -43,6 +43,7 @@ module fma( input logic XSgnM, YSgnM, // input signs - memory stage input logic [`NE-1:0] ZExpM, // input exponents - memory stage input logic [`NF:0] XManM, YManM, ZManM, // input mantissa - memory stage + input logic ZOrigDenormE, // is the original precision denormalized input logic XDenormE, YDenormE, ZDenormE, // is denorm input logic XZeroE, YZeroE, ZZeroE, // is zero - execute stage input logic XNaNM, YNaNM, ZNaNM, // is NaN @@ -72,6 +73,7 @@ module fma( logic PSgnE, PSgnM; logic [$clog2(3*`NF+7)-1:0] NormCntE, NormCntM; logic Mult; + logic ZOrigDenormM; fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, @@ -81,11 +83,11 @@ module fma( // E/M pipeline registers flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM); flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM); - flopenrc #($clog2(3*`NF+7)+7) EMRegFma4(clk, reset, FlushM, ~StallM, - {AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0]}, - {AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult}); + flopenrc #($clog2(3*`NF+7)+8) EMRegFma4(clk, reset, FlushM, ~StallM, + {AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0], ZOrigDenormE}, + {AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult, ZOrigDenormM}); - fma2 fma2(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, + fma2 fma2(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZOrigDenormM, .FrmM, .FmtM, .ProdExpM, .AddendStickyM, .KillProdM, .SumM, .NegSumM, .InvZM, .NormCntM, .ZSgnEffM, .PSgnM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .Mult, .FMAResM, .FMAFlgM); @@ -448,6 +450,7 @@ module fma2( input logic [3*`NF+5:0] SumM, // the positive sum input logic NegSumM, // was the sum negitive input logic InvZM, // do you invert Z + input logic ZOrigDenormM, // is the original precision denormalized input logic ZSgnEffM, // the modified Z sign - depends on instruction input logic PSgnM, // the product's sign input logic Mult, // multiply opperation @@ -530,7 +533,7 @@ module fma2( // Select the result /////////////////////////////////////////////////////////////////////////////// - resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, + resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZOrigDenormM, .FrmM, .FmtM, .AddendStickyM, .KillProdM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd, .ZSgnEffM, .PSgnM, .ResultSgn, .CalcPlus1, .Invalid, .Overflow, .Underflow, .ResultDenorm, .ResultExp, .ResultFrac, .FMAResM); @@ -1103,6 +1106,7 @@ module resultselect( input logic KillProdM, // set the product to zero before addition if the product is too small to matter input logic XInfM, YInfM, ZInfM, // inputs are infinity input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN + input logic ZOrigDenormM, // is the original precision denormalized input logic ZSgnEffM, // the modified Z sign - depends on instruction input logic PSgnM, // the product's sign input logic ResultSgn, // the result's sign @@ -1122,7 +1126,7 @@ module resultselect( assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + assign InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end else begin assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end @@ -1138,7 +1142,7 @@ module resultselect( assign XNaNResult = FmtM ? {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; assign YNaNResult = FmtM ? {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; assign ZNaNResult = FmtM ? {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; - assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + assign InvalidResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end else begin assign XNaNResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end @@ -1147,7 +1151,7 @@ module resultselect( {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} : ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; assign InfResult = FmtM ? {InfSgn, {`NE{1'b1}}, (`NF)'(0)} : {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; assign NormResult = FmtM ? {ResultSgn, ResultExp, ResultFrac} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; @@ -1160,7 +1164,7 @@ module resultselect( XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end else begin XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end @@ -1177,13 +1181,13 @@ module resultselect( XNaNResult = {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; YNaNResult = {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; ZNaNResult = {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; - InvalidResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + InvalidResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end else begin XNaNResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; NormResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; @@ -1193,14 +1197,14 @@ module resultselect( XNaNResult = {{`FLEN-`LEN2{1'b1}}, XSgnM, {`NE2{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF2]}; YNaNResult = {{`FLEN-`LEN2{1'b1}}, YSgnM, {`NE2{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF2]}; ZNaNResult = {{`FLEN-`LEN2{1'b1}}, ZSgnEffM, {`NE2{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF2]}; - InvalidResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + InvalidResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; end else begin XNaNResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, (`NF2)'(0)}; - KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`LEN2{1'b1}}, {ResultSgn, (`LEN2-1)'(0)} + {(`LEN2-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`LEN2{1'b1}}, InfSgn, {`NE2{1'b1}}, (`NF2)'(0)}; NormResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, ResultExp[`NE2-1:0], ResultFrac[`NF-1:`NF-`NF2]}; @@ -1231,7 +1235,7 @@ module resultselect( XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end else begin XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end @@ -1248,13 +1252,13 @@ module resultselect( XNaNResult = {{`FLEN-`D_LEN{1'b1}}, XSgnM, {`D_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`D_NF]}; YNaNResult = {{`FLEN-`D_LEN{1'b1}}, YSgnM, {`D_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`D_NF]}; ZNaNResult = {{`FLEN-`D_LEN{1'b1}}, ZSgnEffM, {`D_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`D_NF]}; - InvalidResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + InvalidResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; end else begin XNaNResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; - KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:0], ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`D_LEN{1'b1}}, {ResultSgn, (`D_LEN-1)'(0)} + {(`D_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`D_LEN{1'b1}}, InfSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; NormResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, ResultExp[`D_NE-1:0], ResultFrac[`NF-1:`NF-`D_NF]}; @@ -1264,14 +1268,14 @@ module resultselect( XNaNResult = {{`FLEN-`S_LEN{1'b1}}, XSgnM, {`S_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`S_NF]}; YNaNResult = {{`FLEN-`S_LEN{1'b1}}, YSgnM, {`S_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`S_NF]}; ZNaNResult = {{`FLEN-`S_LEN{1'b1}}, ZSgnEffM, {`S_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`S_NF]}; - InvalidResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + InvalidResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; end else begin XNaNResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; - KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`S_NE-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`S_LEN{1'b1}}, {ResultSgn, (`S_LEN-1)'(0)} + {(`S_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`S_LEN{1'b1}}, InfSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; NormResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, ResultExp[`S_NE-1:0], ResultFrac[`NF-1:`NF-`S_NF]}; @@ -1289,7 +1293,7 @@ module resultselect( OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; - KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:0], ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:1],ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`H_LEN{1'b1}}, {ResultSgn, (`H_LEN-1)'(0)} + {(`H_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`H_LEN{1'b1}}, InfSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; NormResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, ResultExp[`H_NE-1:0], ResultFrac[`NF-1:`NF-`H_NF]}; diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 7b05b33f2..32b676613 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -104,6 +104,7 @@ module fpu ( logic XInfQ, YInfQ; // is the input infinity - divide logic XExpMaxE; // is the exponent all ones (max value) logic XNormE; // is normal + logic ZOrigDenormE; logic FmtQ; logic FOpCtrlQ; @@ -176,7 +177,7 @@ module fpu ( // unpack unit // - splits FP inputs into their various parts // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) - unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, + unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, .ZOrigDenormE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index a1d96b8b9..6adb23683 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -12,6 +12,7 @@ module unpack ( output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero output logic XInfE, YInfE, ZInfE, // is XYZ infinity + output logic ZOrigDenormE, // is the original precision denormalized output logic XExpMaxE // does X have the maximum exponent (NaN or Inf) ); @@ -47,6 +48,8 @@ module unpack ( assign XExpMaxE = &XExpE; assign YExpMaxE = &YExpE; assign ZExpMaxE = &ZExpE; + + assign OrigDenormE = 1'b0; end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported @@ -69,7 +72,8 @@ module unpack ( // quad and half // double and half - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed + logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; @@ -90,9 +94,15 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // extract the exponent, converting the smaller exponent into the larger precision if nessisary - assign XExpE = FmtE ? X[`FLEN-2:`NF] : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; - assign YExpE = FmtE ? Y[`FLEN-2:`NF] : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; - assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + // - if the original precision had a denormal number convert the exponent value 1 + assign XExpE = FmtE ? X[`FLEN-2:`NF] : XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; + assign YExpE = FmtE ? Y[`FLEN-2:`NF] : YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; + assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + + // is the input (in it's original format) denormalized + assign XOrigDenormE = (FmtE ? 0 : |XLen1[`LEN1-2:`NF1]) & ~XFracZero; + assign YOrigDenormE = (FmtE ? 0 : |YLen1[`LEN1-2:`NF1]) & ~YFracZero; + assign ZOrigDenormE = (FmtE ? 0 : |ZLen1[`LEN1-2:`NF1]) & ~ZFracZero; // extract the fraction, add trailing zeroes to the mantissa if nessisary assign XFracE = FmtE ? X[`NF-1:0] : {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; @@ -129,8 +139,9 @@ module unpack ( // quad and double and half // quad and single and half - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision - logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision + logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision + logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for larger precision assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; @@ -142,6 +153,75 @@ module unpack ( assign YLen2 = &Y[`FLEN-1:`LEN2] ? Y[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; assign ZLen2 = &Z[`FLEN-1:`LEN2] ? Z[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; + // There are 2 case statements + // - one for other singals and one for sgn/exp/frac + // - need two for the dependencies in the expoenent calculation + always_comb begin + case (FmtE) + `FMT: begin // if input is largest precision (`FLEN - ie quad or double) + + // This is the original format so set OrigDenorm to 0 + XOrigDenormE = 1'b0; + YOrigDenormE = 1'b0; + ZOrigDenormE = 1'b0; + + // is the exponent non-zero + XExpNonzero = |X[`FLEN-2:`NF]; + YExpNonzero = |Y[`FLEN-2:`NF]; + ZExpNonzero = |Z[`FLEN-2:`NF]; + + // is the exponent all 1's + XExpMaxE = &X[`FLEN-2:`NF]; + YExpMaxE = &Y[`FLEN-2:`NF]; + ZExpMaxE = &Z[`FLEN-2:`NF]; + end + `FMT1: begin // if input is larger precsion (`LEN1 - double or single) + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen1[`LEN1-2:`NF1] & ~XFracZero; + YOrigDenormE = ~|YLen1[`LEN1-2:`NF1] & ~YFracZero; + ZOrigDenormE = ~|ZLen1[`LEN1-2:`NF1] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen1[`LEN1-2:`NF1]; + YExpNonzero = |YLen1[`LEN1-2:`NF1]; + ZExpNonzero = |ZLen1[`LEN1-2:`NF1]; + + // is the exponent all 1's + XExpMaxE = &XLen1[`LEN1-2:`NF1]; + YExpMaxE = &YLen1[`LEN1-2:`NF1]; + ZExpMaxE = &ZLen1[`LEN1-2:`NF1]; + end + `FMT2: begin // if input is smallest precsion (`LEN2 - single or half) + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen2[`LEN2-2:`NF2] & ~XFracZero; + YOrigDenormE = ~|YLen2[`LEN2-2:`NF2] & ~YFracZero; + ZOrigDenormE = ~|ZLen2[`LEN2-2:`NF2] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen2[`LEN2-2:`NF2]; + YExpNonzero = |YLen2[`LEN2-2:`NF2]; + ZExpNonzero = |ZLen2[`LEN2-2:`NF2]; + + // is the exponent all 1's + XExpMaxE = &XLen2[`LEN2-2:`NF2]; + YExpMaxE = &YLen2[`LEN2-2:`NF2]; + ZExpMaxE = &ZLen2[`LEN2-2:`NF2]; + end + default: begin + XOrigDenormE = 0; + YOrigDenormE = 0; + ZOrigDenormE = 0; + XExpNonzero = 0; + YExpNonzero = 0; + ZExpNonzero = 0; + XExpMaxE = 0; + YExpMaxE = 0; + ZExpMaxE = 0; + end + endcase + end always_comb begin case (FmtE) `FMT: begin // if input is largest precision (`FLEN - ie quad or double) @@ -159,16 +239,6 @@ module unpack ( XFracE = X[`NF-1:0]; YFracE = Y[`NF-1:0]; ZFracE = Z[`NF-1:0]; - - // is the exponent non-zero - XExpNonzero = |X[`FLEN-2:`NF]; - YExpNonzero = |Y[`FLEN-2:`NF]; - ZExpNonzero = |Z[`FLEN-2:`NF]; - - // is the exponent all 1's - XExpMaxE = &X[`FLEN-2:`NF]; - YExpMaxE = &Y[`FLEN-2:`NF]; - ZExpMaxE = &Z[`FLEN-2:`NF]; end `FMT1: begin // if input is larger precsion (`LEN1 - double or single) @@ -186,24 +256,14 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the larger precision's exponent to use the largest precision's bias - XExpE = {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; - YExpE = {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; - ZExpE = {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + XExpE = XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; + YExpE = YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; + ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; YFracE = {YLen1[`NF1-1:0], (`NF-`NF1)'(0)}; ZFracE = {ZLen1[`NF1-1:0], (`NF-`NF1)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen1[`LEN1-2:`NF1]; - YExpNonzero = |YLen1[`LEN1-2:`NF1]; - ZExpNonzero = |ZLen1[`LEN1-2:`NF1]; - - // is the exponent all 1's - XExpMaxE = &XLen1[`LEN1-2:`NF1]; - YExpMaxE = &YLen1[`LEN1-2:`NF1]; - ZExpMaxE = &ZLen1[`LEN1-2:`NF1]; end `FMT2: begin // if input is smallest precsion (`LEN2 - single or half) @@ -221,24 +281,14 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the smallest precision's exponent to use the largest precision's bias - XExpE = {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]}; - YExpE = {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]}; - ZExpE = {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]}; + XExpE = XOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]}; + YExpE = YOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]}; + ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen2[`NF2-1:0], (`NF-`NF2)'(0)}; YFracE = {YLen2[`NF2-1:0], (`NF-`NF2)'(0)}; ZFracE = {ZLen2[`NF2-1:0], (`NF-`NF2)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen2[`LEN2-2:`NF2]; - YExpNonzero = |YLen2[`LEN2-2:`NF2]; - ZExpNonzero = |ZLen2[`LEN2-2:`NF2]; - - // is the exponent all 1's - XExpMaxE = &XLen2[`LEN2-2:`NF2]; - YExpMaxE = &YLen2[`LEN2-2:`NF2]; - ZExpMaxE = &ZLen2[`LEN2-2:`NF2]; end default: begin XSgnE = 0; @@ -250,12 +300,6 @@ module unpack ( XFracE = 0; YFracE = 0; ZFracE = 0; - XExpNonzero = 0; - YExpNonzero = 0; - ZExpNonzero = 0; - XExpMaxE = 0; - YExpMaxE = 0; - ZExpMaxE = 0; end endcase end @@ -271,9 +315,10 @@ module unpack ( // `Q_FMT | `D_FMT | `S_FMT | `H_FMT precision's format value - Q=11 D=01 S=00 H=10 - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision - logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision - logic [`LEN2-1:0] XLen3, YLen3, ZLen3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision + logic [`D_LEN-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision + logic [`S_LEN-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision + logic [`H_LEN-1:0] XLen3, YLen3, ZLen3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision + logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for double precision assign XLen1 = &X[`Q_LEN-1:`D_LEN] ? X[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; @@ -290,6 +335,83 @@ module unpack ( assign YLen3 = &Y[`Q_LEN-1:`H_LEN] ? Y[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; assign ZLen3 = &Z[`Q_LEN-1:`H_LEN] ? Z[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + + // There are 2 case statements + // - one for other singals and one for sgn/exp/frac + // - need two for the dependencies in the expoenent calculation + always_comb begin + case (FmtE) + 2'b11: begin // if input is quad percision + + // This is the original format so set OrigDenorm to 0 + XOrigDenormE = 1'b0; + YOrigDenormE = 1'b0; + ZOrigDenormE = 1'b0; + + // is the exponent non-zero + XExpNonzero = |X[`Q_LEN-2:`Q_NF]; + YExpNonzero = |Y[`Q_LEN-2:`Q_NF]; + ZExpNonzero = |Z[`Q_LEN-2:`Q_NF]; + + // is the exponent all 1's + XExpMaxE = &X[`Q_LEN-2:`Q_NF]; + YExpMaxE = &Y[`Q_LEN-2:`Q_NF]; + ZExpMaxE = &Z[`Q_LEN-2:`Q_NF]; + end + 2'b01: begin // if input is double percision + + // is the exponent all 1's + XExpMaxE = &XLen1[`D_LEN-2:`D_NF]; + YExpMaxE = &YLen1[`D_LEN-2:`D_NF]; + ZExpMaxE = &ZLen1[`D_LEN-2:`D_NF]; + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen1[`D_LEN-2:`D_NF] & ~XFracZero; + YOrigDenormE = ~|YLen1[`D_LEN-2:`D_NF] & ~YFracZero; + ZOrigDenormE = ~|ZLen1[`D_LEN-2:`D_NF] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen1[`D_LEN-2:`D_NF]; + YExpNonzero = |YLen1[`D_LEN-2:`D_NF]; + ZExpNonzero = |ZLen1[`D_LEN-2:`D_NF]; + end + 2'b00: begin // if input is single percision + + // is the exponent all 1's + XExpMaxE = &XLen2[`S_LEN-2:`S_NF]; + YExpMaxE = &YLen2[`S_LEN-2:`S_NF]; + ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF]; + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen2[`S_LEN-2:`S_NF] & ~XFracZero; + YOrigDenormE = ~|YLen2[`S_LEN-2:`S_NF] & ~YFracZero; + ZOrigDenormE = ~|ZLen2[`S_LEN-2:`S_NF] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen2[`S_LEN-2:`S_NF]; + YExpNonzero = |YLen2[`S_LEN-2:`S_NF]; + ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF]; + end + 2'b10: begin // if input is half percision + + // is the exponent all 1's + XExpMaxE = &XLen3[`H_LEN-2:`H_NF]; + YExpMaxE = &YLen3[`H_LEN-2:`H_NF]; + ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF]; + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen3[`H_LEN-2:`H_NF] & ~XFracZero; + YOrigDenormE = ~|YLen3[`H_LEN-2:`H_NF] & ~YFracZero; + ZOrigDenormE = ~|ZLen3[`H_LEN-2:`H_NF] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen3[`H_LEN-2:`H_NF]; + YExpNonzero = |YLen3[`H_LEN-2:`H_NF]; + ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF]; + end + endcase + end + always_comb begin case (FmtE) 2'b11: begin // if input is quad percision @@ -307,16 +429,6 @@ module unpack ( XFracE = X[`Q_NF-1:0]; YFracE = Y[`Q_NF-1:0]; ZFracE = Z[`Q_NF-1:0]; - - // is the exponent non-zero - XExpNonzero = |X[`Q_LEN-2:`Q_NF]; - YExpNonzero = |Y[`Q_LEN-2:`Q_NF]; - ZExpNonzero = |Z[`Q_LEN-2:`Q_NF]; - - // is the exponent all 1's - XExpMaxE = &X[`Q_LEN-2:`Q_NF]; - YExpMaxE = &Y[`Q_LEN-2:`Q_NF]; - ZExpMaxE = &Z[`Q_LEN-2:`Q_NF]; end 2'b01: begin // if input is double percision // extract sign bit @@ -333,24 +445,15 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the double precsion exponent into quad precsion - XExpE = {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]}; - YExpE = {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]}; - ZExpE = {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; + + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; YFracE = {YLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; ZFracE = {ZLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen1[`D_LEN-2:`D_NE]; - YExpNonzero = |YLen1[`D_LEN-2:`D_NE]; - ZExpNonzero = |ZLen1[`D_LEN-2:`D_NE]; - - // is the exponent all 1's - XExpMaxE = &XLen1[`D_LEN-2:`D_NE]; - YExpMaxE = &YLen1[`D_LEN-2:`D_NE]; - ZExpMaxE = &ZLen1[`D_LEN-2:`D_NE]; end 2'b00: begin // if input is single percision // extract sign bit @@ -367,24 +470,14 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the single precsion exponent into quad precsion - XExpE = {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]}; - YExpE = {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]}; - ZExpE = {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]}; + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; YFracE = {YLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; ZFracE = {ZLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen2[`S_LEN-2:`S_NF]; - YExpNonzero = |YLen2[`S_LEN-2:`S_NF]; - ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF]; - - // is the exponent all 1's - XExpMaxE = &XLen2[`S_LEN-2:`S_NF]; - YExpMaxE = &YLen2[`S_LEN-2:`S_NF]; - ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF]; end 2'b10: begin // if input is half percision // extract sign bit @@ -399,26 +492,16 @@ module unpack ( // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/denorm/inf/NaN values - + // convert the half precsion exponent into quad precsion - XExpE = {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]}; - YExpE = {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]}; - ZExpE = {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]}; + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; YFracE = {YLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; ZFracE = {ZLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen3[`H_LEN-2:`H_NF]; - YExpNonzero = |YLen3[`H_LEN-2:`H_NF]; - ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF]; - - // is the exponent all 1's - XExpMaxE = &XLen3[`H_LEN-2:`H_NF]; - YExpMaxE = &YLen3[`H_LEN-2:`H_NF]; - ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF]; end endcase end diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 42aa7312b..d79bc6d19 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -40,6 +40,7 @@ module testbenchfp; logic [1:0] FmaFmtVal, FmtVal; logic [2:0] UnitVal, OpCtrlVal, FrmVal; logic NaNGood; + logic ZOrigDenorm, FmaRneZOrigDenorm, FmaRzZOrigDenorm, FmaRuZOrigDenorm, FmaRdZOrigDenorm, FmaRnmZOrigDenorm; logic FmaRneNaNGood, FmaRzNaNGood, FmaRuNaNGood, FmaRdNaNGood, FmaRnmNaNGood; logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat logic [`FLEN-1:0] FmaRneX, FmaRneY, FmaRneZ; // inputs read from TestFloat @@ -628,7 +629,7 @@ module testbenchfp; .XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn), .FmaNum, .XExpE(FmaRneXExp), .YExpE(FmaRneYExp), .ZExpE(FmaRneZExp), .XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan), - .XNaNE(FmaRneXNaN), .YNaNE(FmaRneYNaN), .ZNaNE(FmaRneZNaN), + .XNaNE(FmaRneXNaN), .YNaNE(FmaRneYNaN), .ZNaNE(FmaRneZNaN), .ZOrigDenormE(FmaRneZOrigDenorm), .XSNaNE(FmaRneXSNaN), .YSNaNE(FmaRneYSNaN), .ZSNaNE(FmaRneZSNaN), .XDenormE(FmaRneXDenorm), .YDenormE(FmaRneYDenorm), .ZDenormE(FmaRneZDenorm), .XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero), @@ -638,7 +639,7 @@ module testbenchfp; .XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), .FmaNum, .FmaModFmt, .XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp), .XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan), - .XNaNE(FmaRzXNaN), .YNaNE(FmaRzYNaN), .ZNaNE(FmaRzZNaN), + .XNaNE(FmaRzXNaN), .YNaNE(FmaRzYNaN), .ZNaNE(FmaRzZNaN), .ZOrigDenormE(FmaRzZOrigDenorm), .XSNaNE(FmaRzXSNaN), .YSNaNE(FmaRzYSNaN), .ZSNaNE(FmaRzZSNaN), .XDenormE(FmaRzXDenorm), .YDenormE(FmaRzYDenorm), .ZDenormE(FmaRzZDenorm), .XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero), @@ -648,7 +649,7 @@ module testbenchfp; .XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), .FmaNum, .FmaModFmt, .XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp), .XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan), - .XNaNE(FmaRuXNaN), .YNaNE(FmaRuYNaN), .ZNaNE(FmaRuZNaN), + .XNaNE(FmaRuXNaN), .YNaNE(FmaRuYNaN), .ZNaNE(FmaRuZNaN), .ZOrigDenormE(FmaRuZOrigDenorm), .XSNaNE(FmaRuXSNaN), .YSNaNE(FmaRuYSNaN), .ZSNaNE(FmaRuZSNaN), .XDenormE(FmaRuXDenorm), .YDenormE(FmaRuYDenorm), .ZDenormE(FmaRuZDenorm), .XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero), @@ -658,7 +659,7 @@ module testbenchfp; .XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), .FmaNum, .FmaModFmt, .XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp), .XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan), - .XNaNE(FmaRdXNaN), .YNaNE(FmaRdYNaN), .ZNaNE(FmaRdZNaN), + .XNaNE(FmaRdXNaN), .YNaNE(FmaRdYNaN), .ZNaNE(FmaRdZNaN), .ZOrigDenormE(FmaRdZOrigDenorm), .XSNaNE(FmaRdXSNaN), .YSNaNE(FmaRdYSNaN), .ZSNaNE(FmaRdZSNaN), .XDenormE(FmaRdXDenorm), .YDenormE(FmaRdYDenorm), .ZDenormE(FmaRdZDenorm), .XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero), @@ -667,7 +668,7 @@ module testbenchfp; readfmavectors readfmarnmvectors (.clk, .Frm(`RNM), .TestVector(FmaRnmVectors[VectorNum]), .VectorNum, .Ans(FmaRnmAns), .AnsFlags(FmaRnmAnsFlags), .XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), .FmaNum, .FmaModFmt, .XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp), - .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), + .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), .ZOrigDenormE(FmaRnmZOrigDenorm), .XNaNE(FmaRnmXNaN), .YNaNE(FmaRnmYNaN), .ZNaNE(FmaRnmZNaN), .XSNaNE(FmaRnmXSNaN), .YSNaNE(FmaRnmYSNaN), .ZSNaNE(FmaRnmZSNaN), .XDenormE(FmaRnmXDenorm), .YDenormE(FmaRnmYDenorm), .ZDenormE(FmaRnmZDenorm), @@ -677,7 +678,7 @@ module testbenchfp; readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlags(AnsFlags), .SrcA, .XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), .Unit (UnitVal), .XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), .TestNum, .OpCtrl(OpCtrlVal), - .XManE(XMan), .YManE(YMan), .ZManE(ZMan), + .XManE(XMan), .YManE(YMan), .ZManE(ZMan), .ZOrigDenormE(ZOrigDenorm), .XNaNE(XNaN), .YNaNE(YNaN), .ZNaNE(ZNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .ZSNaNE(ZSNaN), .XDenormE(XDenorm), .YDenormE(YDenorm), .ZDenormE(ZDenorm), @@ -709,7 +710,7 @@ module testbenchfp; .NormCntE(FmaRneNormCnt), .ZSgnEffE(FmaRneZSgnEff), .PSgnE(FmaRnePSgn), .ProdExpE(FmaRneProdExp), .AddendStickyE(FmaRneAddendSticky), .KillProdE(FmaRneSumKillProd)); fma2 fma2rne(.XSgnM(FmaRneXSgn), .YSgnM(FmaRneYSgn), - .ZExpM(FmaRneZExp), + .ZExpM(FmaRneZExp), .ZOrigDenormM(FmaRneZOrigDenorm), .XManM(FmaRneXMan), .YManM(FmaRneYMan), .ZManM(FmaRneZMan), .XNaNM(FmaRneXNaN), .YNaNM(FmaRneYNaN), .ZNaNM(FmaRneZNaN), .XZeroM(FmaRneXZero), .YZeroM(FmaRneYZero), .ZZeroM(FmaRneZZero), @@ -728,7 +729,7 @@ module testbenchfp; .NormCntE(FmaRzNormCnt), .ZSgnEffE(FmaRzZSgnEff), .PSgnE(FmaRzPSgn), .ProdExpE(FmaRzProdExp), .AddendStickyE(FmaRzAddendSticky), .KillProdE(FmaRzSumKillProd)); fma2 fma2rz(.XSgnM(FmaRzXSgn), .YSgnM(FmaRzYSgn), - .ZExpM(FmaRzZExp), + .ZExpM(FmaRzZExp), .ZOrigDenormM(FmaRzZOrigDenorm), .XManM(FmaRzXMan), .YManM(FmaRzYMan), .ZManM(FmaRzZMan), .XNaNM(FmaRzXNaN), .YNaNM(FmaRzYNaN), .ZNaNM(FmaRzZNaN), .XZeroM(FmaRzXZero), .YZeroM(FmaRzYZero), .ZZeroM(FmaRzZZero), @@ -747,7 +748,7 @@ module testbenchfp; .NormCntE(FmaRuNormCnt), .ZSgnEffE(FmaRuZSgnEff), .PSgnE(FmaRuPSgn), .ProdExpE(FmaRuProdExp), .AddendStickyE(FmaRuAddendSticky), .KillProdE(FmaRuSumKillProd)); fma2 fma2ru(.XSgnM(FmaRuXSgn), .YSgnM(FmaRuYSgn), - .ZExpM(FmaRuZExp), + .ZExpM(FmaRuZExp), .ZOrigDenormM(FmaRuZOrigDenorm), .XManM(FmaRuXMan), .YManM(FmaRuYMan), .ZManM(FmaRuZMan), .XNaNM(FmaRuXNaN), .YNaNM(FmaRuYNaN), .ZNaNM(FmaRuZNaN), .XZeroM(FmaRuXZero), .YZeroM(FmaRuYZero), .ZZeroM(FmaRuZZero), @@ -766,7 +767,7 @@ module testbenchfp; .NormCntE(FmaRdNormCnt), .ZSgnEffE(FmaRdZSgnEff), .PSgnE(FmaRdPSgn), .ProdExpE(FmaRdProdExp), .AddendStickyE(FmaRdAddendSticky), .KillProdE(FmaRdSumKillProd)); fma2 fma2rd(.XSgnM(FmaRdXSgn), .YSgnM(FmaRdYSgn), - .ZExpM(FmaRdZExp), + .ZExpM(FmaRdZExp), .ZOrigDenormM(FmaRdZOrigDenorm), .XManM(FmaRdXMan), .YManM(FmaRdYMan), .ZManM(FmaRdZMan), .XNaNM(FmaRdXNaN), .YNaNM(FmaRdYNaN), .ZNaNM(FmaRdZNaN), .XZeroM(FmaRdXZero), .YZeroM(FmaRdYZero), .ZZeroM(FmaRdZZero), @@ -785,7 +786,7 @@ module testbenchfp; .NormCntE(FmaRnmNormCnt), .ZSgnEffE(FmaRnmZSgnEff), .PSgnE(FmaRnmPSgn), .ProdExpE(FmaRnmProdExp), .AddendStickyE(FmaRnmAddendSticky), .KillProdE(FmaRnmSumKillProd)); fma2 fma2rnm(.XSgnM(FmaRnmXSgn), .YSgnM(FmaRnmYSgn), - .ZExpM(FmaRnmZExp), + .ZExpM(FmaRnmZExp), .ZOrigDenormM(FmaRmeZOrigDenorm), .XManM(FmaRnmXMan), .YManM(FmaRnmYMan), .ZManM(FmaRnmZMan), .XNaNM(FmaRnmXNaN), .YNaNM(FmaRnmYNaN), .ZNaNM(FmaRnmZNaN), .XZeroM(FmaRnmXZero), .YZeroM(FmaRnmYZero), .ZZeroM(FmaRnmZZero), @@ -800,10 +801,10 @@ module testbenchfp; .XManE(XMan), .YManE(YMan), .ZManE(ZMan), .XDenormE(XDenorm), .YDenormE(YDenorm), .ZDenormE(ZDenorm), .XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero), - .FOpCtrlE(3'b0), .FmtE(ModFmt), .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, + .FOpCtrlE(OpCtrlVal), .FmtE(ModFmt), .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, .ProdExpE, .AddendStickyE, .KillProdE); fma2 fma2(.XSgnM(XSgn), .YSgnM(YSgn), - .ZExpM(ZExp), + .ZExpM(ZExp), .ZOrigDenormM(ZOrigDenorm), .XManM(XMan), .YManM(YMan), .ZManM(ZMan), .XNaNM(XNaN), .YNaNM(YNaN), .ZNaNM(ZNaN), .XZeroM(XZero), .YZeroM(YZero), .ZZeroM(ZZero), @@ -922,7 +923,6 @@ module testbenchfp; end end - // check results on falling edge of clk always @(negedge clk) begin case (UnitVal) @@ -940,6 +940,9 @@ module testbenchfp; `CVTFPUNIT: ResFlags = CvtFpFlgM; endcase + // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: + // - the sign of the NaN does not matter for the opperations being tested + // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter case (FmaFmtVal) 4'b11: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneX[`Q_LEN-2:`Q_NF],1'b1,FmaRneX[`Q_NF-2:0]})) | @@ -1035,16 +1038,20 @@ module testbenchfp; case (FmtVal) 4'b11: NaNGood = ((AnsFlags[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | - (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | + (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); 4'b01: NaNGood = ((AnsFlags[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | - (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | + (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); 4'b00: NaNGood = ((AnsFlags[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | - (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | + (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); 4'b10: NaNGood = ((AnsFlags[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | - (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | + (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]}))); endcase else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format case (OpCtrlVal[1:0]) @@ -1172,6 +1179,7 @@ module readfmavectors ( input logic [31:0] VectorNum, input logic [31:0] FmaNum, output logic [`FLEN-1:0] Ans, + output logic ZOrigDenormE, output logic [4:0] AnsFlags, output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) @@ -1221,7 +1229,7 @@ module readfmavectors ( unpack unpack(.X, .Y, .Z, .FmtE(FmaModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, - .XExpMaxE); + .XExpMaxE, .ZOrigDenormE); endmodule @@ -1261,6 +1269,7 @@ module readvectors ( output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero output logic XInfE, YInfE, ZInfE, // is XYZ infinity output logic XNormE, XExpMaxE, + output logic ZOrigDenormE, output logic [`FLEN-1:0] X, Y, Z ); @@ -1274,14 +1283,12 @@ module readvectors ( case (Fmt) 2'b11: begin // quad X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, `Q_NF'h0}; if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; Ans = TestVector[8+(`Q_LEN-1):8]; end 2'b01: begin // double X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, `D_NF'h0}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; @@ -1290,7 +1297,6 @@ module readvectors ( end 2'b00: begin // single X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, `S_NF'h0}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; @@ -1299,7 +1305,6 @@ module readvectors ( end 2'b10: begin // half X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, `H_NF'h0}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; @@ -1534,5 +1539,5 @@ module readvectors ( unpack unpack(.X, .Y, .Z, .FmtE(ModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, - .XExpMaxE); + .XExpMaxE, .ZOrigDenormE); endmodule \ No newline at end of file From bc4804d90aff90ea261ca6f9fcc06502c96512f5 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 19 May 2022 20:34:06 +0000 Subject: [PATCH 28/38] fixed lint warning --- pipelined/src/fpu/fpu.sv | 2 +- pipelined/src/fpu/unpack.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 32b676613..b4b5a2e98 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -193,7 +193,7 @@ module fpu ( .XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM, - .FOpCtrlE, + .FOpCtrlE, .ZOrigDenormE, .FmtE, .FmtM, .FrmM, .FMAFlgM, .FMAResM); diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 6adb23683..eadaa7f2b 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -49,7 +49,7 @@ module unpack ( assign YExpMaxE = &YExpE; assign ZExpMaxE = &ZExpE; - assign OrigDenormE = 1'b0; + assign ZOrigDenormE = 1'b0; end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported From 7d2bfb6db8c85ada8f184596ee534483aed7e4ea Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 19 May 2022 16:21:38 -0700 Subject: [PATCH 29/38] parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do --- pipelined/regression/wally-pipelined.do | 4 ++-- pipelined/testbench/testbench-linux.sv | 22 ++++++++++++---------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index cf116da6d..ad73634dc 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -34,7 +34,7 @@ vlib work if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 #-- Run the Simulation @@ -48,7 +48,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } elseif {$2 eq "buildroot-no-trace"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=1 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 #-- Run the Simulation diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index f405af48f..b397ec70c 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -27,7 +27,7 @@ `include "wally-config.vh" -`define DEBUG_TRACE 0 +// `define DEBUG_TRACE 0 // *** move this info down below and remove this line if parametrization works // Debug Levels // 0: don't check against QEMU // 1: print disagreements with QEMU, but only halt on PCW disagreements @@ -46,6 +46,7 @@ module testbench; parameter CHECKPOINT = 0; parameter RISCV_DIR = "/opt/riscv"; parameter NO_IE_MTIME_CHECKPOINT = 0; + parameter DEBUG_TRACE = 32; @@ -237,6 +238,7 @@ module testbench; logic clk, reset_ext; logic reset; initial begin reset_ext <= 1; # 22; reset_ext <= 0; end + initial begin $display(DEBUG_TRACE); #1; end // *** remove this once debug trace is parametrized always begin clk <= 1; # 5; clk <= 0; # 5; end // Wally Interface logic [`AHBW-1:0] HRDATAEXT; @@ -482,7 +484,7 @@ module testbench; if (checkInstrM) begin \ // read 1 line of the trace file \ matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \ - if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ + if(DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ // extract PC, Instr \ matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \ if (`"STAGE`"=="M") begin \ @@ -566,14 +568,14 @@ module testbench; `define checkEQ(NAME, VAL, EXPECTED) \ if(VAL != EXPECTED) begin \ $display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \ - if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \ + if ((NAME == "PCW") | (DEBUG_TRACE >= 2)) fault = 1; \ end `define checkCSR(CSR) \ begin \ if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ - if(`DEBUG_TRACE >= 3) fault = 1; \ + if(DEBUG_TRACE >= 3) fault = 1; \ end \ end @@ -658,13 +660,13 @@ module testbench; // end sim if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop; fault = 0; - if (`DEBUG_TRACE >= 1) begin + if (DEBUG_TRACE >= 1) begin `checkEQ("PCW",PCW,ExpectedPCW) //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of // compressed to uncompressed conversion `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) #2; // delay 2 ns. - if(`DEBUG_TRACE >= 5) begin + if(DEBUG_TRACE >= 5) begin $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); end @@ -674,13 +676,13 @@ module testbench; `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) end if (MemOpW.substr(0,2) == "Mem") begin - if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); + if(DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) if(MemOpW == "MemR" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); + if(DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); + if(DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) end end @@ -720,7 +722,7 @@ module testbench; $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); $stop; end - end // if (`DEBUG_TRACE >= 1) + end // if (DEBUG_TRACE >= 1) end // if (checkInstrW) end // always @ (negedge clk) From 0982417054512daf5ea40d1e8343643a6b59da6e Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 19 May 2022 17:49:32 -0700 Subject: [PATCH 30/38] Fixed buildroot by adding a second . --- pipelined/testbench/testbench-linux.sv | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index b397ec70c..6718eadc3 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -27,15 +27,6 @@ `include "wally-config.vh" -// `define DEBUG_TRACE 0 // *** move this info down below and remove this line if parametrization works -// Debug Levels -// 0: don't check against QEMU -// 1: print disagreements with QEMU, but only halt on PCW disagreements -// 2: halt on any disagreement with QEMU except CSRs -// 3: halt on all disagreements with QEMU -// 4: print memory accesses whenever they happen -// 5: print everything - module testbench; /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////// CONFIG //////////////////////////////////// @@ -46,8 +37,14 @@ module testbench; parameter CHECKPOINT = 0; parameter RISCV_DIR = "/opt/riscv"; parameter NO_IE_MTIME_CHECKPOINT = 0; - parameter DEBUG_TRACE = 32; - + parameter DEBUG_TRACE = 0; + // Debug Levels + // 0: don't check against QEMU + // 1: print disagreements with QEMU, but only halt on PCW disagreements + // 2: halt on any disagreement with QEMU except CSRs + // 3: halt on all disagreements with QEMU + // 4: print memory accesses whenever they happen + // 5: print everything @@ -238,7 +235,6 @@ module testbench; logic clk, reset_ext; logic reset; initial begin reset_ext <= 1; # 22; reset_ext <= 0; end - initial begin $display(DEBUG_TRACE); #1; end // *** remove this once debug trace is parametrized always begin clk <= 1; # 5; clk <= 0; # 5; end // Wally Interface logic [`AHBW-1:0] HRDATAEXT; @@ -658,7 +654,7 @@ module testbench; // turn on waves if (AttemptedInstructionCount == INSTR_WAVEON) $stop; // end sim - if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop; + if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end fault = 0; if (DEBUG_TRACE >= 1) begin `checkEQ("PCW",PCW,ExpectedPCW) From 05d14bdb3cbe3baf779a90af45bec41e1e92701c Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 19 May 2022 17:50:48 -0700 Subject: [PATCH 31/38] Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py --- pipelined/regression/wally-pipelined-batch.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 6891c7d6c..85d8513ec 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -35,7 +35,7 @@ vlib wkdir/work_${1}_${2} if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084 run -all From a5490c7096decde1fef5f24c977e46caa7bcda7b Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 19 May 2022 17:51:26 -0700 Subject: [PATCH 32/38] Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace --- pipelined/regression/wally-pipelined.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index ad73634dc..0dadea94b 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -48,7 +48,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } elseif {$2 eq "buildroot-no-trace"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=1 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=0 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 #-- Run the Simulation From 3b4286ec331ecffb5d5fbe998d21e0453e9ab9c3 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 19 May 2022 18:30:59 -0700 Subject: [PATCH 33/38] fixed lint autofailing due to no log being produced in regression-wally --- pipelined/regression/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index d98d59368..3daadf769 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -40,7 +40,7 @@ configs = [ TestCase( name="lints", variant="all", - cmd="./lint-wally &> {}", + cmd="./lint-wally | tee {}", grepstr="All lints run with no errors or warnings" ) ] From 4a2538455d1f9f4e427b7d379411219b90b32182 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 19 May 2022 18:31:46 -0700 Subject: [PATCH 34/38] added documentation for ahblite burst types to ahblite.sv --- pipelined/src/ebu/ahblite.sv | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index a68370cdb..35b3797bb 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -123,6 +123,19 @@ module ahblite ( assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH + + /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. + 000: Single (SINGLE) + 001: Increment burst of undefined length (INCR) + 010: 4-beat wrapping burst (WRAP4) [wraps if X in 000X0000] + 011: 4-beat incrementing burst (INCR4) + 100: 8-beat wrapping burst (WRAP8) [wraps if X in 00X00000 changes] + 101: 8-beat incrementing burst (INCR8) + 110: 16-beat wrapping burst (WRAP16) [wraps if X in 0X000000] + 111: 16-beat incrementing burst (INCR16) + */ + + assign HPROT = 4'b0011; // not used; see Section 3.7 assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise assign HMASTLOCK = 0; // no locking supported From 230aae000ecbd7aa0cc7e126bee00b20ad15243a Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Fri, 20 May 2022 01:59:19 +0000 Subject: [PATCH 35/38] fixed dynamic energy units --- addins/riscv-arch-test | 2 +- synthDC/ppaAnalyze.py | 14 ++++++------ synthDC/ppaData.csv | 52 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+), 8 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99bd..307c77b26 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index 56e8b2f83..fadc45eb8 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -62,7 +62,7 @@ def getVals(module, freq, var): units = " (nW)" elif (var == 'denergy'): ind = 6 - units = " (uJ)" #fix check math + units = " (pJ)" else: error @@ -151,10 +151,10 @@ def plotPPA(module, freq, var, ax=None, fits='clsgn'): def makePlots(mod, freq): fig, axs = plt.subplots(2, 2) - plotPPA(mod, freq, 'delay', ax=axs[0,0], fits='cgl') - plotPPA(mod, freq, 'area', ax=axs[0,1], fits='clg') + plotPPA(mod, freq, 'delay', ax=axs[0,0], fits='cg') + plotPPA(mod, freq, 'area', ax=axs[0,1], fits='s') plotPPA(mod, freq, 'lpower', ax=axs[1,0], fits='c') - plotPPA(mod, freq, 'denergy', ax=axs[1,1], fits='glc') + plotPPA(mod, freq, 'denergy', ax=axs[1,1], fits='s') plt.suptitle(mod + " (target " + str(freq) + "MHz)") plt.show() @@ -254,8 +254,8 @@ allSynths = getData() writeCSV(allSynths) # makeCoefTable() -freqPlot('comparator', 8) +# freqPlot('add', 64) -# makePlots('shifter', 5000) +makePlots('shifter', 5000) -# plotPPA('comparator', 5000, 'delay', fits='cls') \ No newline at end of file +# plotPPA('mult', 5000, 'delay', fits='cls') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 9e09c3403..56489568a 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -66,20 +66,72 @@ add,64,6000,0.328457,3749.480066,1.77,0.000391 add,8,10,0.940062,103.879999,24.765,2.41e-05 add,8,5000,0.199689,197.960003,83.576,2.26e-05 comparator,128,10,0.842074,1997.240039,243.506,8.7e-05 +comparator,128,2308,0.406531,2810.640055,437.781,0.00016637781629116118 +comparator,128,3077,0.324985,2559.760047,659.43,0.00017159571010724734 +comparator,128,3538,0.282712,3158.540057,1.6,0.00026483889202939516 +comparator,128,3615,0.276605,3092.880056,1.5,0.00026445366528354077 +comparator,128,3692,0.270828,3380.020055,2.0,0.00030173347778981584 +comparator,128,3769,0.27069,3741.640049,2.91,0.0003372247280445741 +comparator,128,3846,0.273602,4038.58005,3.61,0.0003967758710348414 +comparator,128,3923,0.256043,4153.240051,3.84,0.00038083099668620956 +comparator,128,4000,0.268954,4027.800041,3.66,0.000414 +comparator,128,4077,0.262622,4638.340054,5.12,0.0004716703458425313 +comparator,128,4154,0.257245,4649.120047,5.1,0.0005149253731343283 +comparator,128,4615,0.265848,4047.400041,3.87,0.0004028169014084507 comparator,128,5000,0.260142,5215.56005,6.0,0.0007416 +comparator,128,5385,0.267095,4787.300045,5.3,0.0007069637883008356 comparator,16,10000,0.146177,1065.260009,1.61,0.00012470000000000002 comparator,16,10,0.576329,252.840005,31.402,1.4400000000000001e-05 +comparator,16,4000,0.249312,280.280005,55.248,1.4524999999999999e-05 comparator,16,5000,0.199026,313.600006,78.893,1.718e-05 +comparator,16,5333,0.186933,318.500006,100.145,2.1938871179448716e-05 comparator,16,6000,0.166568,422.380007,301.506,4.25e-05 +comparator,16,6133,0.16297,441.000006,363.571,4.0110875591064735e-05 +comparator,16,6267,0.168782,502.740008,498.843,5.090154779001117e-05 +comparator,16,6400,0.168782,604.660008,744.154,5.4843749999999995e-05 +comparator,16,6533,0.152969,508.620009,432.277,5.632940456145722e-05 +comparator,16,6667,0.150575,691.880011,816.855,6.88465576721164e-05 +comparator,16,6800,0.146926,723.240009,925.474,8.11764705882353e-05 +comparator,16,6933,0.168782,607.600006,799.51,5.567575364200202e-05 +comparator,16,7067,0.158772,756.56001,1.05,7.04683741332956e-05 +comparator,16,7200,0.15891,771.260013,1.09,7.027777777777778e-05 +comparator,16,8000,0.158838,801.640006,1.19,7.8375e-05 +comparator,16,9333,0.166546,695.800007,927.014,7.243115825565199e-05 comparator,32,10000,0.194087,1451.380013,1.85,0.00024430000000000003 comparator,32,10,0.765874,495.88001,66.41,2.26e-05 +comparator,32,3158,0.304333,684.040013,135.532,4.274857504749842e-05 comparator,32,4000,0.24995,608.580012,130.613,4.2000000000000004e-05 +comparator,32,4211,0.237004,654.640013,145.103,4.701971028259321e-05 +comparator,32,4842,0.206449,781.060011,485.75,7.001239157372987e-05 +comparator,32,4947,0.2021,882.980013,601.459,0.00010491206791995148 comparator,32,5000,0.205372,919.240014,840.47,8.6e-05 +comparator,32,5053,0.197891,805.560012,561.888,7.302592519295468e-05 +comparator,32,5158,0.197393,1203.440015,1.31,0.0001446297014346646 +comparator,32,5263,0.195832,1060.360011,1.06,0.00010450313509405283 +comparator,32,5368,0.199678,1110.340013,1.12,0.0001272354694485842 +comparator,32,5474,0.192304,1188.740012,1.43,0.0001309828279137742 +comparator,32,5579,0.192149,1206.380012,1.44,0.0001609607456533429 +comparator,32,5684,0.203736,1218.140014,1.42,0.00017065446868402533 comparator,32,6000,0.2012,1248.520016,1.48,0.00015466666666666667 +comparator,32,6316,0.2012,1239.700017,1.45,0.0001545281823939202 +comparator,32,7368,0.194845,1391.600021,1.66,0.00024239956568946797 comparator,64,10,0.561562,1008.42002,127.626,4.49e-05 +comparator,64,2727,0.333026,1392.580027,202.012,8.507517418408508e-05 +comparator,64,3636,0.275001,1323.000026,357.28,9.708470847084707e-05 comparator,64,4000,0.249905,1437.660027,558.66,0.0001155 +comparator,64,4182,0.239102,1454.320026,590.635,0.00010975609756097561 +comparator,64,4273,0.233995,1568.980027,683.786,0.00014299087292300491 +comparator,64,4364,0.229142,1709.120026,1.02,0.00017552703941338223 +comparator,64,4455,0.224454,1899.240032,1.34,0.00020493827160493827 +comparator,64,4545,0.229482,2235.380032,2.24,0.0002486248624862486 +comparator,64,4636,0.215691,2072.700029,1.84,0.00021031061259706643 +comparator,64,4727,0.225291,2499.000023,2.71,0.00029236302094351593 +comparator,64,4818,0.214579,2591.120026,2.62,0.00036841012868410125 +comparator,64,4909,0.213022,2891.980026,3.4,0.00038439600733346913 comparator,64,5000,0.219296,2738.120023,2.95,0.0003978 +comparator,64,5455,0.221407,2929.220025,3.36,0.00041191567369385884 comparator,64,6000,0.221138,2341.220025,2.59,0.00022383333333333332 +comparator,64,6364,0.223965,2547.020023,2.94,0.0003914204902576996 comparator,8,10000,0.1136,496.86,810.074,6.46e-05 comparator,8,10909,0.11361,387.1,565.114,5.885049042075351e-05 comparator,8,10,0.29577,118.580002,16.053,6.830000000000001e-06 From 6bc31f2e78565e0d6d01b603fa7a04e0966316ec Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Fri, 20 May 2022 17:19:50 +0000 Subject: [PATCH 36/38] Fixed unpacker bug LT EQ LE pass testfloat --- addins/riscv-arch-test | 2 +- pipelined/regression/sim-fp | 4 +- pipelined/regression/sim-fp-batch | 2 +- pipelined/regression/sim-wally | 2 +- pipelined/regression/sim-wally-batch | 2 +- pipelined/src/fpu/fcmp.sv | 93 +++-- pipelined/src/fpu/fma.sv | 6 +- pipelined/src/fpu/unpack.sv | 6 +- pipelined/testbench/testbench-fp.sv | 514 ++++++++++++++------------- 9 files changed, 344 insertions(+), 287 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..be67c99bd 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/regression/sim-fp b/pipelined/regression/sim-fp index 1d6425425..700a103ab 100755 --- a/pipelined/regression/sim-fp +++ b/pipelined/regression/sim-fp @@ -5,7 +5,7 @@ # add - test addition # sub - test subtraction # div - test division -# sqrt - test square root +# sqrt - test square ro # all - test everything -vsim -do "do fp.do rv64fp mul" +vsim -do "do fp.do rv64fp cmp" diff --git a/pipelined/regression/sim-fp-batch b/pipelined/regression/sim-fp-batch index 26085239d..7e2c6a341 100755 --- a/pipelined/regression/sim-fp-batch +++ b/pipelined/regression/sim-fp-batch @@ -7,4 +7,4 @@ # sqrt - test square root # all - test everything -vsim -c -do "do fp.do rv64fp mul" \ No newline at end of file +vsim -c -do "do fp.do rv64fp fma" \ No newline at end of file diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally index 2f88d9aa2..1cb461ffe 100755 --- a/pipelined/regression/sim-wally +++ b/pipelined/regression/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally-pipelined.do rv32e wally32e" +vsim -do "do wally-pipelined.do rv64gc imperas64f" diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch index 44d986454..91f116976 100755 --- a/pipelined/regression/sim-wally-batch +++ b/pipelined/regression/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-pipelined-batch.do rv32e wally32e" +vsim -c -do "do wally-pipelined-batch.do rv64gc imperas64f" diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 94b75d7e1..6ea8fb62f 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -10,20 +10,21 @@ module fcmp ( - input logic FmtE, // precision 1 = double 0 = single - input logic [2:0] FOpCtrlE, // see above table - input logic XSgnE, YSgnE, // input signs - input logic [`NE-1:0] XExpE, YExpE, // input exponents - input logic [`NF:0] XManE, YManE, // input mantissa - input logic XZeroE, YZeroE, // is zero - input logic XNaNE, YNaNE, // is NaN - input logic XSNaNE, YSNaNE, // is signaling NaN - input logic [`FLEN-1:0] FSrcXE, FSrcYE, // original, non-converted to double, inputs - output logic CmpNVE, // invalid flag - output logic [`FLEN-1:0] CmpResE // compare resilt + input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single + input logic [2:0] FOpCtrlE, // see above table + input logic XSgnE, YSgnE, // input signs + input logic [`NE-1:0] XExpE, YExpE, // input exponents + input logic [`NF:0] XManE, YManE, // input mantissa + input logic XZeroE, YZeroE, // is zero + input logic XNaNE, YNaNE, // is NaN + input logic XSNaNE, YSNaNE, // is signaling NaN + input logic [`FLEN-1:0] FSrcXE, FSrcYE, // original, non-converted to double, inputs + output logic CmpNVE, // invalid flag + output logic [`FLEN-1:0] CmpResE // compare resilt ); logic LTabs, LT, EQ; // is X < or > or = Y + logic [`FLEN-1:0] NaNRes; logic BothZeroE, EitherNaNE, EitherSNaNE; assign LTabs= {1'b0, XExpE, XManE} < {1'b0, YExpE, YManE}; // unsigned comparison, treating FP as integers @@ -65,26 +66,62 @@ module fcmp ( // - inf = inf and -inf = -inf // - return 0 if comparison with NaN (unordered) - logic [`FLEN-1:0] QNaN; // fmin/fmax of two NaNs returns a quiet NaN of the appropriate size // for IEEE, return the payload of X // for RISC-V, return the canonical NaN - if(`IEEE754) assign QNaN = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]}; - else assign QNaN = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0}; - - // when one input is a NaN -output the non-NaN - always_comb begin - case (FOpCtrlE[2:0]) - 3'b111: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Min - : YNaNE ? FSrcXE : LT ? FSrcXE : FSrcYE; - 3'b101: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Max - : YNaNE ? FSrcXE : LT ? FSrcYE : FSrcXE; - 3'b010: CmpResE = {63'b0, (EQ|BothZeroE) & ~EitherNaNE}; // Equal - 3'b001: CmpResE = {63'b0, LT & ~BothZeroE & ~EitherNaNE}; // Less than - 3'b011: CmpResE = {63'b0, (LT|EQ|BothZeroE) & ~EitherNaNE}; // Less than or equal - default: CmpResE = 64'b0; - endcase - end + if (`FPSIZES == 1) + if(`IEEE754) assign NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]}; + else assign NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + + else if (`FPSIZES == 2) + if(`IEEE754) assign NaNRes = FmtE ? {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, XSgnE, {`NE1{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF1]}; + else assign NaNRes = FmtE ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + + else if (`FPSIZES == 3) + always_comb + case (FmtE) + `FMT: + if(`IEEE754) NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]}; + else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + `FMT1: + if(`IEEE754) NaNRes = {{`FLEN-`LEN1{1'b1}}, XSgnE, {`NE1{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF1]}; + else NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + `FMT2: + if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, XSgnE, {`NE2{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF2]}; + else NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + default: NaNRes = (`FLEN)'(0); + endcase + + else if (`FPSIZES == 4) + always_comb + case (FmtE) + 2'h3: + if(`IEEE754) NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]}; + else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + 2'h1: + if(`IEEE754) NaNRes = {{`FLEN-`D_LEN{1'b1}}, XSgnE, {`D_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`D_NF]}; + else NaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + 2'h0: + if(`IEEE754) NaNRes = {{`FLEN-`S_LEN{1'b1}}, XSgnE, {`S_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`S_NF]}; + else NaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + 2'h2: + if(`IEEE754) NaNRes = {{`FLEN-`H_LEN{1'b1}}, XSgnE, {`H_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`H_NF]}; + else NaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; + endcase + + // when one input is a NaN -output the non-NaN + always_comb + case (FOpCtrlE[2:0]) + 3'b111: CmpResE = XNaNE ? YNaNE ? NaNRes : FSrcYE // Min + : YNaNE ? FSrcXE : LT ? FSrcXE : FSrcYE; + 3'b101: CmpResE = XNaNE ? YNaNE ? NaNRes : FSrcYE // Max + : YNaNE ? FSrcXE : LT ? FSrcYE : FSrcXE; + 3'b010: CmpResE = {(`FLEN-1)'(0), (EQ|BothZeroE) & ~EitherNaNE}; // Equal + 3'b001: CmpResE = {(`FLEN-1)'(0), LT & ~BothZeroE & ~EitherNaNE}; // Less than + 3'b011: CmpResE = {(`FLEN-1)'(0), (LT|EQ|BothZeroE) & ~EitherNaNE}; // Less than or equal + default: CmpResE = (`FLEN)'(0); + endcase + endmodule diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 71d990371..431e6d6e0 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -486,7 +486,7 @@ module fma2( /////////////////////////////////////////////////////////////////////////////// normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, - .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm); + .ZOrigDenormM, .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm); @@ -580,6 +580,7 @@ module normalize( input logic [$clog2(3*`NF+7)-1:0] NormCntM, // normalization shift count input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single input logic KillProdM, // is the product set to zero + input logic ZOrigDenormM, input logic AddendStickyM, // the sticky bit caclulated from the aligned addend output logic [`NF+2:0] NormSum, // normalized sum output logic SumZero, // is the sum zero @@ -603,7 +604,7 @@ module normalize( assign SumZero = ~(|SumM); // calculate the sum's exponent - assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); + assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZOrigDenormM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); //convert the sum's exponent into the propper percision if (`FPSIZES == 1) begin @@ -1083,6 +1084,7 @@ module fmaflags( // - Don't set the underflow flag if the result is exact assign Underflow = (SumExp[`NE+1] | ((SumExp == 0) & (Round|Guard|Sticky)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); + // exp is negitive result is denorm exp was denorm but rounded to norm and if given an unbounded exponent it would stay denormal assign UnderflowFlag = (FullResultExp[`NE+1] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); // Set Inexact flag if the result is diffrent from what would be outputed given infinite precision // - Don't set the underflow flag if an underflowed result isn't outputed diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index eadaa7f2b..c45f86d2e 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -100,9 +100,9 @@ module unpack ( assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; // is the input (in it's original format) denormalized - assign XOrigDenormE = (FmtE ? 0 : |XLen1[`LEN1-2:`NF1]) & ~XFracZero; - assign YOrigDenormE = (FmtE ? 0 : |YLen1[`LEN1-2:`NF1]) & ~YFracZero; - assign ZOrigDenormE = (FmtE ? 0 : |ZLen1[`LEN1-2:`NF1]) & ~ZFracZero; + assign XOrigDenormE = FmtE ? 0 : ~|XLen1[`LEN1-2:`NF1] & ~XFracZero; + assign YOrigDenormE = FmtE ? 0 : ~|YLen1[`LEN1-2:`NF1] & ~YFracZero; + assign ZOrigDenormE = FmtE ? 0 : ~|ZLen1[`LEN1-2:`NF1] & ~ZFracZero; // extract the fraction, add trailing zeroes to the mantissa if nessisary assign XFracE = FmtE ? X[`NF-1:0] : {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index d79bc6d19..9e8a35167 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -6,126 +6,121 @@ // 1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh // 2) go to riscv-wally/pipelined/testbench/fp/Tests // 3) run ./sim-fma-batch -//*** drop the any constants in each file and figure out a way to do them without the code module testbenchfp; parameter TEST="none"; - string Tests[]; - logic [2:0] OpCtrl[]; - logic [2:0] Unit[]; - string FmaRneTests[]; - string FmaRuTests[]; - string FmaRdTests[]; - string FmaRzTests[]; - string FmaRnmTests[]; - logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rne, rz, ru, rd, rnm - logic [1:0] Fmt[]; - logic [1:0] FmaFmt[]; + string Tests[]; // list of tests to be run + string FmaRneTests[]; // list of FMA round to nearest even tests to run + string FmaRuTests[]; // list of FMA round up tests to run + string FmaRdTests[]; // list of FMA round down tests to run + string FmaRzTests[]; // list of FMA round twords zero + string FmaRnmTests[]; // list of FMA round to nearest max magnitude + logic [2:0] OpCtrl[]; // list of op controls + logic [2:0] Unit[]; // list of units being tested + logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100 + logic [1:0] Fmt[]; // list of formats for the other units + logic [1:0] FmaFmt[]; // list of formats for the FMA - logic clk=0; - logic [31:0] TestNum=0; - logic [31:0] OpCtrlNum=0; - logic [31:0] errors=0; - logic [31:0] VectorNum=0; - logic [31:0] FrmNum=0; - logic [31:0] FmaNum=0; - logic [`FLEN*4+7:0] TestVectors[46464:0]; - logic [`FLEN*4+7:0] FmaRneVectors[6133248:0]; - logic [`FLEN*4+7:0] FmaRuVectors[6133248:0]; - logic [`FLEN*4+7:0] FmaRdVectors[6133248:0]; - logic [`FLEN*4+7:0] FmaRzVectors[6133248:0]; - logic [`FLEN*4+7:0] FmaRnmVectors[6133248:0]; + logic clk=0; + logic [31:0] TestNum=0; // index for the test + logic [31:0] OpCtrlNum=0; // index for OpCtrl + logic [31:0] errors=0; // how many errors + logic [31:0] VectorNum=0; // index for test vector + logic [31:0] FrmNum=0; // index for rounding mode + logic [`FLEN*4+7:0] TestVectors[46464:0]; // list of test vectors + logic [`FLEN*4+7:0] FmaRneVectors[6133248:0]; // list of fma rne test vectors + logic [`FLEN*4+7:0] FmaRuVectors[6133248:0]; // list of fma ru test vectors + logic [`FLEN*4+7:0] FmaRdVectors[6133248:0]; // list of fma rd test vectors + logic [`FLEN*4+7:0] FmaRzVectors[6133248:0]; // list of fma rz test vectors + logic [`FLEN*4+7:0] FmaRnmVectors[6133248:0]; // list of fma rnm test vectors - logic [1:0] FmaFmtVal, FmtVal; - logic [2:0] UnitVal, OpCtrlVal, FrmVal; - logic NaNGood; - logic ZOrigDenorm, FmaRneZOrigDenorm, FmaRzZOrigDenorm, FmaRuZOrigDenorm, FmaRdZOrigDenorm, FmaRnmZOrigDenorm; - logic FmaRneNaNGood, FmaRzNaNGood, FmaRuNaNGood, FmaRdNaNGood, FmaRnmNaNGood; - logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat + logic [1:0] FmaFmtVal, FmtVal; // value of the current Fmt + logic [2:0] UnitVal, OpCtrlVal, FrmVal; // vlaue of the currnet Unit/OpCtrl/FrmVal + logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat logic [`FLEN-1:0] FmaRneX, FmaRneY, FmaRneZ; // inputs read from TestFloat - logic [`FLEN-1:0] FmaRzX, FmaRzY, FmaRzZ; // inputs read from TestFloat - logic [`FLEN-1:0] FmaRuX, FmaRuY, FmaRuZ; // inputs read from TestFloat - logic [`FLEN-1:0] FmaRdX, FmaRdY, FmaRdZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRzX, FmaRzY, FmaRzZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRuX, FmaRuY, FmaRuZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRdX, FmaRdY, FmaRdZ; // inputs read from TestFloat logic [`FLEN-1:0] FmaRnmX, FmaRnmY, FmaRnmZ; // inputs read from TestFloat - logic [`XLEN-1:0] SrcA; // integer input - logic [`FLEN-1:0] Ans; // result from TestFloat - logic [`FLEN-1:0] FmaRneAns, FmaRzAns, FmaRuAns, FmaRdAns, FmaRnmAns; // flags read form testfloat - logic [`FLEN-1:0] Res; - logic [`FLEN-1:0] FmaRneRes, FmaRzRes, FmaRuRes, FmaRdRes, FmaRnmRes; // result from Units - logic [4:0] AnsFlags; // flags read form testfloat - logic [4:0] FmaRneAnsFlags, FmaRzAnsFlags, FmaRuAnsFlags, FmaRdAnsFlags, FmaRnmAnsFlags; // flags read form testfloat - logic [4:0] ResFlags; // Res's flags - logic [4:0] FmaRneResFlags, FmaRzResFlags, FmaRuResFlags, FmaRdResFlags, FmaRnmResFlags; // flags read form testfloat - logic [2:0] FrmE; // rounding mode - logic [`FPSIZES/3:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad - logic [3:0] FpuUnit; // Which unit is being tested - logic [`FLEN-1:0] FMAResM, DivResM, CmpResE, CvtResE, CvtFpResE; // Ress - logic [4:0] FMAFlgM, CvtFpFlgM, DivFlgM, CvtIntFlgM, CmpFlgM; // FMA's outputed flags - logic CmpNVE; - logic ResNaN, FmaRneResNaN, FmaRzResNaN, FmaRuResNaN, FmaRdResNaN, FmaRnmResNaN; // is the outputed result NaN + logic [`XLEN-1:0] SrcA; // integer input + logic [`FLEN-1:0] Ans; // correct answer from TestFloat + logic [`FLEN-1:0] FmaRneAns, FmaRzAns, FmaRuAns, FmaRdAns, FmaRnmAns; // flags read form testfloat + logic [`FLEN-1:0] Res; // result from other units + logic [`FLEN-1:0] FmaRneRes, FmaRzRes, FmaRuRes, FmaRdRes, FmaRnmRes; // results from FMA + logic [4:0] AnsFlg; // correct flags read from testfloat + logic [4:0] FmaRneAnsFlg, FmaRzAnsFlg, FmaRuAnsFlg, FmaRdAnsFlg, FmaRnmAnsFlg; // flags read form testfloat + logic [4:0] ResFlg; // Result flags + logic [4:0] FmaRneResFlg, FmaRzResFlg, FmaRuResFlg, FmaRdResFlg, FmaRnmResFlg; // flags read form testfloat + logic [`FPSIZES/3:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad + logic [`FLEN-1:0] FmaRes, DivRes, CmpRes, CvtRes, CvtFpRes; // Results from each unit + logic [4:0] FmaFlg, CvtFpFlg, DivFlg, CvtIntFlg, CmpFlg; // Outputed flags + logic ResNaN, FmaRneResNaN, FmaRzResNaN, FmaRuResNaN, FmaRdResNaN, FmaRnmResNaN; // is the outputed result NaN logic AnsNaN, FmaRneAnsNaN, FmaRzAnsNaN, FmaRuAnsNaN, FmaRdAnsNaN, FmaRnmAnsNaN; // is the correct answer NaN - logic [`NE+1:0] ProdExpE, FmaRneProdExp, FmaRzProdExp, FmaRuProdExp, FmaRdProdExp, FmaRnmProdExp; - logic AddendStickyE, FmaRneAddendSticky, FmaRzAddendSticky, FmaRuAddendSticky, FmaRdAddendSticky, FmaRnmAddendSticky; - logic KillProdE, FmaRneKillProd, FmaRzKillProd, FmaRuKillProd, FmaRdKillProd, FmaRnmKillProd; - logic XSgn, YSgn, ZSgn; - logic FmaRneXSgn, FmaRneYSgn, FmaRneZSgn; - logic FmaRzXSgn, FmaRzYSgn, FmaRzZSgn; - logic FmaRuXSgn, FmaRuYSgn, FmaRuZSgn; - logic FmaRdXSgn, FmaRdYSgn, FmaRdZSgn; - logic FmaRnmXSgn, FmaRnmYSgn, FmaRnmZSgn; - logic [`NE-1:0] XExp, YExp, ZExp; - logic [`NE-1:0] FmaRneXExp, FmaRneYExp, FmaRneZExp; - logic [`NE-1:0] FmaRzXExp, FmaRzYExp, FmaRzZExp; - logic [`NE-1:0] FmaRuXExp, FmaRuYExp, FmaRuZExp; - logic [`NE-1:0] FmaRdXExp, FmaRdYExp, FmaRdZExp; - logic [`NE-1:0] FmaRnmXExp, FmaRnmYExp, FmaRnmZExp; - logic [`NF:0] XMan, YMan, ZMan; - logic [`NF:0] FmaRneXMan, FmaRneYMan, FmaRneZMan; - logic [`NF:0] FmaRzXMan, FmaRzYMan, FmaRzZMan; - logic [`NF:0] FmaRuXMan, FmaRuYMan, FmaRuZMan; - logic [`NF:0] FmaRdXMan, FmaRdYMan, FmaRdZMan; - logic [`NF:0] FmaRnmXMan, FmaRnmYMan, FmaRnmZMan; - logic XNorm; - logic XExpMaxE; - logic XNaN, YNaN, ZNaN; - logic FmaRneXNaN, FmaRneYNaN, FmaRneZNaN; - logic FmaRzXNaN, FmaRzYNaN, FmaRzZNaN; - logic FmaRuXNaN, FmaRuYNaN, FmaRuZNaN; - logic FmaRdXNaN, FmaRdYNaN, FmaRdZNaN; - logic FmaRnmXNaN, FmaRnmYNaN, FmaRnmZNaN; - logic XSNaN, YSNaN, ZSNaN; - logic FmaRneXSNaN, FmaRneYSNaN, FmaRneZSNaN; - logic FmaRzXSNaN, FmaRzYSNaN, FmaRzZSNaN; - logic FmaRuXSNaN, FmaRuYSNaN, FmaRuZSNaN; - logic FmaRdXSNaN, FmaRdYSNaN, FmaRdZSNaN; - logic FmaRnmXSNaN, FmaRnmYSNaN, FmaRnmZSNaN; - logic XDenorm, YDenorm, ZDenorm; - logic FmaRneXDenorm, FmaRneYDenorm, FmaRneZDenorm; - logic FmaRzXDenorm, FmaRzYDenorm, FmaRzZDenorm; - logic FmaRuXDenorm, FmaRuYDenorm, FmaRuZDenorm; - logic FmaRdXDenorm, FmaRdYDenorm, FmaRdZDenorm; - logic FmaRnmXDenorm, FmaRnmYDenorm, FmaRnmZDenorm; - logic XInf, YInf, ZInf; - logic FmaRneXInf, FmaRneYInf, FmaRneZInf; - logic FmaRzXInf, FmaRzYInf, FmaRzZInf; - logic FmaRuXInf, FmaRuYInf, FmaRuZInf; - logic FmaRdXInf, FmaRdYInf, FmaRdZInf; - logic FmaRnmXInf, FmaRnmYInf, FmaRnmZInf; - logic XZero, YZero, ZZero; - logic FmaRneXZero, FmaRneYZero, FmaRneZZero; - logic FmaRzXZero, FmaRzYZero, FmaRzZZero; - logic FmaRuXZero, FmaRuYZero, FmaRuZZero; - logic FmaRdXZero, FmaRdYZero, FmaRdZZero; - logic FmaRnmXZero, FmaRnmYZero, FmaRnmZZero; - logic XExpMax, YExpMax, ZExpMax, Mult; - logic [3*`NF+5:0] SumE, FmaRneSum, FmaRzSum, FmaRuSum, FmaRdSum, FmaRnmSum; - logic InvZE, FmaRneInvZ, FmaRzInvZ, FmaRuInvZ, FmaRdInvZ, FmaRnmInvZ; - logic NegSumE, FmaRneNegSum, FmaRzNegSum, FmaRuNegSum, FmaRdNegSum, FmaRnmNegSum; - logic ZSgnEffE, FmaRneZSgnEff, FmaRzZSgnEff, FmaRuZSgnEff, FmaRdZSgnEff, FmaRnmZSgnEff; - logic PSgnE, FmaRnePSgn, FmaRzPSgn, FmaRuPSgn, FmaRdPSgn, FmaRnmPSgn; - logic [$clog2(3*`NF+7)-1:0] NormCntE, FmaRneNormCnt, FmaRzNormCnt, FmaRuNormCnt, FmaRdNormCnt, FmaRnmNormCnt; + logic NaNGood, FmaRneNaNGood, FmaRzNaNGood, FmaRuNaNGood, FmaRdNaNGood, FmaRnmNaNGood; // is the NaN answer correct + logic XSgn, YSgn, ZSgn; // sign of the inputs + logic FmaRneXSgn, FmaRneYSgn, FmaRneZSgn; + logic FmaRzXSgn, FmaRzYSgn, FmaRzZSgn; + logic FmaRuXSgn, FmaRuYSgn, FmaRuZSgn; + logic FmaRdXSgn, FmaRdYSgn, FmaRdZSgn; + logic FmaRnmXSgn, FmaRnmYSgn, FmaRnmZSgn; + logic [`NE-1:0] XExp, YExp, ZExp; // exponent of the inputs + logic [`NE-1:0] FmaRneXExp, FmaRneYExp, FmaRneZExp; + logic [`NE-1:0] FmaRzXExp, FmaRzYExp, FmaRzZExp; + logic [`NE-1:0] FmaRuXExp, FmaRuYExp, FmaRuZExp; + logic [`NE-1:0] FmaRdXExp, FmaRdYExp, FmaRdZExp; + logic [`NE-1:0] FmaRnmXExp, FmaRnmYExp, FmaRnmZExp; + logic [`NF:0] XMan, YMan, ZMan; // mantissas of the inputs + logic [`NF:0] FmaRneXMan, FmaRneYMan, FmaRneZMan; + logic [`NF:0] FmaRzXMan, FmaRzYMan, FmaRzZMan; + logic [`NF:0] FmaRuXMan, FmaRuYMan, FmaRuZMan; + logic [`NF:0] FmaRdXMan, FmaRdYMan, FmaRdZMan; + logic [`NF:0] FmaRnmXMan, FmaRnmYMan, FmaRnmZMan; + logic XNorm; // is X normal + logic XNaN, YNaN, ZNaN; // is the input NaN + logic FmaRneXNaN, FmaRneYNaN, FmaRneZNaN; + logic FmaRzXNaN, FmaRzYNaN, FmaRzZNaN; + logic FmaRuXNaN, FmaRuYNaN, FmaRuZNaN; + logic FmaRdXNaN, FmaRdYNaN, FmaRdZNaN; + logic FmaRnmXNaN, FmaRnmYNaN, FmaRnmZNaN; + logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN + logic FmaRneXSNaN, FmaRneYSNaN, FmaRneZSNaN; + logic FmaRzXSNaN, FmaRzYSNaN, FmaRzZSNaN; + logic FmaRuXSNaN, FmaRuYSNaN, FmaRuZSNaN; + logic FmaRdXSNaN, FmaRdYSNaN, FmaRdZSNaN; + logic FmaRnmXSNaN, FmaRnmYSNaN, FmaRnmZSNaN; + logic XDenorm, YDenorm, ZDenorm; // is the input denormalized + logic FmaRneXDenorm, FmaRneYDenorm, FmaRneZDenorm; + logic FmaRzXDenorm, FmaRzYDenorm, FmaRzZDenorm; + logic FmaRuXDenorm, FmaRuYDenorm, FmaRuZDenorm; + logic FmaRdXDenorm, FmaRdYDenorm, FmaRdZDenorm; + logic FmaRnmXDenorm, FmaRnmYDenorm, FmaRnmZDenorm; + logic XInf, YInf, ZInf; // is the input infinity + logic FmaRneXInf, FmaRneYInf, FmaRneZInf; + logic FmaRzXInf, FmaRzYInf, FmaRzZInf; + logic FmaRuXInf, FmaRuYInf, FmaRuZInf; + logic FmaRdXInf, FmaRdYInf, FmaRdZInf; + logic FmaRnmXInf, FmaRnmYInf, FmaRnmZInf; + logic XZero, YZero, ZZero; // is the input zero + logic FmaRneXZero, FmaRneYZero, FmaRneZZero; + logic FmaRzXZero, FmaRzYZero, FmaRzZZero; + logic FmaRuXZero, FmaRuYZero, FmaRuZZero; + logic FmaRdXZero, FmaRdYZero, FmaRdZZero; + logic FmaRnmXZero, FmaRnmYZero, FmaRnmZZero; + logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones + logic ZOrigDenorm, FmaRneZOrigDenorm, FmaRzZOrigDenorm, FmaRuZOrigDenorm, FmaRdZOrigDenorm, FmaRnmZOrigDenorm; // is the original precision dnormalized + // in-between FMA signals + logic Mult; + logic [`NE+1:0] ProdExpE, FmaRneProdExp, FmaRzProdExp, FmaRuProdExp, FmaRdProdExp, FmaRnmProdExp; + logic AddendStickyE, FmaRneAddendSticky, FmaRzAddendSticky, FmaRuAddendSticky, FmaRdAddendSticky, FmaRnmAddendSticky; + logic KillProdE, FmaRneKillProd, FmaRzKillProd, FmaRuKillProd, FmaRdKillProd, FmaRnmKillProd; + logic [$clog2(3*`NF+7)-1:0] NormCntE, FmaRneNormCnt, FmaRzNormCnt, FmaRuNormCnt, FmaRdNormCnt, FmaRnmNormCnt; + logic [3*`NF+5:0] SumE, FmaRneSum, FmaRzSum, FmaRuSum, FmaRdSum, FmaRnmSum; + logic InvZE, FmaRneInvZ, FmaRzInvZ, FmaRuInvZ, FmaRdInvZ, FmaRnmInvZ; + logic NegSumE, FmaRneNegSum, FmaRzNegSum, FmaRuNegSum, FmaRdNegSum, FmaRnmNegSum; + logic ZSgnEffE, FmaRneZSgnEff, FmaRzZSgnEff, FmaRuZSgnEff, FmaRdZSgnEff, FmaRnmZSgnEff; + logic PSgnE, FmaRnePSgn, FmaRzPSgn, FmaRuPSgn, FmaRdPSgn, FmaRnmPSgn; /////////////////////////////////////////////////////////////////////////////////////////////// @@ -478,13 +473,13 @@ module testbenchfp; // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel FmaRneTests = {FmaRneTests, "f32_mulAdd_rne.tv"}; - FmaRzTests = {FmaRzTests, "f32_mulAdd_rz.tv"}; - FmaRuTests = {FmaRuTests, "f32_mulAdd_ru.tv"}; - FmaRdTests = {FmaRdTests, "f32_mulAdd_rd.tv"}; - FmaRnmTests = {FmaRnmTests, "f32_mulAdd_rnm.tv"}; - for(int i = 0; i<5; i++) begin + // FmaRzTests = {FmaRzTests, "f32_mulAdd_rz.tv"}; + // FmaRuTests = {FmaRuTests, "f32_mulAdd_ru.tv"}; + // FmaRdTests = {FmaRdTests, "f32_mulAdd_rd.tv"}; + // FmaRnmTests = {FmaRnmTests, "f32_mulAdd_rnm.tv"}; + // for(int i = 0; i<5; i++) begin FmaFmt = {FmaFmt, 2'b00}; - end + // end end end if (`ZFH_SUPPORTED) begin // if half precision supported @@ -566,13 +561,13 @@ module testbenchfp; // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel FmaRneTests = {FmaRneTests, "f16_mulAdd_rne.tv"}; - FmaRzTests = {FmaRzTests, "f16_mulAdd_rz.tv"}; - FmaRuTests = {FmaRuTests, "f16_mulAdd_ru.tv"}; - FmaRdTests = {FmaRdTests, "f16_mulAdd_rd.tv"}; - FmaRnmTests = {FmaRnmTests, "f16_mulAdd_rnm.tv"}; - for(int i = 0; i<5; i++) begin + // FmaRzTests = {FmaRzTests, "f16_mulAdd_rz.tv"}; + // FmaRuTests = {FmaRuTests, "f16_mulAdd_ru.tv"}; + // FmaRdTests = {FmaRdTests, "f16_mulAdd_rd.tv"}; + // FmaRnmTests = {FmaRnmTests, "f16_mulAdd_rnm.tv"}; + // for(int i = 0; i<5; i++) begin FmaFmt = {FmaFmt, 2'b10}; - end + // end end end @@ -607,7 +602,7 @@ module testbenchfp; end // set a the signals for all tests - always_comb FmaFmtVal = FmaFmt[FmaNum]; + always_comb FmaFmtVal = FmaFmt[TestNum]; always_comb UnitVal = Unit[TestNum]; always_comb FmtVal = Fmt[TestNum]; always_comb OpCtrlVal = OpCtrl[OpCtrlNum]; @@ -624,9 +619,9 @@ module testbenchfp; else FmaModFmt = FmaFmtVal === `FMT; end - // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlags) from the current test vector - readfmavectors readfmarnevectors (.clk, .Frm(`RNE), .TestVector(FmaRneVectors[VectorNum]), .VectorNum, .Ans(FmaRneAns), .AnsFlags(FmaRneAnsFlags), - .XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn), .FmaNum, + // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector + readfmavectors readfmarnevectors (.clk, .TestVector(FmaRneVectors[VectorNum]), .Ans(FmaRneAns), .AnsFlg(FmaRneAnsFlg), + .XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn), .XExpE(FmaRneXExp), .YExpE(FmaRneYExp), .ZExpE(FmaRneZExp), .XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan), .XNaNE(FmaRneXNaN), .YNaNE(FmaRneYNaN), .ZNaNE(FmaRneZNaN), .ZOrigDenormE(FmaRneZOrigDenorm), @@ -635,8 +630,8 @@ module testbenchfp; .XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero), .XInfE(FmaRneXInf), .YInfE(FmaRneYInf), .ZInfE(FmaRneZInf), .FmaModFmt, .FmaFmt(FmaFmtVal), .X(FmaRneX), .Y(FmaRneY), .Z(FmaRneZ)); - readfmavectors readfmarzvectors (.clk, .Frm(`RZ), .TestVector(FmaRzVectors[VectorNum]), .VectorNum, .Ans(FmaRzAns), .AnsFlags(FmaRzAnsFlags), - .XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), .FmaNum, .FmaModFmt, + readfmavectors readfmarzvectors (.clk, .TestVector(FmaRzVectors[VectorNum]), .Ans(FmaRzAns), .AnsFlg(FmaRzAnsFlg), + .XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), .FmaModFmt, .XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp), .XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan), .XNaNE(FmaRzXNaN), .YNaNE(FmaRzYNaN), .ZNaNE(FmaRzZNaN), .ZOrigDenormE(FmaRzZOrigDenorm), @@ -645,8 +640,8 @@ module testbenchfp; .XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero), .XInfE(FmaRzXInf), .YInfE(FmaRzYInf), .ZInfE(FmaRzZInf), .FmaFmt(FmaFmtVal), .X(FmaRzX), .Y(FmaRzY), .Z(FmaRzZ)); - readfmavectors readfmaruvectors (.clk, .Frm(`RU), .TestVector(FmaRuVectors[VectorNum]), .VectorNum, .Ans(FmaRuAns), .AnsFlags(FmaRuAnsFlags), - .XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), .FmaNum, .FmaModFmt, + readfmavectors readfmaruvectors (.clk, .TestVector(FmaRuVectors[VectorNum]), .Ans(FmaRuAns), .AnsFlg(FmaRuAnsFlg), + .XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), .FmaModFmt, .XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp), .XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan), .XNaNE(FmaRuXNaN), .YNaNE(FmaRuYNaN), .ZNaNE(FmaRuZNaN), .ZOrigDenormE(FmaRuZOrigDenorm), @@ -655,8 +650,8 @@ module testbenchfp; .XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero), .XInfE(FmaRuXInf), .YInfE(FmaRuYInf), .ZInfE(FmaRuZInf), .FmaFmt(FmaFmtVal), .X(FmaRuX), .Y(FmaRuY), .Z(FmaRuZ)); - readfmavectors readfmardvectors (.clk, .Frm(`RD), .TestVector(FmaRdVectors[VectorNum]), .VectorNum, .Ans(FmaRdAns), .AnsFlags(FmaRdAnsFlags), - .XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), .FmaNum, .FmaModFmt, + readfmavectors readfmardvectors (.clk, .TestVector(FmaRdVectors[VectorNum]), .Ans(FmaRdAns), .AnsFlg(FmaRdAnsFlg), + .XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), .FmaModFmt, .XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp), .XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan), .XNaNE(FmaRdXNaN), .YNaNE(FmaRdYNaN), .ZNaNE(FmaRdZNaN), .ZOrigDenormE(FmaRdZOrigDenorm), @@ -665,8 +660,8 @@ module testbenchfp; .XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero), .XInfE(FmaRdXInf), .YInfE(FmaRdYInf), .ZInfE(FmaRdZInf), .FmaFmt(FmaFmtVal), .X(FmaRdX), .Y(FmaRdY), .Z(FmaRdZ)); - readfmavectors readfmarnmvectors (.clk, .Frm(`RNM), .TestVector(FmaRnmVectors[VectorNum]), .VectorNum, .Ans(FmaRnmAns), .AnsFlags(FmaRnmAnsFlags), - .XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), .FmaNum, .FmaModFmt, + readfmavectors readfmarnmvectors (.clk, .TestVector(FmaRnmVectors[VectorNum]), .Ans(FmaRnmAns), .AnsFlg(FmaRnmAnsFlg), + .XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), .FmaModFmt, .XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp), .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), .ZOrigDenormE(FmaRnmZOrigDenorm), .XNaNE(FmaRnmXNaN), .YNaNE(FmaRnmYNaN), .ZNaNE(FmaRnmZNaN), @@ -675,7 +670,7 @@ module testbenchfp; .XZeroE(FmaRnmXZero), .YZeroE(FmaRnmYZero), .ZZeroE(FmaRnmZZero), .XInfE(FmaRnmXInf), .YInfE(FmaRnmYInf), .ZInfE(FmaRnmZInf), .FmaFmt(FmaFmtVal), .X(FmaRnmX), .Y(FmaRnmY), .Z(FmaRnmZ)); - readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlags(AnsFlags), .SrcA, + readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, .XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), .Unit (UnitVal), .XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), .TestNum, .OpCtrl(OpCtrlVal), .XManE(XMan), .YManE(YMan), .ZManE(ZMan), .ZOrigDenormE(ZOrigDenorm), @@ -719,7 +714,7 @@ module testbenchfp; .KillProdM(FmaRneSumKillProd), .AddendStickyM(FmaRneAddendSticky), .ProdExpM(FmaRneProdExp), .SumM((FmaRneSum)), .NegSumM(FmaRneNegSum), .InvZM(FmaRneInvZ), .NormCntM(FmaRneNormCnt), .ZSgnEffM(FmaRneZSgnEff), .PSgnM(FmaRnePSgn), .FmtM(FmaModFmt), .FrmM(`RNE), - .FMAFlgM(FmaRneResFlags), .FMAResM(FmaRneRes), .Mult(1'b0)); + .FMAFlgM(FmaRneResFlg), .FMAResM(FmaRneRes), .Mult(1'b0)); fma1 fma1rz(.XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), .XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp), .XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan), @@ -738,7 +733,7 @@ module testbenchfp; .KillProdM(FmaRzSumKillProd), .AddendStickyM(FmaRzAddendSticky), .ProdExpM(FmaRzProdExp), .SumM((FmaRzSum)), .NegSumM(FmaRzNegSum), .InvZM(FmaRzInvZ), .NormCntM(FmaRzNormCnt), .ZSgnEffM(FmaRzZSgnEff), .PSgnM(FmaRzPSgn), .FmtM(FmaModFmt), .FrmM(`RZ), - .FMAFlgM(FmaRzResFlags), .FMAResM(FmaRzRes), .Mult(1'b0)); + .FMAFlgM(FmaRzResFlg), .FMAResM(FmaRzRes), .Mult(1'b0)); fma1 fma1ru(.XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), .XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp), .XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan), @@ -757,7 +752,7 @@ module testbenchfp; .KillProdM(FmaRuSumKillProd), .AddendStickyM(FmaRuAddendSticky), .ProdExpM(FmaRuProdExp), .SumM((FmaRuSum)), .NegSumM(FmaRuNegSum), .InvZM(FmaRuInvZ), .NormCntM(FmaRuNormCnt), .ZSgnEffM(FmaRuZSgnEff), .PSgnM(FmaRuPSgn), .FmtM(FmaModFmt), .FrmM(`RU), - .FMAFlgM(FmaRuResFlags), .FMAResM(FmaRuRes), .Mult(1'b0)); + .FMAFlgM(FmaRuResFlg), .FMAResM(FmaRuRes), .Mult(1'b0)); fma1 fma1rd(.XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), .XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp), .XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan), @@ -776,7 +771,7 @@ module testbenchfp; .KillProdM(FmaRdSumKillProd), .AddendStickyM(FmaRdAddendSticky), .ProdExpM(FmaRdProdExp), .SumM((FmaRdSum)), .NegSumM(FmaRdNegSum), .InvZM(FmaRdInvZ), .NormCntM(FmaRdNormCnt), .ZSgnEffM(FmaRdZSgnEff), .PSgnM(FmaRdPSgn), .FmtM(FmaModFmt), .FrmM(`RD), - .FMAFlgM(FmaRdResFlags), .FMAResM(FmaRdRes), .Mult(1'b0)); + .FMAFlgM(FmaRdResFlg), .FMAResM(FmaRdRes), .Mult(1'b0)); fma1 fma1rnm(.XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), .XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp), .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), @@ -786,7 +781,7 @@ module testbenchfp; .NormCntE(FmaRnmNormCnt), .ZSgnEffE(FmaRnmZSgnEff), .PSgnE(FmaRnmPSgn), .ProdExpE(FmaRnmProdExp), .AddendStickyE(FmaRnmAddendSticky), .KillProdE(FmaRnmSumKillProd)); fma2 fma2rnm(.XSgnM(FmaRnmXSgn), .YSgnM(FmaRnmYSgn), - .ZExpM(FmaRnmZExp), .ZOrigDenormM(FmaRmeZOrigDenorm), + .ZExpM(FmaRnmZExp), .ZOrigDenormM(FmaRnmZOrigDenorm), .XManM(FmaRnmXMan), .YManM(FmaRnmYMan), .ZManM(FmaRnmZMan), .XNaNM(FmaRnmXNaN), .YNaNM(FmaRnmYNaN), .ZNaNM(FmaRnmZNaN), .XZeroM(FmaRnmXZero), .YZeroM(FmaRnmYZero), .ZZeroM(FmaRnmZZero), @@ -795,7 +790,7 @@ module testbenchfp; .KillProdM(FmaRnmSumKillProd), .AddendStickyM(FmaRnmAddendSticky), .ProdExpM(FmaRnmProdExp), .SumM((FmaRnmSum)), .NegSumM(FmaRnmNegSum), .InvZM(FmaRnmInvZ), .NormCntM(FmaRnmNormCnt), .ZSgnEffM(FmaRnmZSgnEff), .PSgnM(FmaRnmPSgn), .FmtM(FmaModFmt), .FrmM(`RNM), - .FMAFlgM(FmaRnmResFlags), .FMAResM(FmaRnmRes), .Mult(1'b0)); + .FMAFlgM(FmaRnmResFlg), .FMAResM(FmaRnmRes), .Mult(1'b0)); fma1 fma1(.XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), .XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), .XManE(XMan), .YManE(YMan), .ZManE(ZMan), @@ -812,20 +807,22 @@ module testbenchfp; .XSNaNM(XSNaN), .YSNaNM(YSNaN), .ZSNaNM(ZSNaN), .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(ModFmt), .FrmM(FrmVal), - .FMAFlgM, .FMAResM, .Mult); + .FMAFlgM(FmaFlg), .FMAResM(FmaRes), .Mult); // fcvtfp fcvtfp (.XExpE(XExp), .XManE(XMan), .XSgnE(XSgn), .XZeroE(XZero), .XDenormE(XDenorm), .XInfE(XInf), - // .XNaNE(XNaN), .XSNaNE(XSNaN), .FrmE(Frmal), .FmtE(ModFmt), .CvtFpResE, .CvtFpFlgE); - // fcmp fcmp (.FmtE(ModFmt), .FOpCtrlE, .XSgnE(XSgn), .YSgnE(YSgn), .XExpE(XExp), .YExpE(YExp), - // .XManE(XMan), .YManE(YMan), .XZeroE(XZero), .YZeroE(YZero), - // .XNaNE(XNaN), .YNaNE(YNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .FSrcXE(X), .FSrcYE(Y), .CmpNVE, .CmpResE); + // .XNaNE(XNaN), .XSNaNE(XSNaN), .FrmE(Frmal), .FmtE(ModFmt), .CvtFpRes, .CvtFpFlgE); + fcmp fcmp (.FmtE(ModFmt), .FOpCtrlE(OpCtrlVal), .XSgnE(XSgn), .YSgnE(YSgn), .XExpE(XExp), .YExpE(YExp), + .XManE(XMan), .YManE(YMan), .XZeroE(XZero), .YZeroE(YZero), + .XNaNE(XNaN), .YNaNE(YNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .FSrcXE(X), .FSrcYE(Y), .CmpNVE(CmpFlg[4]), .CmpResE(CmpRes)); // fcvtint fcvtint (.XSgnE(XSgn), .XExpE(XExp), .XManE(XMan), .XZeroE(XZero), .XNaNE(XNaN), .XInfE(XInf), // .XDenormE(XDenorm), .ForwardedSrcAE(SrcA), .FOpCtrlE, .FmtE(ModFmt), .FrmE(Frmal), - // .CvtResE, .CvtFlgE); + // .CvtRes, .CvtFlgE); // *** integrade divide and squareroot // fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmVal[1:0]), .op_type(FOpCtrlQ), // .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1), // .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload, - // .FDivBusyE, .done(FDivSqrtDoneE), .AS_Res(FDivResM), .Flags(FDivFlgM)); + // .FDivBusyE, .done(FDivSqrtDoneE), .AS_Res(FDivRes), .Flg(FDivFlg)); + + assign CmpFlg[3:0] = 0; // produce clock always begin @@ -843,7 +840,7 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// - //Check if answer is a NaN + //Check if the correct answer and result is a NaN always_comb begin case (FmaFmtVal) 4'b11: begin // quad @@ -896,8 +893,11 @@ module testbenchfp; end endcase end - always_comb begin //***need for other units??? + + + always_comb begin if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin + // an integer output can't be a NaN AnsNaN = 1'b0; ResNaN = 1'b0; end @@ -905,19 +905,19 @@ module testbenchfp; case (FmtVal) 4'b11: begin // quad AnsNaN = &Ans[`FLEN-2:`NF]&(|Ans[`NF-1:0]); - ResNaN = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]); + ResNaN = &FmaRes[`FLEN-2:`NF]&(|FmaRes[`NF-1:0]); end 4'b01: begin // double AnsNaN = &Ans[`LEN1-2:`NF1]&(|Ans[`NF1-1:0]); - ResNaN = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]); + ResNaN = &FmaRes[`LEN1-2:`NF1]&(|FmaRes[`NF1-1:0]); end 4'b00: begin // single AnsNaN = &Ans[`LEN2-2:`NF2]&(|Ans[`NF2-1:0]); - ResNaN = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]); + ResNaN = &FmaRes[`LEN2-2:`NF2]&(|FmaRes[`NF2-1:0]); end 4'b10: begin // half AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); - ResNaN = &FMAResM[`H_LEN-2:`H_NF]&(|FMAResM[`H_NF-1:0]); + ResNaN = &FmaRes[`H_LEN-2:`H_NF]&(|FmaRes[`H_NF-1:0]); end endcase end @@ -925,150 +925,154 @@ module testbenchfp; // check results on falling edge of clk always @(negedge clk) begin + + // select the result to check case (UnitVal) - `FMAUNIT: Res = FMAResM; - `DIVUNIT: Res = DivResM; - `CMPUNIT: Res = CmpResE; - `CVTINTUNIT: Res = CvtResE; - `CVTFPUNIT: Res = CvtFpResE; + `FMAUNIT: Res = FmaRes; + `DIVUNIT: Res = DivRes; + `CMPUNIT: Res = CmpRes; + `CVTINTUNIT: Res = CvtRes; + `CVTFPUNIT: Res = CvtFpRes; endcase + + // select the flag to check case (UnitVal) - `FMAUNIT: ResFlags = FMAFlgM; - `DIVUNIT: ResFlags = DivFlgM; - `CMPUNIT: ResFlags = CmpFlgM; - `CVTINTUNIT: ResFlags = CvtIntFlgM; - `CVTFPUNIT: ResFlags = CvtFpFlgM; + `FMAUNIT: ResFlg = FmaFlg; + `DIVUNIT: ResFlg = DivFlg; + `CMPUNIT: ResFlg = CmpFlg; + `CVTINTUNIT: ResFlg = CvtIntFlg; + `CVTFPUNIT: ResFlg = CvtFpFlg; endcase // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: // - the sign of the NaN does not matter for the opperations being tested // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter case (FmaFmtVal) - 4'b11: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneX[`Q_LEN-2:`Q_NF],1'b1,FmaRneX[`Q_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneY[`Q_LEN-2:`Q_NF],1'b1,FmaRneY[`Q_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneZ[`Q_LEN-2:`Q_NF],1'b1,FmaRneZ[`Q_NF-2:0]}))); - 4'b01: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneX[`D_LEN-2:`D_NF],1'b1,FmaRneX[`D_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneY[`D_LEN-2:`D_NF],1'b1,FmaRneY[`D_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneZ[`D_LEN-2:`D_NF],1'b1,FmaRneZ[`D_NF-2:0]}))); - 4'b00: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneX[`S_LEN-2:`S_NF],1'b1,FmaRneX[`S_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneY[`S_LEN-2:`S_NF],1'b1,FmaRneY[`S_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneZ[`S_LEN-2:`S_NF],1'b1,FmaRneZ[`S_NF-2:0]}))); - 4'b10: FmaRneNaNGood =((FmaRneAnsFlags[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneX[`H_LEN-2:`H_NF],1'b1,FmaRneX[`H_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneY[`H_LEN-2:`H_NF],1'b1,FmaRneY[`H_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneZ[`H_LEN-2:`H_NF],1'b1,FmaRneZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRzNaNGood = ((FmaRzAnsFlags[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzX[`Q_LEN-2:`Q_NF],1'b1,FmaRzX[`Q_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzY[`Q_LEN-2:`Q_NF],1'b1,FmaRzY[`Q_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzZ[`Q_LEN-2:`Q_NF],1'b1,FmaRzZ[`Q_NF-2:0]}))); - 4'b01: FmaRzNaNGood = ((FmaRzAnsFlags[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzX[`D_LEN-2:`D_NF],1'b1,FmaRzX[`D_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzY[`D_LEN-2:`D_NF],1'b1,FmaRzY[`D_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzZ[`D_LEN-2:`D_NF],1'b1,FmaRzZ[`D_NF-2:0]}))); - 4'b00: FmaRzNaNGood = ((FmaRzAnsFlags[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzX[`S_LEN-2:`S_NF],1'b1,FmaRzX[`S_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzY[`S_LEN-2:`S_NF],1'b1,FmaRzY[`S_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzZ[`S_LEN-2:`S_NF],1'b1,FmaRzZ[`S_NF-2:0]}))); - 4'b10: FmaRzNaNGood = ((FmaRzAnsFlags[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzX[`H_LEN-2:`H_NF],1'b1,FmaRzX[`H_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzY[`H_LEN-2:`H_NF],1'b1,FmaRzY[`H_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzZ[`H_LEN-2:`H_NF],1'b1,FmaRzZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRuNaNGood = ((FmaRuAnsFlags[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuX[`Q_LEN-2:`Q_NF],1'b1,FmaRuX[`Q_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuY[`Q_LEN-2:`Q_NF],1'b1,FmaRuY[`Q_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuZ[`Q_LEN-2:`Q_NF],1'b1,FmaRuZ[`Q_NF-2:0]}))); - 4'b01: FmaRuNaNGood = ((FmaRuAnsFlags[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (FmaRuAnsFlags[4]&(FmaRuRes[`Q_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF{1'b0}}})) | + 4'b01: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuX[`D_LEN-2:`D_NF],1'b1,FmaRuX[`D_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuY[`D_LEN-2:`D_NF],1'b1,FmaRuY[`D_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuZ[`D_LEN-2:`D_NF],1'b1,FmaRuZ[`D_NF-2:0]}))); - 4'b00: FmaRuNaNGood = ((FmaRuAnsFlags[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuX[`S_LEN-2:`S_NF],1'b1,FmaRuX[`S_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuY[`S_LEN-2:`S_NF],1'b1,FmaRuY[`S_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuZ[`S_LEN-2:`S_NF],1'b1,FmaRuZ[`S_NF-2:0]}))); - 4'b10: FmaRuNaNGood = ((FmaRuAnsFlags[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuX[`H_LEN-2:`H_NF],1'b1,FmaRuX[`H_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuY[`H_LEN-2:`H_NF],1'b1,FmaRuY[`H_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuZ[`H_LEN-2:`H_NF],1'b1,FmaRuZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRdNaNGood = ((FmaRdAnsFlags[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdX[`Q_LEN-2:`Q_NF],1'b1,FmaRdX[`Q_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdY[`Q_LEN-2:`Q_NF],1'b1,FmaRdY[`Q_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdZ[`Q_LEN-2:`Q_NF],1'b1,FmaRdZ[`Q_NF-2:0]}))); - 4'b01: FmaRdNaNGood = ((FmaRdAnsFlags[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdX[`D_LEN-2:`D_NF],1'b1,FmaRdX[`D_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdY[`D_LEN-2:`D_NF],1'b1,FmaRdY[`D_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdZ[`D_LEN-2:`D_NF],1'b1,FmaRdZ[`D_NF-2:0]}))); - 4'b00: FmaRdNaNGood = ((FmaRdAnsFlags[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdX[`S_LEN-2:`S_NF],1'b1,FmaRdX[`S_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdY[`S_LEN-2:`S_NF],1'b1,FmaRdY[`S_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdZ[`S_LEN-2:`S_NF],1'b1,FmaRdZ[`S_NF-2:0]}))); - 4'b10: FmaRdNaNGood = ((FmaRdAnsFlags[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdX[`H_LEN-2:`H_NF],1'b1,FmaRdX[`H_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdY[`H_LEN-2:`H_NF],1'b1,FmaRdY[`H_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdZ[`H_LEN-2:`H_NF],1'b1,FmaRdZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRnmNaNGood =((FmaRnmAnsFlags[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmX[`Q_LEN-2:`Q_NF],1'b1,FmaRnmX[`Q_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmY[`Q_LEN-2:`Q_NF],1'b1,FmaRnmY[`Q_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmZ[`Q_LEN-2:`Q_NF],1'b1,FmaRnmZ[`Q_NF-2:0]}))); - 4'b01: FmaRnmNaNGood =((FmaRnmAnsFlags[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmX[`D_LEN-2:`D_NF],1'b1,FmaRnmX[`D_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmY[`D_LEN-2:`D_NF],1'b1,FmaRnmY[`D_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmZ[`D_LEN-2:`D_NF],1'b1,FmaRnmZ[`D_NF-2:0]}))); - 4'b00: FmaRnmNaNGood =((FmaRnmAnsFlags[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmX[`S_LEN-2:`S_NF],1'b1,FmaRnmX[`S_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmY[`S_LEN-2:`S_NF],1'b1,FmaRnmY[`S_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmZ[`S_LEN-2:`S_NF],1'b1,FmaRnmZ[`S_NF-2:0]}))); - 4'b10: FmaRnmNaNGood =((FmaRnmAnsFlags[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmX[`H_LEN-2:`H_NF],1'b1,FmaRnmX[`H_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmY[`H_LEN-2:`H_NF],1'b1,FmaRnmY[`H_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmZ[`H_LEN-2:`H_NF],1'b1,FmaRnmZ[`H_NF-2:0]}))); endcase if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) case (FmtVal) - 4'b11: NaNGood = ((AnsFlags[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); - 4'b01: NaNGood = ((AnsFlags[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); - 4'b00: NaNGood = ((AnsFlags[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); - 4'b10: NaNGood = ((AnsFlags[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]}))); endcase else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format case (OpCtrlVal[1:0]) - 2'b11: NaNGood = ((AnsFlags[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 2'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); - 2'b01: NaNGood = ((AnsFlags[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 2'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); - 2'b00: NaNGood = ((AnsFlags[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 2'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); - 2'b10: NaNGood = ((AnsFlags[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 2'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); endcase - else NaNGood = 1'b0; + else NaNGood = 1'b0; // integers can't be NaNs /////////////////////////////////////////////////////////////////////////////////////////////// @@ -1081,55 +1085,68 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// - if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlags === AnsFlags | AnsFlags === 5'bx))) begin + // check if the non-fma test is correct + if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(UnitVal !== `CMPUNIT)) begin errors += 1; $display("There is an error in %s", Tests[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlags, Ans, AnsFlags); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; end - if(~((FmaRneRes === FmaRneAns | FmaRneNaNGood | FmaRneNaNGood === 1'bx) & (FmaRneResFlags === FmaRneAnsFlags | FmaRneAnsFlags === 5'bx))) begin + // in The RISC-V Instruction Set Manual (2019) section 11.8 specifies that + // if a any of the inputs to the EQ LT LE opperations then the opperation should return a 0 + else if ((UnitVal === `CMPUNIT)&(XNaN|YNaN)&(Res !== (`FLEN)'(0))) begin + errors += 1; + $display("There is an error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end + + // check if the fma tests are correct + if(~((FmaRneRes === FmaRneAns | FmaRneNaNGood | FmaRneNaNGood === 1'bx) & (FmaRneResFlg === FmaRneAnsFlg | FmaRneAnsFlg === 5'bx))) begin errors += 1; $display("There is an error in FMA - RNE"); - $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRneX, FmaRneY, FmaRneZ, FmaRneRes, FmaRneResFlags, FmaRneAns, FmaRneAnsFlags); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRneX, FmaRneY, FmaRneZ, FmaRneRes, FmaRneResFlg, FmaRneAns, FmaRneAnsFlg); $stop; end - if(~((FmaRzRes === FmaRzAns | FmaRzNaNGood | FmaRzNaNGood === 1'bx) & (FmaRzResFlags === FmaRzAnsFlags | FmaRzAnsFlags === 5'bx))) begin + if(~((FmaRzRes === FmaRzAns | FmaRzNaNGood | FmaRzNaNGood === 1'bx) & (FmaRzResFlg === FmaRzAnsFlg | FmaRzAnsFlg === 5'bx))) begin errors += 1; $display("There is an error in FMA - RZ"); - $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRzX, FmaRzY, FmaRzZ, FmaRzRes, FmaRzResFlags, FmaRzAns, FmaRzAnsFlags); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRzX, FmaRzY, FmaRzZ, FmaRzRes, FmaRzResFlg, FmaRzAns, FmaRzAnsFlg); $stop; end - if(~((FmaRuRes === FmaRuAns | FmaRuNaNGood | FmaRuNaNGood === 1'bx) & (FmaRuResFlags === FmaRuAnsFlags | FmaRuAnsFlags === 5'bx))) begin + if(~((FmaRuRes === FmaRuAns | FmaRuNaNGood | FmaRuNaNGood === 1'bx) & (FmaRuResFlg === FmaRuAnsFlg | FmaRuAnsFlg === 5'bx))) begin errors += 1; $display("There is an error in FMA - RU"); - $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRuX, FmaRuY, FmaRuZ, FmaRuRes, FmaRuResFlags, FmaRuAns, FmaRuAnsFlags); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRuX, FmaRuY, FmaRuZ, FmaRuRes, FmaRuResFlg, FmaRuAns, FmaRuAnsFlg); $stop; end - if(~((FmaRdRes === FmaRdAns | FmaRdNaNGood | FmaRdNaNGood === 1'bx) & (FmaRdResFlags === FmaRdAnsFlags | FmaRdAnsFlags === 5'bx))) begin + if(~((FmaRdRes === FmaRdAns | FmaRdNaNGood | FmaRdNaNGood === 1'bx) & (FmaRdResFlg === FmaRdAnsFlg | FmaRdAnsFlg === 5'bx))) begin errors += 1; $display("There is an error in FMA - RD"); - $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRdX, FmaRdY, FmaRdZ, FmaRdRes, FmaRdResFlags, FmaRdAns, FmaRdAnsFlags); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRdX, FmaRdY, FmaRdZ, FmaRdRes, FmaRdResFlg, FmaRdAns, FmaRdAnsFlg); $stop; end - if(~((FmaRnmRes === FmaRnmAns | FmaRnmNaNGood | FmaRnmNaNGood === 1'bx) & (FmaRnmResFlags === FmaRnmAnsFlags | FmaRnmAnsFlags === 5'bx))) begin + if(~((FmaRnmRes === FmaRnmAns | FmaRnmNaNGood | FmaRnmNaNGood === 1'bx) & (FmaRnmResFlg === FmaRnmAnsFlg | FmaRnmAnsFlg === 5'bx))) begin errors += 1; $display("There is an error in FMA - RNM"); - $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRnmX, FmaRnmY, FmaRnmZ, FmaRnmRes, FmaRnmResFlags, FmaRnmAns, FmaRnmAnsFlags); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRnmX, FmaRnmY, FmaRnmZ, FmaRnmRes, FmaRnmResFlg, FmaRnmAns, FmaRnmAnsFlg); $stop; end - VectorNum += 1; // increment test + + VectorNum += 1; // increment the vector + + // check to see if there more vectors in this test + // *** fix this so that fma and other run sepratly - re-add fma num if (TestVectors[VectorNum][0] === 1'bx & FmaRneVectors[VectorNum][0] === 1'bx & FmaRzVectors[VectorNum][0] === 1'bx & FmaRuVectors[VectorNum][0] === 1'bx & FmaRdVectors[VectorNum][0] === 1'bx & FmaRnmVectors[VectorNum][0] === 1'bx) begin // if reached the end of file - if (errors) begin // if there were errors - $display("%s completed with %d Tests and %d errors", Tests[VectorNum], VectorNum, errors); - $stop; - end + // increment the test TestNum += 1; + // read next files $readmemh({`PATH, Tests[TestNum]}, TestVectors); $readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors); @@ -1137,11 +1154,15 @@ module testbenchfp; $readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors); $readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors); $readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors); - FmaNum += 1; + + // set the vector index back to 0 VectorNum = 0; + // incemet the operation if all the rounding modes have been tested if(FrmNum === 4) OpCtrlNum += 1; + // increment the rounding mode or loop back to rne if(FrmNum < 4) FrmNum += 1; else FrmNum = 0; + // if no more Tests - finish if(Tests[TestNum] === "" & FmaRneTests[TestNum] === "" & @@ -1171,33 +1192,30 @@ endmodule module readfmavectors ( - input logic clk, - input logic [2:0] Frm, - input logic [`FPSIZES/3:0] FmaModFmt, - input logic [1:0] FmaFmt, - input logic [`FLEN*4+7:0] TestVector, - input logic [31:0] VectorNum, - input logic [31:0] FmaNum, - output logic [`FLEN-1:0] Ans, - output logic ZOrigDenormE, - output logic [4:0] AnsFlags, - output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ - output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) - output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) - output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN - output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN - output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized - output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero - output logic XInfE, YInfE, ZInfE, // is XYZ infinity - output logic [`FLEN-1:0] X, Y, Z + input logic clk, + input logic [`FPSIZES/3:0] FmaModFmt, // the modified format + input logic [1:0] FmaFmt, // the format of the FMA inputs + input logic [`FLEN*4+7:0] TestVector, // the test vector + output logic [`FLEN-1:0] Ans, // the correct answer + output logic ZOrigDenormE, // is z denormalized in it's original precision + output logic [4:0] AnsFlg, // the correct flag + output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ + output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) + output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN + output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN + output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero + output logic XInfE, YInfE, ZInfE, // is XYZ infinity + output logic [`FLEN-1:0] X, Y, Z // inputs ); logic XNormE, XExpMaxE; // signals the unpacker outputs but isn't used in FMA // apply test vectors on rising edge of clk - // Format of vectors Inputs(1/2/3)_AnsFlags + // Format of vectors Inputs(1/2/3)_AnsFlg always @(posedge clk) begin #1; - AnsFlags = TestVector[4:0]; + AnsFlg = TestVector[4:0]; case (FmaFmt) 2'b11: begin // quad X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)]; @@ -1259,7 +1277,7 @@ module readvectors ( input logic [2:0] OpCtrl, output logic [`FLEN-1:0] Ans, output logic [`XLEN-1:0] SrcA, - output logic [4:0] AnsFlags, + output logic [4:0] AnsFlg, output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) @@ -1274,10 +1292,10 @@ module readvectors ( ); // apply test vectors on rising edge of clk - // Format of vectors Inputs(1/2/3)_AnsFlags + // Format of vectors Inputs(1/2/3)_AnsFlg always @(posedge clk) begin #1; - AnsFlags = TestVector[4:0]; + AnsFlg = TestVector[4:0]; case (Unit) `FMAUNIT: case (Fmt) @@ -1336,26 +1354,26 @@ module readvectors ( end endcase `CMPUNIT: - case (Fmt) + case (Fmt) 2'b11: begin // quad - X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; - Y = TestVector[8+(`Q_LEN)-1:9]; + X = TestVector[12+2*(`Q_LEN)-1:12+(`Q_LEN)]; + Y = TestVector[12+(`Q_LEN)-1:12]; Ans = TestVector[8]; end 2'b01: begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN)-1:9]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8]}; + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+2*(`D_LEN)-1:12+(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+(`D_LEN)-1:12]}; + Ans = TestVector[8]; end 2'b00: begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN)-1:9]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8]}; + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+2*(`S_LEN)-1:12+(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+(`S_LEN)-1:12]}; + Ans = TestVector[8]; end 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN)-1:9]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8]}; + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+3*(`H_LEN)-1:12+(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]}; + Ans = TestVector[8]; end endcase `CVTFPUNIT: From a5d5bd272b84aef3fcc20d0668102680b5b1e933 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 20 May 2022 18:42:38 -0700 Subject: [PATCH 37/38] changes suggested by ben, hopefully fixing buildroot (which is now not running) --- linux/testvector-generation/debug.sh | 24 +++++++++---------- pipelined/testbench/testbench-linux.sv | 32 +++++++++++++------------- pipelined/testbench/testbench.sv | 10 ++++---- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/linux/testvector-generation/debug.sh b/linux/testvector-generation/debug.sh index 748f6e023..7ca3e9b15 100755 --- a/linux/testvector-generation/debug.sh +++ b/linux/testvector-generation/debug.sh @@ -4,18 +4,18 @@ tvDir=$RISCV/linux-testvectors tcpPort=1239 # QEMU Simulation -(qemu-system-riscv64 \ +qemu-system-riscv64 \ -M virt -dtb $imageDir/wally-virt.dtb \ -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ --singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on \ -> ./qemu-serial \ --gdb tcp::$tcpPort -S) \ -& riscv64-unknown-elf-gdb -quiet \ --ex "set pagination off" \ --ex "set logging overwrite on" \ --ex "set logging redirect on" \ --ex "set confirm off" \ --ex "target extended-remote :$tcpPort" \ --ex "maintenance packet Qqemu.PhyMemMode:1" \ --ex "file $imageDir/vmlinux" +-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on +# > ./qemu-serial \ +# -gdb tcp::$tcpPort -S) \ +# & riscv64-unknown-elf-gdb -quiet \ +# -ex "set pagination off" \ +# -ex "set logging overwrite on" \ +# -ex "set logging redirect on" \ +# -ex "set confirm off" \ +# -ex "target extended-remote :$tcpPort" \ +# -ex "maintenance packet Qqemu.PhyMemMode:1" \ +# -ex "file $imageDir/vmlinux" diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 6718eadc3..31add80a2 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -36,7 +36,7 @@ module testbench; parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim parameter CHECKPOINT = 0; parameter RISCV_DIR = "/opt/riscv"; - parameter NO_IE_MTIME_CHECKPOINT = 0; + parameter NO_SPOOFING = 0; parameter DEBUG_TRACE = 0; // Debug Levels // 0: don't check against QEMU @@ -93,7 +93,7 @@ module testbench; logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ string ExpectedCSRArray``STAGE[10:0]; \ - logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; + logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? `DECLARE_TRACE_SCANNER_SIGNALS(E) `DECLARE_TRACE_SCANNER_SIGNALS(M) // M-stage expected values @@ -216,7 +216,7 @@ module testbench; /////////////////////////////// Cache Issue /////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// logic probe; - if (NO_IE_MTIME_CHECKPOINT) + if (NO_SPOOFING) assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c & testbench.dut.core.InstrM != 32'h14021273 & testbench.dut.core.InstrValidM; @@ -356,7 +356,7 @@ module testbench; `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin `INIT_CHECKPOINT_VAL(MIE, [11:0]); `INIT_CHECKPOINT_VAL(MIP, [11:0]); end @@ -393,7 +393,7 @@ module testbench; // ========== INITIALIZATION ========== initial begin - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin force `MEIP = 0; force `SEIP = 0; force `UART_IP = 0; @@ -403,7 +403,7 @@ module testbench; $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR); if (CHECKPOINT!=0) $sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT); - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); + $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); // *** initialize these using zeroes rather than reading from files, see testbench.sv $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"}; ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"}; @@ -460,7 +460,7 @@ module testbench; release `INSTRET; end // Get the E-stage trace reader ahead of the M-stage trace reader - matchCountE = $fgets(lineE,traceFileE); + matchCountE = $fgets(lineE,traceFileE); // *** look at removing? end /////////////////////////////////////////////////////////////////////////////// @@ -545,16 +545,16 @@ module testbench; if(`"STAGE`"=="M") begin \ // override on special conditions \ if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \ - if(!NO_IE_MTIME_CHECKPOINT) begin \ - $display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \ + if(!NO_SPOOFING) begin \ + $display("%tns, %d instrs: Overwrite UART's Register in memory stage.", $time, AttemptedInstructionCount); \ force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ end \ end else \ - if(!NO_IE_MTIME_CHECKPOINT) \ + if(!NO_SPOOFING) \ release dut.core.ieu.dp.ReadDataM; \ if(textM.substr(0,5) == "rdtime") begin \ //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \ - if(!NO_IE_MTIME_CHECKPOINT) \ + if(!NO_SPOOFING) \ force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ end \ end \ @@ -631,7 +631,7 @@ module testbench; if(~dut.core.StallW) begin if(textW.substr(0,5) == "rdtime") begin //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); - if(!NO_IE_MTIME_CHECKPOINT) + if(!NO_SPOOFING) release dut.uncore.clint.clint.MTIME; end //if (ExpectedIEUAdrM == 'h10000005) begin @@ -700,7 +700,7 @@ module testbench; "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) "mip": begin `checkCSR(`CSR_BASE.csrm.MIP_REGW) - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) force `MEIP = 0; if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) @@ -716,7 +716,7 @@ module testbench; if (fault == 1) begin errorCount +=1; $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); - $stop; + $stop; $stop; end end // if (DEBUG_TRACE >= 1) end // if (checkInstrW) @@ -732,7 +732,7 @@ module testbench; always @(negedge clk) begin if(checkInterruptM) begin if((interruptInstrCount+1) == AttemptedInstructionCount) begin - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin case (interruptCauseVal) 11: begin force `MEIP = 1; @@ -763,7 +763,7 @@ module testbench; end end end - + diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 5aa1750dc..4ebd37785 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -328,18 +328,18 @@ logic [3:0] dummy; // initialize the branch predictor if (`BPRED_ENABLED == 1) - initial begin - integer adrindex; + begin + genvar adrindex; // Initializing all zeroes into the branch predictor memory. for(adrindex = 0; adrindex < 1024; adrindex++) begin + initial begin force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; - end - #1; - for(adrindex = 0; adrindex < 1024; adrindex++) begin + #1; release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end end end endmodule From fcaf032a0d75c5ab431c98b42b4b463525bc58ee Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Sat, 21 May 2022 09:53:26 +0000 Subject: [PATCH 38/38] ppa updates added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots --- pipelined/src/ppa/ppa.sv | 333 +++++++++++- synthDC/ppaAnalyze.py | 142 ++++-- synthDC/ppaData.csv | 1050 +++++++++++++++++++++++++++++--------- synthDC/ppaSynth.py | 67 ++- 4 files changed, 1258 insertions(+), 334 deletions(-) diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 32fc45e29..931684e91 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -214,7 +214,39 @@ module ppa_alu #(parameter WIDTH=32) ( else assign Result = FullResult; endmodule -module ppa_shiftleft #(parameter WIDTH=32) ( +module ppa_shiftleft_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_32 #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_128 #(parameter WIDTH=128) ( input logic [WIDTH-1:0] a, input logic [$clog2(WIDTH)-1:0] amt, output logic [WIDTH-1:0] y); @@ -329,30 +361,132 @@ module ppa_prioritythermometer #(parameter N = 8) ( end endmodule -module ppa_priorityonehot #(parameter N = 8) ( - input logic [N-1:0] a, - output logic [N-1:0] y); - logic [N-1:0] nolower; +module ppa_priorityonehot #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; // create thermometer code mask - ppa_prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower)); + ppa_prioritythermometer #(WIDTH) maskgen(.a({a[WIDTH-2:0], 1'b0}), .y(nolower)); assign y = a & nolower; endmodule -module ppa_priorityencoder #(parameter N = 8) ( - input logic [N-1:0] a, - output logic [$clog2(N)-1:0] y); - // Carefully crafted so design compiler will synthesize into a fast tree structure - // Rather than linear. +module ppa_priorityonehot_8 #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityonehot_16 #(parameter WIDTH = 16) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; + + // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityonehot_32 #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; + + // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityonehot_64 #(parameter WIDTH = 64) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; + + // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityonehot_128 #(parameter WIDTH = 128) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; + + // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityencoder_8 #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder_16 #(parameter WIDTH = 16) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder_32 #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder_64 #(parameter WIDTH = 64) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder_128 #(parameter WIDTH = 128) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + int i; always_comb - for (i=0; i 0.25) & (norm<1.75): - f += [freqs[i]] - d += [delays[i]] - a += [areas[i]] + try: + med = statistics.median(freqs) + for i in range(len(freqs)): + norm = freqs[i]/med + if (norm > 0.25) & (norm<1.75): + f += [freqs[i]] + d += [delays[i]] + a += [areas[i]] + except: pass + return f, d, a def freqPlot(mod, width): - freqs = [] - delays = [] - areas = [] + allSynths = getData(mod=mod, width=width) + + freqsV, delaysV, areasV, freqsA, delaysA, areasA = ([] for i in range(6)) for oneSynth in allSynths: if (mod == oneSynth[0]) & (width == oneSynth[1]): - freqs += [oneSynth[2]] - delays += [oneSynth[3]] - areas += [oneSynth[4]] + if (1000/oneSynth[3] < oneSynth[2]): + freqsV += [oneSynth[2]] + delaysV += [oneSynth[3]] + areasV += [oneSynth[4]] + else: + freqsA += [oneSynth[2]] + delaysA += [oneSynth[3]] + areasA += [oneSynth[4]] - freqs, delays, areas = noOutliers(freqs, delays, areas) + freqsV, delaysV, areasV = noOutliers(freqsV, delaysV, areasV) + freqsA, delaysA, areasA = noOutliers(freqsA, delaysA, areasA) - adprod = np.multiply(areas, delays) - adsq = np.multiply(adprod, delays) + adprodA = np.multiply(areasA, delaysA) + adsqA = np.multiply(adprodA, delaysA) + adprodV = np.multiply(areasV, delaysV) + adsqV = np.multiply(adprodV, delaysV) + + legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), + lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True) - ax1.scatter(freqs, delays) - ax2.scatter(freqs, areas) - ax3.scatter(freqs, adprod) - ax4.scatter(freqs, adsq) - ax4.set_xlabel("Freq (MHz)") + ax1.scatter(freqsA, delaysA, color='green') + ax1.scatter(freqsV, delaysV, color='blue') + ax2.scatter(freqsA, areasA, color='green') + ax2.scatter(freqsV, areasV, color='blue') + ax3.scatter(freqsA, adprodA, color='green') + ax3.scatter(freqsV, adprodV, color='blue') + ax4.scatter(freqsA, adsqA, color='green') + ax4.scatter(freqsV, adsqV, color='blue') + ax1.legend(handles=legend_elements) + ax4.set_xlabel("Target Freq (MHz)") ax1.set_ylabel('Delay (ns)') ax2.set_ylabel('Area (sq microns)') ax3.set_ylabel('Area * Delay') @@ -250,12 +279,19 @@ def freqPlot(mod, width): ax1.set_title(mod + '_' + str(width)) plt.show() -allSynths = getData() -writeCSV(allSynths) +def plotPPA(mod, freq=None): + fig, axs = plt.subplots(2, 2) + oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='clg', freq=freq) + oneMetricPlot(mod, 'area', ax=axs[0,1], fits='s', freq=freq) + oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='c', freq=freq) + oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits='s', freq=freq) + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " min delay" + plt.suptitle(mod + titleStr) + plt.show() + +# writeCSV() # makeCoefTable() -# freqPlot('add', 64) +freqPlot('decoder', 8) -makePlots('shifter', 5000) - -# plotPPA('mult', 5000, 'delay', fits='cls') \ No newline at end of file +plotPPA('decoder') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 56489568a..c7b4d9496 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,249 +1,803 @@ Module,Width,Target Freq,Delay,Area,L Power (nW),D energy (mJ) -add,128,10,7.100851,1867.879976,465.925,0.0005009999999999999 -add,128,1538,0.633294,4623.64009,632.254,0.00027958387516254874 -add,128,2051,0.486762,4951.940095,885.884,0.0003568990736226231 -add,128,2359,0.423881,5520.340104,1.49,0.00045146248410343363 -add,128,2410,0.414767,5600.700103,1.57,0.00045684647302904563 -add,128,2462,0.406101,5721.240105,1.77,0.0004780666125101544 -add,128,2513,0.397913,6085.800112,2.14,0.0005161161957819339 -add,128,2564,0.436395,6456.240111,2.27,0.0005503120124804992 -add,128,2615,0.390136,6662.040117,2.45,0.0006137667304015296 -add,128,2667,0.394304,7494.060127,3.58,0.00072928383952006 -add,128,2718,0.407908,7287.280117,3.35,0.0006938925680647534 -add,128,2769,0.431383,6941.340124,2.86,0.0006218851570964247 -add,128,3077,0.387515,7712.60013,2.93,0.0007572310692232694 -add,128,3590,0.386891,6860.000114,2.62,0.0006579387186629527 -add,128,5000,0.389771,7007.980119,2.77,0.0006618 -add,16,10,2.032906,221.479998,55.29,5.75e-05 -add,16,2609,0.375085,405.720008,52.28,2.9359908010732082e-05 -add,16,3478,0.287131,443.940009,126.253,4.1978148361127085e-05 -add,16,4000,0.249839,551.74001,302.479,5.9749999999999995e-05 -add,16,4087,0.243761,503.720009,183.936,5.113775385368241e-05 -add,16,4174,0.239287,549.780011,304.811,6.013416387158601e-05 -add,16,4261,0.234402,607.60001,368.742,6.688570758038019e-05 -add,16,4348,0.22992,610.540011,364.173,6.577736890524379e-05 -add,16,4435,0.22545,666.400011,419.709,7.891770011273957e-05 -add,16,4522,0.222724,820.260016,626.379,9.022556390977442e-05 -add,16,4609,0.221986,815.360013,735.998,8.960729008461705e-05 -add,16,4696,0.227412,866.320016,645.684,9.731686541737649e-05 -add,16,5000,0.228259,924.140017,641.631,0.0001038 -add,16,5217,0.22222,824.180016,601.276,8.778991757715163e-05 -add,16,6000,0.225754,1120.140018,1.01,0.00012316666666666666 -add,16,6087,0.226225,857.500013,678.287,0.00010284212255626745 -add,32,10,4.160501,456.679995,112.161,0.00011800000000000001 -add,32,2400,0.41509,958.440019,151.083,6.875e-05 -add,32,3200,0.312424,1121.120021,296.836,0.000105625 -add,32,3680,0.271527,1465.100024,591.825,0.00015000000000000001 -add,32,3760,0.278449,1689.520028,834.387,0.00017898936170212767 -add,32,3840,0.291206,1547.420027,784.112,0.00015859375 -add,32,3920,0.273454,2044.280039,1.33,0.00022066326530612246 -add,32,4000,0.280842,1730.680031,849.828,0.00018375 -add,32,4080,0.256294,1991.360031,1.24,0.00021397058823529412 -add,32,4160,0.253175,2031.540036,1.24,0.00021995192307692308 -add,32,4240,0.268332,1829.660028,1.09,0.00019245283018867924 -add,32,4320,0.254861,1716.960028,866.723,0.0001814814814814815 -add,32,4800,0.258491,1955.100033,1.07,0.00022458333333333334 -add,32,5000,0.2505,1933.540033,1.03,0.00020979999999999998 -add,32,5600,0.254525,1871.800028,877.446,0.0001967857142857143 -add,32,6000,0.271774,1746.36003,955.901,0.00018966666666666665 -add,64,10,8.474034,927.079988,230.083,0.000246 -add,64,1818,0.538894,2114.840041,250.049,0.0001375137513751375 -add,64,2424,0.412474,2298.100044,453.413,0.00017574257425742574 -add,64,2788,0.358537,2637.180048,758.693,0.00023565279770444765 -add,64,2848,0.351091,2625.420049,698.362,0.00023525280898876406 -add,64,2909,0.343753,2800.840049,852.781,0.0002536954279821244 -add,64,2970,0.337807,3412.360059,1.37,0.00032895622895622896 -add,64,3030,0.331556,3202.640054,1.28,0.0003099009900990099 -add,64,3091,0.349251,3284.960053,1.35,0.00031802005823358134 -add,64,3152,0.328164,3804.360061,1.89,0.00038229695431472085 -add,64,3212,0.336436,3593.660062,1.72,0.00035523038605230384 -add,64,3273,0.311119,3816.120062,1.96,0.0003923006416131989 -add,64,3636,0.330032,3266.340054,1.22,0.00033938393839383937 -add,64,4000,0.323267,3758.300065,1.75,0.00038074999999999996 -add,64,4242,0.328234,3507.420063,1.57,0.00033757661480433756 -add,64,5000,0.334061,3798.480071,2.18,0.0003834 -add,64,6000,0.328457,3749.480066,1.77,0.000391 -add,8,10,0.940062,103.879999,24.765,2.41e-05 -add,8,5000,0.199689,197.960003,83.576,2.26e-05 -comparator,128,10,0.842074,1997.240039,243.506,8.7e-05 -comparator,128,2308,0.406531,2810.640055,437.781,0.00016637781629116118 -comparator,128,3077,0.324985,2559.760047,659.43,0.00017159571010724734 -comparator,128,3538,0.282712,3158.540057,1.6,0.00026483889202939516 -comparator,128,3615,0.276605,3092.880056,1.5,0.00026445366528354077 -comparator,128,3692,0.270828,3380.020055,2.0,0.00030173347778981584 -comparator,128,3769,0.27069,3741.640049,2.91,0.0003372247280445741 -comparator,128,3846,0.273602,4038.58005,3.61,0.0003967758710348414 -comparator,128,3923,0.256043,4153.240051,3.84,0.00038083099668620956 -comparator,128,4000,0.268954,4027.800041,3.66,0.000414 -comparator,128,4077,0.262622,4638.340054,5.12,0.0004716703458425313 -comparator,128,4154,0.257245,4649.120047,5.1,0.0005149253731343283 -comparator,128,4615,0.265848,4047.400041,3.87,0.0004028169014084507 -comparator,128,5000,0.260142,5215.56005,6.0,0.0007416 -comparator,128,5385,0.267095,4787.300045,5.3,0.0007069637883008356 -comparator,16,10000,0.146177,1065.260009,1.61,0.00012470000000000002 -comparator,16,10,0.576329,252.840005,31.402,1.4400000000000001e-05 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subprocess.check_output(['bash','-c', bashCommand]) + linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] -widths = ['128'] -modules = ['comparator'] -freqs = [str(round(f+f*x/100)) for x in arr] + cpl = re.compile('\d{1}\.\d{6}') + f = re.compile('_\d*_MHz') + wm = re.compile('ppa_\w*_\d*_qor') + + allSynths = [] + + for i in range(len(linesCPL)): + line = linesCPL[i] + mwm = wm.findall(line)[0][4:-4].split('_') + freq = int(f.findall(line)[0][1:-4]) + delay = float(cpl.findall(line)[0]) + mod = mwm[0] + width = int(mwm[1]) + + oneSynth = [mod, width, freq, delay] + allSynths += [oneSynth] + + return allSynths + +allSynths = getData() +arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 10, 14, 20, 40] + +widths = [8] +modules = ['decoder'] tech = 'sky90' - - LoT = [] -for module in modules: - for width in widths: - for freq in freqs: - LoT += [[module, width, tech, freq]] + +## initial sweep to get estimate of min delay +# freqs = ['17200'] +# for module in modules: +# for width in widths: +# for freq in freqs: +# LoT += [[module, width, tech, freq]] + +# thorough sweep based on estimate of min delay +for m in modules: + for w in widths: + delays = [] + for oneSynth in allSynths: + if (oneSynth[0] == m) & (oneSynth[1] == w): + delays += [oneSynth[3]] + try: f = 1000/min(delays) + except: print(m) + for freq in [str(round(f+f*x/100)) for x in arr]: + LoT += [[m, w, tech, freq]] deleteRedundant(LoT) pool = Pool() pool.starmap(runCommand, LoT) -pool.close() - -bashCommand = "wait" -outputCPL = subprocess.check_output(['bash','-c', bashCommand]) \ No newline at end of file +pool.close() \ No newline at end of file