diff --git a/.gitignore b/.gitignore index 0a25e7d3d..1e986c3bd 100644 --- a/.gitignore +++ b/.gitignore @@ -103,3 +103,4 @@ pipelined/config/rv64ic_noMulDiv pipelined/config/rv64ic_noPriv pipelined/config/rv64ic_orig synthDC/Summary.csv +pipelined/srt/exptestgen diff --git a/addins/embench-iot b/addins/embench-iot index 2d2aaa7b8..261a65e0a 160000 --- a/addins/embench-iot +++ b/addins/embench-iot @@ -1 +1 @@ -Subproject commit 2d2aaa7b85c60219c591555b647dfa1785ffe1b3 +Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9 diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index effd553a6..be67c99bd 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/addins/riscv-dv b/addins/riscv-dv index cb4295f9c..a7e27bc04 160000 --- a/addins/riscv-dv +++ b/addins/riscv-dv @@ -1 +1 @@ -Subproject commit cb4295f9ce5da2881d7746015a6105adb8f09071 +Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172 diff --git a/addins/riscv-tests b/addins/riscv-tests index 3e2bf06b0..cf04274f5 160000 --- a/addins/riscv-tests +++ b/addins/riscv-tests @@ -1 +1 @@ -Subproject commit 3e2bf06b071a77ae62c09bf07c5229d1f9397d94 +Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7 diff --git a/linux/testvector-generation/debug.sh b/linux/testvector-generation/debug.sh index 748f6e023..7ca3e9b15 100755 --- a/linux/testvector-generation/debug.sh +++ b/linux/testvector-generation/debug.sh @@ -4,18 +4,18 @@ tvDir=$RISCV/linux-testvectors tcpPort=1239 # QEMU Simulation -(qemu-system-riscv64 \ +qemu-system-riscv64 \ -M virt -dtb $imageDir/wally-virt.dtb \ -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ --singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on \ -> ./qemu-serial \ --gdb tcp::$tcpPort -S) \ -& riscv64-unknown-elf-gdb -quiet \ --ex "set pagination off" \ --ex "set logging overwrite on" \ --ex "set logging redirect on" \ --ex "set confirm off" \ --ex "target extended-remote :$tcpPort" \ --ex "maintenance packet Qqemu.PhyMemMode:1" \ --ex "file $imageDir/vmlinux" +-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on +# > ./qemu-serial \ +# -gdb tcp::$tcpPort -S) \ +# & riscv64-unknown-elf-gdb -quiet \ +# -ex "set pagination off" \ +# -ex "set logging overwrite on" \ +# -ex "set logging redirect on" \ +# -ex "set confirm off" \ +# -ex "target extended-remote :$tcpPort" \ +# -ex "maintenance packet Qqemu.PhyMemMode:1" \ +# -ex "file $imageDir/vmlinux" diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index c6f80d497..36cda4d91 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -38,12 +38,13 @@ `define IEEE754 1 // MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +//16 - quad 3 - double 5 - single +`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 +`define ZFH_SUPPORTED 1 /// Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 35b74c6d2..d7ad9d3c8 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -131,8 +131,8 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" +`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/shared/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/regression/fp.do b/pipelined/regression/fp.do new file mode 100644 index 000000000..208118fc6 --- /dev/null +++ b/pipelined/regression/fp.do @@ -0,0 +1,52 @@ +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +# $num = the added words after the call +vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv -suppress 2583,7063,8607,2697 + +vsim -voptargs=+acc work.testbenchfp -G TEST=$2 + +view wave +#-- display input and output signals as hexidecimal values +#do ./wave-dos/peripheral-waves.do +#add log -recursive /* +#do wave.do deal with when ready + +do wave-fpu.do + +#-- Run the Simulation +#run 3600 +run -all +noview testbench-fp.sv +view wave + diff --git a/pipelined/regression/make-tests.sh b/pipelined/regression/make-tests.sh index c5d3644d6..fe4555ff2 100755 --- a/pipelined/regression/make-tests.sh +++ b/pipelined/regression/make-tests.sh @@ -1,14 +1,16 @@ #!/bin/bash rm -r work* -cd ../../tests/imperas-riscv-tests/ make allclean make -cd ../wally-riscv-arch-test -make allclean -make -make XLEN=32 -exe2memfile.pl work/*/*/*.elf -cd ../linux-testgen/linux-testvectors -./tvLinker.sh -cd ../../../pipelined/regression +# cd ../../tests/imperas-riscv-tests/ +# make allclean +# make +# cd ../wally-riscv-arch-test +# make allclean +# make +# make XLEN=32 +# exe2memfile.pl work/*/*/*.elf +# cd ../linux-testgen/linux-testvectors +# ./tvLinker.sh +# cd ../../../pipelined/regression diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index d98d59368..3daadf769 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -40,7 +40,7 @@ configs = [ TestCase( name="lints", variant="all", - cmd="./lint-wally &> {}", + cmd="./lint-wally | tee {}", grepstr="All lints run with no errors or warnings" ) ] diff --git a/pipelined/regression/sim-fp b/pipelined/regression/sim-fp new file mode 100755 index 000000000..700a103ab --- /dev/null +++ b/pipelined/regression/sim-fp @@ -0,0 +1,11 @@ + +# cvtint - test integer conversion unit (fcvtint) +# cvtfp - test floating-point conversion unit (fcvtfp) +# cmp - test comparison unit's LT, LE, EQ opperations (fcmp) +# add - test addition +# sub - test subtraction +# div - test division +# sqrt - test square ro +# all - test everything + +vsim -do "do fp.do rv64fp cmp" diff --git a/pipelined/regression/sim-fp-batch b/pipelined/regression/sim-fp-batch new file mode 100755 index 000000000..7e2c6a341 --- /dev/null +++ b/pipelined/regression/sim-fp-batch @@ -0,0 +1,10 @@ +# cvtint - test integer conversion unit (fcvtint) +# cvtfp - test floating-point conversion unit (fcvtfp) +# cmp - test comparison unit's LT, LE, EQ opperations (fcmp) +# add - test addition +# sub - test subtraction +# div - test division +# sqrt - test square root +# all - test everything + +vsim -c -do "do fp.do rv64fp fma" \ No newline at end of file diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally index 2f88d9aa2..1cb461ffe 100755 --- a/pipelined/regression/sim-wally +++ b/pipelined/regression/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally-pipelined.do rv32e wally32e" +vsim -do "do wally-pipelined.do rv64gc imperas64f" diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch index 44d986454..91f116976 100755 --- a/pipelined/regression/sim-wally-batch +++ b/pipelined/regression/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-pipelined-batch.do rv32e wally32e" +vsim -c -do "do wally-pipelined-batch.do rv64gc imperas64f" diff --git a/pipelined/regression/slack-notifier/slack-notifier.py b/pipelined/regression/slack-notifier/slack-notifier.py index 934932671..273299d23 100755 --- a/pipelined/regression/slack-notifier/slack-notifier.py +++ b/pipelined/regression/slack-notifier/slack-notifier.py @@ -8,7 +8,7 @@ if not os.path.isfile(sys.path[0]+'/slack-webhook-url.txt'): print('slack-notifier.py can help let you know when your sim is done.') print('To make it work, please supply your Slack bot webhook URL in:') print(sys.path[0]+'/slack-webhook-url.txt') - print('Ask Ben for the Tera Slack Notifier Tutorial for more details.') + print('Tutorial for slack webhook urls: https://bit.ly/BenSlackNotifier') print('==============================================================') else: urlFile = open(sys.path[0]+'/slack-webhook-url.txt','r') diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 6891c7d6c..85d8513ec 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -35,7 +35,7 @@ vlib wkdir/work_${1}_${2} if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084 run -all diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index cf116da6d..0dadea94b 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -34,7 +34,7 @@ vlib work if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 #-- Run the Simulation @@ -48,7 +48,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } elseif {$2 eq "buildroot-no-trace"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=0 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 #-- Run the Simulation diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do new file mode 100644 index 000000000..d2ea6d486 --- /dev/null +++ b/pipelined/regression/wave-fpu.do @@ -0,0 +1,102 @@ + +add wave -noupdate /testbenchfp/clk +add wave -noupdate -radix decimal /testbenchfp/VectorNum +add wave -group Other -noupdate /testbenchfp/FrmNum +add wave -group Other -noupdate /testbenchfp/X +add wave -group Other -noupdate /testbenchfp/Y +add wave -group Other -noupdate /testbenchfp/Z +add wave -group Other -noupdate /testbenchfp/Res +add wave -group Other -noupdate /testbenchfp/Ans + +add wave -group Rne -noupdate /testbenchfp/FmaRneX +add wave -group Rne -noupdate /testbenchfp/FmaRneY +add wave -group Rne -noupdate /testbenchfp/FmaRneZ +add wave -group Rne -noupdate /testbenchfp/FmaRneRes +add wave -group Rne -noupdate /testbenchfp/FmaRneAns +add wave -group Rz -noupdate /testbenchfp/FmaRzX +add wave -group Rz -noupdate /testbenchfp/FmaRzY +add wave -group Rz -noupdate /testbenchfp/FmaRzZ +add wave -group Rz -noupdate /testbenchfp/FmaRzRes +add wave -group Rz -noupdate /testbenchfp/FmaRzAns +add wave -group Ru -noupdate /testbenchfp/FmaRuX +add wave -group Ru -noupdate /testbenchfp/FmaRuY +add wave -group Ru -noupdate /testbenchfp/FmaRuZ +add wave -group Ru -noupdate /testbenchfp/FmaRuRes +add wave -group Ru -noupdate /testbenchfp/FmaRuAns +add wave -group Rd -noupdate /testbenchfp/FmaRdX +add wave -group Rd -noupdate /testbenchfp/FmaRdY +add wave -group Rd -noupdate /testbenchfp/FmaRdZ +add wave -group Rd -noupdate /testbenchfp/FmaRdRes +add wave -group Rd -noupdate /testbenchfp/FmaRdAns +add wave -group Rnm -noupdate /testbenchfp/FmaRnmX +add wave -group Rnm -noupdate /testbenchfp/FmaRnmY +add wave -group Rnm -noupdate /testbenchfp/FmaRnmZ +add wave -group Rnm -noupdate /testbenchfp/FmaRnmRes +add wave -group Rnm -noupdate /testbenchfp/FmaRnmAns +add wave -group AllSignals -noupdate /* +add wave -group AllSignals -noupdate /testbenchfp/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rne/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rne/resultselect/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rz/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rz/resultselect/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1ru/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2ru/resultselect/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rd/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rd/resultselect/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/expadd/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/mult/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/align/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/sign/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/add/* +add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/loa/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/normalize/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/fmaround/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/resultsign/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/fmaflags/* +add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/resultselect/* \ No newline at end of file diff --git a/pipelined/regression/wkdir/.gitignore b/pipelined/regression/wkdir/.gitignore new file mode 100644 index 000000000..5e7d2734c --- /dev/null +++ b/pipelined/regression/wkdir/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index a68370cdb..35b3797bb 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -123,6 +123,19 @@ module ahblite ( assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH + + /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. + 000: Single (SINGLE) + 001: Increment burst of undefined length (INCR) + 010: 4-beat wrapping burst (WRAP4) [wraps if X in 000X0000] + 011: 4-beat incrementing burst (INCR4) + 100: 8-beat wrapping burst (WRAP8) [wraps if X in 00X00000 changes] + 101: 8-beat incrementing burst (INCR8) + 110: 16-beat wrapping burst (WRAP16) [wraps if X in 0X000000] + 111: 16-beat incrementing burst (INCR16) + */ + + assign HPROT = 4'b0011; // not used; see Section 3.7 assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise assign HMASTLOCK = 0; // no locking supported diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 94b75d7e1..6ea8fb62f 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -10,20 +10,21 @@ module fcmp ( - input logic FmtE, // precision 1 = double 0 = single - input logic [2:0] FOpCtrlE, // see above table - input logic XSgnE, YSgnE, // input signs - input logic [`NE-1:0] XExpE, YExpE, // input exponents - input logic [`NF:0] XManE, YManE, // input mantissa - input logic XZeroE, YZeroE, // is zero - input logic XNaNE, YNaNE, // is NaN - input logic XSNaNE, YSNaNE, // is signaling NaN - input logic [`FLEN-1:0] FSrcXE, FSrcYE, // original, non-converted to double, inputs - output logic CmpNVE, // invalid flag - output logic [`FLEN-1:0] CmpResE // compare resilt + input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single + input logic [2:0] FOpCtrlE, // see above table + input logic XSgnE, YSgnE, // input signs + input logic [`NE-1:0] XExpE, YExpE, // input exponents + input logic [`NF:0] XManE, YManE, // input mantissa + input logic XZeroE, YZeroE, // is zero + input logic XNaNE, YNaNE, // is NaN + input logic XSNaNE, YSNaNE, // is signaling NaN + input logic [`FLEN-1:0] FSrcXE, FSrcYE, // original, non-converted to double, inputs + output logic CmpNVE, // invalid flag + output logic [`FLEN-1:0] CmpResE // compare resilt ); logic LTabs, LT, EQ; // is X < or > or = Y + logic [`FLEN-1:0] NaNRes; logic BothZeroE, EitherNaNE, EitherSNaNE; assign LTabs= {1'b0, XExpE, XManE} < {1'b0, YExpE, YManE}; // unsigned comparison, treating FP as integers @@ -65,26 +66,62 @@ module fcmp ( // - inf = inf and -inf = -inf // - return 0 if comparison with NaN (unordered) - logic [`FLEN-1:0] QNaN; // fmin/fmax of two NaNs returns a quiet NaN of the appropriate size // for IEEE, return the payload of X // for RISC-V, return the canonical NaN - if(`IEEE754) assign QNaN = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]}; - else assign QNaN = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0}; - - // when one input is a NaN -output the non-NaN - always_comb begin - case (FOpCtrlE[2:0]) - 3'b111: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Min - : YNaNE ? FSrcXE : LT ? FSrcXE : FSrcYE; - 3'b101: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Max - : YNaNE ? FSrcXE : LT ? FSrcYE : FSrcXE; - 3'b010: CmpResE = {63'b0, (EQ|BothZeroE) & ~EitherNaNE}; // Equal - 3'b001: CmpResE = {63'b0, LT & ~BothZeroE & ~EitherNaNE}; // Less than - 3'b011: CmpResE = {63'b0, (LT|EQ|BothZeroE) & ~EitherNaNE}; // Less than or equal - default: CmpResE = 64'b0; - endcase - end + if (`FPSIZES == 1) + if(`IEEE754) assign NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]}; + else assign NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + + else if (`FPSIZES == 2) + if(`IEEE754) assign NaNRes = FmtE ? {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, XSgnE, {`NE1{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF1]}; + else assign NaNRes = FmtE ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + + else if (`FPSIZES == 3) + always_comb + case (FmtE) + `FMT: + if(`IEEE754) NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]}; + else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + `FMT1: + if(`IEEE754) NaNRes = {{`FLEN-`LEN1{1'b1}}, XSgnE, {`NE1{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF1]}; + else NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + `FMT2: + if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, XSgnE, {`NE2{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF2]}; + else NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + default: NaNRes = (`FLEN)'(0); + endcase + + else if (`FPSIZES == 4) + always_comb + case (FmtE) + 2'h3: + if(`IEEE754) NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]}; + else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + 2'h1: + if(`IEEE754) NaNRes = {{`FLEN-`D_LEN{1'b1}}, XSgnE, {`D_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`D_NF]}; + else NaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + 2'h0: + if(`IEEE754) NaNRes = {{`FLEN-`S_LEN{1'b1}}, XSgnE, {`S_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`S_NF]}; + else NaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + 2'h2: + if(`IEEE754) NaNRes = {{`FLEN-`H_LEN{1'b1}}, XSgnE, {`H_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`H_NF]}; + else NaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; + endcase + + // when one input is a NaN -output the non-NaN + always_comb + case (FOpCtrlE[2:0]) + 3'b111: CmpResE = XNaNE ? YNaNE ? NaNRes : FSrcYE // Min + : YNaNE ? FSrcXE : LT ? FSrcXE : FSrcYE; + 3'b101: CmpResE = XNaNE ? YNaNE ? NaNRes : FSrcYE // Max + : YNaNE ? FSrcXE : LT ? FSrcYE : FSrcXE; + 3'b010: CmpResE = {(`FLEN-1)'(0), (EQ|BothZeroE) & ~EitherNaNE}; // Equal + 3'b001: CmpResE = {(`FLEN-1)'(0), LT & ~BothZeroE & ~EitherNaNE}; // Less than + 3'b011: CmpResE = {(`FLEN-1)'(0), (LT|EQ|BothZeroE) & ~EitherNaNE}; // Less than or equal + default: CmpResE = (`FLEN)'(0); + endcase + endmodule diff --git a/pipelined/src/fpu/fcvtfp.sv b/pipelined/src/fpu/fcvtfp.sv index fb8e1ad9a..f43d15661 100644 --- a/pipelined/src/fpu/fcvtfp.sv +++ b/pipelined/src/fpu/fcvtfp.sv @@ -1,6 +1,6 @@ `include "wally-config.vh" -module cvtfp ( +module fcvtfp ( input logic [10:0] XExpE, // input's exponent input logic [52:0] XManE, // input's mantissa input logic XSgnE, // input's sign diff --git a/pipelined/src/fpu/fcvtint.sv b/pipelined/src/fpu/fcvtint.sv index 6a6686993..97007d660 100644 --- a/pipelined/src/fpu/fcvtint.sv +++ b/pipelined/src/fpu/fcvtint.sv @@ -2,7 +2,7 @@ `include "wally-config.vh" // `include "../../config/rv64icfd/wally-config.vh" // `define XLEN 64 -module fcvt ( +module fcvtint ( input logic XSgnE, // X's sign input logic [10:0] XExpE, // X's exponent input logic [52:0] XManE, // X's fraction diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 69d6fc8ee..431e6d6e0 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -43,6 +43,7 @@ module fma( input logic XSgnM, YSgnM, // input signs - memory stage input logic [`NE-1:0] ZExpM, // input exponents - memory stage input logic [`NF:0] XManM, YManM, ZManM, // input mantissa - memory stage + input logic ZOrigDenormE, // is the original precision denormalized input logic XDenormE, YDenormE, ZDenormE, // is denorm input logic XZeroE, YZeroE, ZZeroE, // is zero - execute stage input logic XNaNM, YNaNM, ZNaNM, // is NaN @@ -72,6 +73,7 @@ module fma( logic PSgnE, PSgnM; logic [$clog2(3*`NF+7)-1:0] NormCntE, NormCntM; logic Mult; + logic ZOrigDenormM; fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, @@ -81,11 +83,11 @@ module fma( // E/M pipeline registers flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM); flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM); - flopenrc #($clog2(3*`NF+7)+7) EMRegFma4(clk, reset, FlushM, ~StallM, - {AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0]}, - {AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult}); + flopenrc #($clog2(3*`NF+7)+8) EMRegFma4(clk, reset, FlushM, ~StallM, + {AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0], ZOrigDenormE}, + {AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult, ZOrigDenormM}); - fma2 fma2(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, + fma2 fma2(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZOrigDenormM, .FrmM, .FmtM, .ProdExpM, .AddendStickyM, .KillProdM, .SumM, .NegSumM, .InvZM, .NormCntM, .ZSgnEffM, .PSgnM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .Mult, .FMAResM, .FMAFlgM); @@ -448,6 +450,7 @@ module fma2( input logic [3*`NF+5:0] SumM, // the positive sum input logic NegSumM, // was the sum negitive input logic InvZM, // do you invert Z + input logic ZOrigDenormM, // is the original precision denormalized input logic ZSgnEffM, // the modified Z sign - depends on instruction input logic PSgnM, // the product's sign input logic Mult, // multiply opperation @@ -483,7 +486,7 @@ module fma2( /////////////////////////////////////////////////////////////////////////////// normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, - .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm); + .ZOrigDenormM, .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm); @@ -530,7 +533,7 @@ module fma2( // Select the result /////////////////////////////////////////////////////////////////////////////// - resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, + resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZOrigDenormM, .FrmM, .FmtM, .AddendStickyM, .KillProdM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd, .ZSgnEffM, .PSgnM, .ResultSgn, .CalcPlus1, .Invalid, .Overflow, .Underflow, .ResultDenorm, .ResultExp, .ResultFrac, .FMAResM); @@ -577,6 +580,7 @@ module normalize( input logic [$clog2(3*`NF+7)-1:0] NormCntM, // normalization shift count input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single input logic KillProdM, // is the product set to zero + input logic ZOrigDenormM, input logic AddendStickyM, // the sticky bit caclulated from the aligned addend output logic [`NF+2:0] NormSum, // normalized sum output logic SumZero, // is the sum zero @@ -600,7 +604,7 @@ module normalize( assign SumZero = ~(|SumM); // calculate the sum's exponent - assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); + assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZOrigDenormM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); //convert the sum's exponent into the propper percision if (`FPSIZES == 1) begin @@ -1080,6 +1084,7 @@ module fmaflags( // - Don't set the underflow flag if the result is exact assign Underflow = (SumExp[`NE+1] | ((SumExp == 0) & (Round|Guard|Sticky)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); + // exp is negitive result is denorm exp was denorm but rounded to norm and if given an unbounded exponent it would stay denormal assign UnderflowFlag = (FullResultExp[`NE+1] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); // Set Inexact flag if the result is diffrent from what would be outputed given infinite precision // - Don't set the underflow flag if an underflowed result isn't outputed @@ -1103,6 +1108,7 @@ module resultselect( input logic KillProdM, // set the product to zero before addition if the product is too small to matter input logic XInfM, YInfM, ZInfM, // inputs are infinity input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN + input logic ZOrigDenormM, // is the original precision denormalized input logic ZSgnEffM, // the modified Z sign - depends on instruction input logic PSgnM, // the product's sign input logic ResultSgn, // the result's sign @@ -1122,7 +1128,7 @@ module resultselect( assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + assign InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end else begin assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end @@ -1138,7 +1144,7 @@ module resultselect( assign XNaNResult = FmtM ? {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; assign YNaNResult = FmtM ? {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; assign ZNaNResult = FmtM ? {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; - assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + assign InvalidResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end else begin assign XNaNResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end @@ -1147,7 +1153,7 @@ module resultselect( {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} : ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; assign InfResult = FmtM ? {InfSgn, {`NE{1'b1}}, (`NF)'(0)} : {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; assign NormResult = FmtM ? {ResultSgn, ResultExp, ResultFrac} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; @@ -1160,7 +1166,7 @@ module resultselect( XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end else begin XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end @@ -1177,13 +1183,13 @@ module resultselect( XNaNResult = {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; YNaNResult = {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; ZNaNResult = {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; - InvalidResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + InvalidResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end else begin XNaNResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; NormResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; @@ -1193,14 +1199,14 @@ module resultselect( XNaNResult = {{`FLEN-`LEN2{1'b1}}, XSgnM, {`NE2{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF2]}; YNaNResult = {{`FLEN-`LEN2{1'b1}}, YSgnM, {`NE2{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF2]}; ZNaNResult = {{`FLEN-`LEN2{1'b1}}, ZSgnEffM, {`NE2{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF2]}; - InvalidResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + InvalidResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; end else begin XNaNResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, (`NF2)'(0)}; - KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`LEN2{1'b1}}, {ResultSgn, (`LEN2-1)'(0)} + {(`LEN2-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`LEN2{1'b1}}, InfSgn, {`NE2{1'b1}}, (`NF2)'(0)}; NormResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, ResultExp[`NE2-1:0], ResultFrac[`NF-1:`NF-`NF2]}; @@ -1231,7 +1237,7 @@ module resultselect( XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end else begin XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; end @@ -1248,13 +1254,13 @@ module resultselect( XNaNResult = {{`FLEN-`D_LEN{1'b1}}, XSgnM, {`D_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`D_NF]}; YNaNResult = {{`FLEN-`D_LEN{1'b1}}, YSgnM, {`D_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`D_NF]}; ZNaNResult = {{`FLEN-`D_LEN{1'b1}}, ZSgnEffM, {`D_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`D_NF]}; - InvalidResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + InvalidResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; end else begin XNaNResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; - KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:0], ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`D_LEN{1'b1}}, {ResultSgn, (`D_LEN-1)'(0)} + {(`D_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`D_LEN{1'b1}}, InfSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; NormResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, ResultExp[`D_NE-1:0], ResultFrac[`NF-1:`NF-`D_NF]}; @@ -1264,14 +1270,14 @@ module resultselect( XNaNResult = {{`FLEN-`S_LEN{1'b1}}, XSgnM, {`S_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`S_NF]}; YNaNResult = {{`FLEN-`S_LEN{1'b1}}, YSgnM, {`S_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`S_NF]}; ZNaNResult = {{`FLEN-`S_LEN{1'b1}}, ZSgnEffM, {`S_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`S_NF]}; - InvalidResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + InvalidResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; end else begin XNaNResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; end OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; - KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`S_NE-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`S_LEN{1'b1}}, {ResultSgn, (`S_LEN-1)'(0)} + {(`S_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`S_LEN{1'b1}}, InfSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; NormResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, ResultExp[`S_NE-1:0], ResultFrac[`NF-1:`NF-`S_NF]}; @@ -1289,7 +1295,7 @@ module resultselect( OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; - KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:0], ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; + KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:1],ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; UnderflowResult = {{`FLEN-`H_LEN{1'b1}}, {ResultSgn, (`H_LEN-1)'(0)} + {(`H_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; InfResult = {{`FLEN-`H_LEN{1'b1}}, InfSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; NormResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, ResultExp[`H_NE-1:0], ResultFrac[`NF-1:`NF-`H_NF]}; diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 9a78a36b2..b4b5a2e98 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -104,6 +104,7 @@ module fpu ( logic XInfQ, YInfQ; // is the input infinity - divide logic XExpMaxE; // is the exponent all ones (max value) logic XNormE; // is normal + logic ZOrigDenormE; logic FmtQ; logic FOpCtrlQ; @@ -176,7 +177,7 @@ module fpu ( // unpack unit // - splits FP inputs into their various parts // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) - unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, + unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, .ZOrigDenormE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); @@ -192,7 +193,7 @@ module fpu ( .XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM, - .FOpCtrlE, + .FOpCtrlE, .ZOrigDenormE, .FmtE, .FmtM, .FrmM, .FMAFlgM, .FMAResM); @@ -213,12 +214,12 @@ module fpu ( .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); // other FP execution units - cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); + fcvtfp fcvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE); fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE); fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE); - fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, + fcvtint fcvtint (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE); // data to be stored in memory - to IEU diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 1c0589e10..c45f86d2e 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -2,7 +2,7 @@ module unpack ( input logic [`FLEN-1:0] X, Y, Z, // inputs from register file - input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 10 - double 11 - quad 10 - half + input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) @@ -12,6 +12,7 @@ module unpack ( output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero output logic XInfE, YInfE, ZInfE, // is XYZ infinity + output logic ZOrigDenormE, // is the original precision denormalized output logic XExpMaxE // does X have the maximum exponent (NaN or Inf) ); @@ -47,10 +48,11 @@ module unpack ( assign XExpMaxE = &XExpE; assign YExpMaxE = &YExpE; assign ZExpMaxE = &ZExpE; + + assign ZOrigDenormE = 1'b0; end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported - //***need better names for these constants // largest format | smaller format //---------------------------------- @@ -70,7 +72,8 @@ module unpack ( // quad and half // double and half - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed + logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; @@ -91,9 +94,15 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // extract the exponent, converting the smaller exponent into the larger precision if nessisary - assign XExpE = FmtE ? X[`FLEN-2:`NF] : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; - assign YExpE = FmtE ? Y[`FLEN-2:`NF] : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; - assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + // - if the original precision had a denormal number convert the exponent value 1 + assign XExpE = FmtE ? X[`FLEN-2:`NF] : XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; + assign YExpE = FmtE ? Y[`FLEN-2:`NF] : YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; + assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + + // is the input (in it's original format) denormalized + assign XOrigDenormE = FmtE ? 0 : ~|XLen1[`LEN1-2:`NF1] & ~XFracZero; + assign YOrigDenormE = FmtE ? 0 : ~|YLen1[`LEN1-2:`NF1] & ~YFracZero; + assign ZOrigDenormE = FmtE ? 0 : ~|ZLen1[`LEN1-2:`NF1] & ~ZFracZero; // extract the fraction, add trailing zeroes to the mantissa if nessisary assign XFracE = FmtE ? X[`NF-1:0] : {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; @@ -130,8 +139,9 @@ module unpack ( // quad and double and half // quad and single and half - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision - logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision + logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision + logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision + logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for larger precision assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; @@ -143,6 +153,75 @@ module unpack ( assign YLen2 = &Y[`FLEN-1:`LEN2] ? Y[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; assign ZLen2 = &Z[`FLEN-1:`LEN2] ? Z[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)}; + // There are 2 case statements + // - one for other singals and one for sgn/exp/frac + // - need two for the dependencies in the expoenent calculation + always_comb begin + case (FmtE) + `FMT: begin // if input is largest precision (`FLEN - ie quad or double) + + // This is the original format so set OrigDenorm to 0 + XOrigDenormE = 1'b0; + YOrigDenormE = 1'b0; + ZOrigDenormE = 1'b0; + + // is the exponent non-zero + XExpNonzero = |X[`FLEN-2:`NF]; + YExpNonzero = |Y[`FLEN-2:`NF]; + ZExpNonzero = |Z[`FLEN-2:`NF]; + + // is the exponent all 1's + XExpMaxE = &X[`FLEN-2:`NF]; + YExpMaxE = &Y[`FLEN-2:`NF]; + ZExpMaxE = &Z[`FLEN-2:`NF]; + end + `FMT1: begin // if input is larger precsion (`LEN1 - double or single) + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen1[`LEN1-2:`NF1] & ~XFracZero; + YOrigDenormE = ~|YLen1[`LEN1-2:`NF1] & ~YFracZero; + ZOrigDenormE = ~|ZLen1[`LEN1-2:`NF1] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen1[`LEN1-2:`NF1]; + YExpNonzero = |YLen1[`LEN1-2:`NF1]; + ZExpNonzero = |ZLen1[`LEN1-2:`NF1]; + + // is the exponent all 1's + XExpMaxE = &XLen1[`LEN1-2:`NF1]; + YExpMaxE = &YLen1[`LEN1-2:`NF1]; + ZExpMaxE = &ZLen1[`LEN1-2:`NF1]; + end + `FMT2: begin // if input is smallest precsion (`LEN2 - single or half) + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen2[`LEN2-2:`NF2] & ~XFracZero; + YOrigDenormE = ~|YLen2[`LEN2-2:`NF2] & ~YFracZero; + ZOrigDenormE = ~|ZLen2[`LEN2-2:`NF2] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen2[`LEN2-2:`NF2]; + YExpNonzero = |YLen2[`LEN2-2:`NF2]; + ZExpNonzero = |ZLen2[`LEN2-2:`NF2]; + + // is the exponent all 1's + XExpMaxE = &XLen2[`LEN2-2:`NF2]; + YExpMaxE = &YLen2[`LEN2-2:`NF2]; + ZExpMaxE = &ZLen2[`LEN2-2:`NF2]; + end + default: begin + XOrigDenormE = 0; + YOrigDenormE = 0; + ZOrigDenormE = 0; + XExpNonzero = 0; + YExpNonzero = 0; + ZExpNonzero = 0; + XExpMaxE = 0; + YExpMaxE = 0; + ZExpMaxE = 0; + end + endcase + end always_comb begin case (FmtE) `FMT: begin // if input is largest precision (`FLEN - ie quad or double) @@ -160,16 +239,6 @@ module unpack ( XFracE = X[`NF-1:0]; YFracE = Y[`NF-1:0]; ZFracE = Z[`NF-1:0]; - - // is the exponent non-zero - XExpNonzero = |X[`FLEN-2:`NF]; - YExpNonzero = |Y[`FLEN-2:`NF]; - ZExpNonzero = |Z[`FLEN-2:`NF]; - - // is the exponent all 1's - XExpMaxE = &X[`FLEN-2:`NF]; - YExpMaxE = &Y[`FLEN-2:`NF]; - ZExpMaxE = &Z[`FLEN-2:`NF]; end `FMT1: begin // if input is larger precsion (`LEN1 - double or single) @@ -187,24 +256,14 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the larger precision's exponent to use the largest precision's bias - XExpE = {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; - YExpE = {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; - ZExpE = {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + XExpE = XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; + YExpE = YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; + ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; YFracE = {YLen1[`NF1-1:0], (`NF-`NF1)'(0)}; ZFracE = {ZLen1[`NF1-1:0], (`NF-`NF1)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen1[`LEN1-2:`NF1]; - YExpNonzero = |YLen1[`LEN1-2:`NF1]; - ZExpNonzero = |ZLen1[`LEN1-2:`NF1]; - - // is the exponent all 1's - XExpMaxE = &XLen1[`LEN1-2:`NF1]; - YExpMaxE = &YLen1[`LEN1-2:`NF1]; - ZExpMaxE = &ZLen1[`LEN1-2:`NF1]; end `FMT2: begin // if input is smallest precsion (`LEN2 - single or half) @@ -222,24 +281,14 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the smallest precision's exponent to use the largest precision's bias - XExpE = {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]}; - YExpE = {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]}; - ZExpE = {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]}; + XExpE = XOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]}; + YExpE = YOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]}; + ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen2[`NF2-1:0], (`NF-`NF2)'(0)}; YFracE = {YLen2[`NF2-1:0], (`NF-`NF2)'(0)}; ZFracE = {ZLen2[`NF2-1:0], (`NF-`NF2)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen2[`LEN2-2:`NF2]; - YExpNonzero = |YLen2[`LEN2-2:`NF2]; - ZExpNonzero = |ZLen2[`LEN2-2:`NF2]; - - // is the exponent all 1's - XExpMaxE = &XLen2[`LEN2-2:`NF2]; - YExpMaxE = &YLen2[`LEN2-2:`NF2]; - ZExpMaxE = &ZLen2[`LEN2-2:`NF2]; end default: begin XSgnE = 0; @@ -251,12 +300,6 @@ module unpack ( XFracE = 0; YFracE = 0; ZFracE = 0; - XExpNonzero = 0; - YExpNonzero = 0; - ZExpNonzero = 0; - XExpMaxE = 0; - YExpMaxE = 0; - ZExpMaxE = 0; end endcase end @@ -272,9 +315,10 @@ module unpack ( // `Q_FMT | `D_FMT | `S_FMT | `H_FMT precision's format value - Q=11 D=01 S=00 H=10 - logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision - logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision - logic [`LEN2-1:0] XLen3, YLen3, ZLen3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision + logic [`D_LEN-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision + logic [`S_LEN-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision + logic [`H_LEN-1:0] XLen3, YLen3, ZLen3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision + logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for double precision assign XLen1 = &X[`Q_LEN-1:`D_LEN] ? X[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; @@ -291,6 +335,83 @@ module unpack ( assign YLen3 = &Y[`Q_LEN-1:`H_LEN] ? Y[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; assign ZLen3 = &Z[`Q_LEN-1:`H_LEN] ? Z[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)}; + + // There are 2 case statements + // - one for other singals and one for sgn/exp/frac + // - need two for the dependencies in the expoenent calculation + always_comb begin + case (FmtE) + 2'b11: begin // if input is quad percision + + // This is the original format so set OrigDenorm to 0 + XOrigDenormE = 1'b0; + YOrigDenormE = 1'b0; + ZOrigDenormE = 1'b0; + + // is the exponent non-zero + XExpNonzero = |X[`Q_LEN-2:`Q_NF]; + YExpNonzero = |Y[`Q_LEN-2:`Q_NF]; + ZExpNonzero = |Z[`Q_LEN-2:`Q_NF]; + + // is the exponent all 1's + XExpMaxE = &X[`Q_LEN-2:`Q_NF]; + YExpMaxE = &Y[`Q_LEN-2:`Q_NF]; + ZExpMaxE = &Z[`Q_LEN-2:`Q_NF]; + end + 2'b01: begin // if input is double percision + + // is the exponent all 1's + XExpMaxE = &XLen1[`D_LEN-2:`D_NF]; + YExpMaxE = &YLen1[`D_LEN-2:`D_NF]; + ZExpMaxE = &ZLen1[`D_LEN-2:`D_NF]; + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen1[`D_LEN-2:`D_NF] & ~XFracZero; + YOrigDenormE = ~|YLen1[`D_LEN-2:`D_NF] & ~YFracZero; + ZOrigDenormE = ~|ZLen1[`D_LEN-2:`D_NF] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen1[`D_LEN-2:`D_NF]; + YExpNonzero = |YLen1[`D_LEN-2:`D_NF]; + ZExpNonzero = |ZLen1[`D_LEN-2:`D_NF]; + end + 2'b00: begin // if input is single percision + + // is the exponent all 1's + XExpMaxE = &XLen2[`S_LEN-2:`S_NF]; + YExpMaxE = &YLen2[`S_LEN-2:`S_NF]; + ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF]; + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen2[`S_LEN-2:`S_NF] & ~XFracZero; + YOrigDenormE = ~|YLen2[`S_LEN-2:`S_NF] & ~YFracZero; + ZOrigDenormE = ~|ZLen2[`S_LEN-2:`S_NF] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen2[`S_LEN-2:`S_NF]; + YExpNonzero = |YLen2[`S_LEN-2:`S_NF]; + ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF]; + end + 2'b10: begin // if input is half percision + + // is the exponent all 1's + XExpMaxE = &XLen3[`H_LEN-2:`H_NF]; + YExpMaxE = &YLen3[`H_LEN-2:`H_NF]; + ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF]; + + // is the input (in it's original format) denormalized + XOrigDenormE = ~|XLen3[`H_LEN-2:`H_NF] & ~XFracZero; + YOrigDenormE = ~|YLen3[`H_LEN-2:`H_NF] & ~YFracZero; + ZOrigDenormE = ~|ZLen3[`H_LEN-2:`H_NF] & ~ZFracZero; + + // is the exponent non-zero + XExpNonzero = |XLen3[`H_LEN-2:`H_NF]; + YExpNonzero = |YLen3[`H_LEN-2:`H_NF]; + ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF]; + end + endcase + end + always_comb begin case (FmtE) 2'b11: begin // if input is quad percision @@ -308,16 +429,6 @@ module unpack ( XFracE = X[`Q_NF-1:0]; YFracE = Y[`Q_NF-1:0]; ZFracE = Z[`Q_NF-1:0]; - - // is the exponent non-zero - XExpNonzero = |X[`Q_LEN-2:`Q_NF]; - YExpNonzero = |Y[`Q_LEN-2:`Q_NF]; - ZExpNonzero = |Z[`Q_LEN-2:`Q_NF]; - - // is the exponent all 1's - XExpMaxE = &X[`Q_LEN-2:`Q_NF]; - YExpMaxE = &Y[`Q_LEN-2:`Q_NF]; - ZExpMaxE = &Z[`Q_LEN-2:`Q_NF]; end 2'b01: begin // if input is double percision // extract sign bit @@ -334,24 +445,15 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the double precsion exponent into quad precsion - XExpE = {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]}; - YExpE = {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]}; - ZExpE = {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; + + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; // extract the fraction and add the nessesary trailing zeros - XFracE = {XLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; - YFracE = {YLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; - ZFracE = {ZLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen1[`D_LEN-2:`D_NE]; - YExpNonzero = |YLen1[`D_LEN-2:`D_NE]; - ZExpNonzero = |ZLen1[`D_LEN-2:`D_NE]; - - // is the exponent all 1's - XExpMaxE = &XLen1[`D_LEN-2:`D_NE]; - YExpMaxE = &YLen1[`D_LEN-2:`D_NE]; - ZExpMaxE = &ZLen1[`D_LEN-2:`D_NE]; + XFracE = {XLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; + YFracE = {YLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; + ZFracE = {ZLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; end 2'b00: begin // if input is single percision // extract sign bit @@ -368,24 +470,14 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the single precsion exponent into quad precsion - XExpE = {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]}; - YExpE = {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]}; - ZExpE = {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]}; + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; YFracE = {YLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; ZFracE = {ZLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen2[`S_LEN-2:`S_NF]; - YExpNonzero = |YLen2[`S_LEN-2:`S_NF]; - ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF]; - - // is the exponent all 1's - XExpMaxE = &XLen2[`S_LEN-2:`S_NF]; - YExpMaxE = &YLen2[`S_LEN-2:`S_NF]; - ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF]; end 2'b10: begin // if input is half percision // extract sign bit @@ -400,26 +492,16 @@ module unpack ( // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b // dexp = 0bdd dbbb bbbb // also need to take into account possible zero/denorm/inf/NaN values - + // convert the half precsion exponent into quad precsion - XExpE = {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]}; - YExpE = {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]}; - ZExpE = {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]}; + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; YFracE = {YLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; ZFracE = {ZLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; - - // is the exponent non-zero - XExpNonzero = |XLen3[`H_LEN-2:`H_NF]; - YExpNonzero = |YLen3[`H_LEN-2:`H_NF]; - ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF]; - - // is the exponent all 1's - XExpMaxE = &XLen3[`H_LEN-2:`H_NF]; - YExpMaxE = &YLen3[`H_LEN-2:`H_NF]; - ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF]; end endcase end diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index de2ac72ab..2e306dc60 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -116,7 +116,7 @@ module bpred // this predictor will have two pieces of data, // 1) A direction (1 = Taken, 0 = Not Taken) - // 2) Any information which is necessary for the predictor to built it's next state. + // 2) Any information which is necessary for the predictor to build its next state. // For a 2 bit table this is the prediction count. assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) | diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 083c76bf4..931684e91 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -3,6 +3,14 @@ // & mmasserfrye@hmc.edu // Measure PPA of various building blocks +module ppa_comparator_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -27,6 +35,14 @@ module ppa_comparator_64 #(parameter WIDTH=64) ( ppa_comparator #(WIDTH) comp (.*); endmodule +module ppa_comparator_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -45,6 +61,13 @@ module ppa_comparator #(parameter WIDTH=16) ( assign flags = {eq, lt}; endmodule +module ppa_add_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + module ppa_add_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] y); @@ -66,6 +89,19 @@ module ppa_add_64 #(parameter WIDTH=64) ( assign y = a + b; endmodule +module ppa_add_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_mult_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_mult_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH*2-1:0] y); //is this right width @@ -84,6 +120,12 @@ module ppa_mult_64 #(parameter WIDTH=64) ( assign y = a * b; endmodule +module ppa_mult_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_alu_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, B, input logic [2:0] ALUControl, @@ -172,7 +214,7 @@ module ppa_alu #(parameter WIDTH=32) ( else assign Result = FullResult; endmodule -module ppa_shiftleft #(parameter WIDTH=32) ( +module ppa_shiftleft_8 #(parameter WIDTH=8) ( input logic [WIDTH-1:0] a, input logic [$clog2(WIDTH)-1:0] amt, output logic [WIDTH-1:0] y); @@ -180,12 +222,89 @@ module ppa_shiftleft #(parameter WIDTH=32) ( assign y = a << amt; endmodule +module ppa_shiftleft_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_32 #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shifter_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + +module ppa_shifter_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter_32 #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, input logic Right, Arith, W64, output logic [WIDTH-1:0] Y); + ppa_shifter #(WIDTH) sh (.*); +endmodule + +module ppa_shifter_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + +module ppa_shifter_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + +module ppa_shifter #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + logic [2*WIDTH-2:0] z, zshift; logic [$clog2(WIDTH)-1:0] amttrunc, offset; @@ -194,28 +313,29 @@ module ppa_shifter_32 #(parameter WIDTH=32) ( // For RV64, 32 and 64-bit shifts are needed, with sign extension. // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (WIDTH==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 + if (WIDTH == 64 | WIDTH ==128) begin:shifter // RV64 or 128 always_comb // funnel mux if (W64) begin // 32-bit shifts if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; + if (Arith) z = {{WIDTH{1'b0}}, {WIDTH/2 -1{A[WIDTH/2 -1]}}, A[WIDTH/2 -1:0]}; + else z = {{WIDTH*3/2-1{1'b0}}, A[WIDTH/2 -1:0]}; + else z = {{WIDTH/2{1'b0}}, A[WIDTH/2 -1:0], {WIDTH-1{1'b0}}}; end else begin if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; + if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + else z = {{WIDTH-1{1'b0}}, A}; + else z = {A, {WIDTH-1{1'b0}}}; end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift - end + assign amttrunc = W64 ? {1'b0, Amt[$clog2(WIDTH)-2:0]} : Amt; // 32 or 64-bit shift + end else begin:shifter // RV32 or less + always_comb // funnel mux + if (Right) + if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + else z = {{WIDTH-1{1'b0}}, A}; + else z = {A, {WIDTH-1{1'b0}}}; + assign amttrunc = Amt; // shift amount + end + // opposite offset for right shfits assign offset = Right ? amttrunc : ~amttrunc; @@ -225,6 +345,7 @@ module ppa_shifter_32 #(parameter WIDTH=32) ( assign Y = zshift[WIDTH-1:0]; endmodule +// just report one hot module ppa_prioritythermometer #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y); @@ -240,30 +361,132 @@ module ppa_prioritythermometer #(parameter N = 8) ( end endmodule -module ppa_priorityonehot #(parameter N = 8) ( - input logic [N-1:0] a, - output logic [N-1:0] y); - logic [N-1:0] nolower; +module ppa_priorityonehot #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; // create thermometer code mask - ppa_prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower)); + ppa_prioritythermometer #(WIDTH) maskgen(.a({a[WIDTH-2:0], 1'b0}), .y(nolower)); assign y = a & nolower; endmodule -module ppa_prioriyencoder #(parameter N = 8) ( - input logic [N-1:0] a, - output logic [$clog2(N)-1:0] y); - // Carefully crafted so design compiler will synthesize into a fast tree structure - // Rather than linear. +module ppa_priorityonehot_8 #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityonehot_16 #(parameter WIDTH = 16) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; + + // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityonehot_32 #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; + + // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityonehot_64 #(parameter WIDTH = 64) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; + + // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityonehot_128 #(parameter WIDTH = 128) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] y); + logic [WIDTH-1:0] nolower; + + // create thermometer code mask + ppa_priorityonehot #(WIDTH) poh (.*); +endmodule + +module ppa_priorityencoder_8 #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder_16 #(parameter WIDTH = 16) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder_32 #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder_64 #(parameter WIDTH = 64) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder_128 #(parameter WIDTH = 128) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + ppa_priorityencoder #(WIDTH) pe (.*); +endmodule + +module ppa_priorityencoder #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] a, + output logic [$clog2(WIDTH)-1:0] y); + int i; always_comb - for (i=0; i 1) // check if accurate to 1 ulp - // giving error "srt_stanford.sv(395): (vopt-7063) Failed to find 'abs' in hierarchical name 'abs'." - if (correctr - r > 1) // check if accurate to 1 ulp + if ((correctr - r) > 1) // check if accurate to 1 ulp begin errors = errors+1; $display("failed\n"); diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 8b3fec51d..0af3821ec 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -40,66 +40,33 @@ module testbench; logic clk; logic req; logic done; - logic [63:0] a; - logic [63:0] b; - logic [63:0] result; - logic [51:0] r; + logic [51:0] a; + logic [51:0] b; + logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits - logic [10:0] e; // output exponent - // input logic for Unpacker - // input logic [63:0] X, Y, Z, - numbers - // input logic FmtE, ---- format, 1 is for double precision, 0 is single - // input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide - // all variables are commented in fpu.sv - - // output logic from Unpacker - logic XSgnE, YSgnE, ZSgnE; - logic [10:0] XExpE, YExpE, ZExpE; // exponent - logic [52:0] XManE, YManE, ZManE; - logic XNormE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; // denormals - logic XZeroE, YZeroE, ZZeroE; - logic [10:0] BiasE; // currrently hardcoded, will probs be removed - logic XInfE, YInfE, ZInfE; - logic XExpMaxE; // says exponent is all ones, can ignore - // Test parameters - parameter MEM_SIZE = 60000; - parameter MEM_WIDTH = 64+64+64; + parameter MEM_SIZE = 40000; + parameter MEM_WIDTH = 52+52+52; - `define memr 63:0 - `define memb 127:64 - `define mema 191:128 + `define memr 51:0 + `define memb 103:52 + `define mema 155:104 // Test logicisters logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a // bit field of an array - logic [63:0] correctr, nextr, diffn, diffp; + logic [51:0] correctr, nextr, diffn, diffp; integer testnum, errors; - // Unpacker - // Note: BiasE will probably get taken out eventually - unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), - .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), - .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), - .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), - .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE), - .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); - // Divider srt #(52) srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), - .SrcXExpE(XExpE), .SrcYExpE(YExpE), - .SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]), + .SrcXFrac(a), .SrcYFrac(b), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .Rem(), .Exp(e), .Flags()); - - assign result = {1'b0, e, r}; + .Quot(r), .Rem(), .Flags()); // Counter counter counter(clk, req, done); @@ -133,18 +100,16 @@ module testbench; if (done) begin req <= #5 1; - diffp = correctr - result; - diffn = result - correctr; + diffp = correctr - r; + diffn = r - correctr; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; - $display("a = %h b = %h result = %h",a,b,correctr); - $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp); - $display("at fail"); + $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); $display("failed\n"); $stop; end - if (a === 64'hxxxxxxxxxxxxxxxx) + if (a === 52'hxxxxxxxxxxxxx) begin $display("%d Tests completed successfully", testnum); $stop; @@ -154,14 +119,12 @@ module testbench; begin req <= #5 0; correctr = nextr; - $display("pre increment"); testnum = testnum+1; - a = Vec[`mema]; - b = Vec[`memb]; Vec = Tests[testnum]; - $display("a = %h b = %h result = %h",a,b,nextr); + $display("a = %h b = %h",a,b); + a = Vec[`mema]; + b = Vec[`memb]; nextr = Vec[`memr]; - $display("after increment"); end end diff --git a/pipelined/srt/testgen.c b/pipelined/srt/testgen.c index 143ef058f..98d52819b 100644 --- a/pipelined/srt/testgen.c +++ b/pipelined/srt/testgen.c @@ -28,7 +28,7 @@ double random_input(void); void main(void) { FILE *fptr; - double x1, x2, a, b, r; + double a, b, r; double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -63,7 +63,6 @@ void main(void) void output(FILE *fptr, double a, double b, double r) { - printhex(fptr, a); fprintf(fptr, "_"); printhex(fptr, b); diff --git a/pipelined/srt/testvectors b/pipelined/srt/testvectors index c6412a9e6..112803fe9 100644 --- a/pipelined/srt/testvectors +++ b/pipelined/srt/testvectors @@ -1,289 +1,789 @@ -4000000000000000_4000000000000000_3ff0000000000000 -4018000000000000_4000000000000000_4008000000000000 -4024000000000000_4000000000000000_4014000000000000 -4032000000000000_4000000000000000_4022000000000000 -4041000000000000_4000000000000000_4031000000000000 -405c000000000000_4000000000000000_404c000000000000 -406e000000000000_4000000000000000_405e000000000000 -407ffff583a53b8e_4000000000000000_406ffff583a53b8e -408199999999999a_4000000000000000_407199999999999a -4093333333333333_4000000000000000_4083333333333333 -40a028f5c28f5c29_4000000000000000_409028f5c28f5c29 -40b004189374bc6a_4000000000000000_40a004189374bc6a -40c00068db8bac71_4000000000000000_40b00068db8bac71 -40dd1745d1745d17_4000000000000000_40cd1745d1745d17 -40e5555555555555_4000000000000000_40d5555555555555 -40f999999999999a_4000000000000000_40e999999999999a -410c71c71c71c71c_4000000000000000_40fc71c71c71c71c -4000000000000000_4018000000000000_3fe5555555555555 -4018000000000000_4018000000000000_3ff0000000000000 -4024000000000000_4018000000000000_400aaaaaaaaaaaab -4032000000000000_4018000000000000_4018000000000000 -4041000000000000_4018000000000000_4026aaaaaaaaaaab -405c000000000000_4018000000000000_4032aaaaaaaaaaab -406e000000000000_4018000000000000_4044000000000000 -407ffff583a53b8e_4018000000000000_4055554e57c37d09 -408199999999999a_4018000000000000_4067777777777778 -4093333333333333_4018000000000000_4079999999999999 -40a028f5c28f5c29_4018000000000000_40858bf258bf258c -40b004189374bc6a_4018000000000000_40955acb6f46508d -40c00068db8bac71_4018000000000000_40a555e124ba3b41 -40dd1745d1745d17_4018000000000000_40b364d9364d9365 -40e5555555555555_4018000000000000_40cc71c71c71c71c -40f999999999999a_4018000000000000_40d1111111111111 -410c71c71c71c71c_4018000000000000_40e2f684bda12f68 -4000000000000000_4024000000000000_3fd999999999999a -4018000000000000_4024000000000000_3fe3333333333333 -4024000000000000_4024000000000000_3ff0000000000000 -4032000000000000_4024000000000000_400ccccccccccccd -4041000000000000_4024000000000000_401b333333333333 -405c000000000000_4024000000000000_4026666666666666 -406e000000000000_4024000000000000_4038000000000000 -407ffff583a53b8e_4024000000000000_40499991361dc93e -408199999999999a_4024000000000000_405c28f5c28f5c2a -4093333333333333_4024000000000000_406eb851eb851eb8 -40a028f5c28f5c29_4024000000000000_4079db22d0e56042 -40b004189374bc6a_4024000000000000_4089a027525460aa -40c00068db8bac71_4024000000000000_40999a415f45e0b5 -40dd1745d1745d17_4024000000000000_40a745d1745d1746 -40e5555555555555_4024000000000000_40b1111111111111 -40f999999999999a_4024000000000000_40c47ae147ae147b -410c71c71c71c71c_4024000000000000_40d6c16c16c16c16 -4000000000000000_4032000000000000_3fcc71c71c71c71c -4018000000000000_4032000000000000_3fd5555555555555 -4024000000000000_4032000000000000_3fe1c71c71c71c72 -4032000000000000_4032000000000000_3ff0000000000000 -4041000000000000_4032000000000000_400e38e38e38e38e -405c000000000000_4032000000000000_4018e38e38e38e39 -406e000000000000_4032000000000000_402aaaaaaaaaaaab -407ffff583a53b8e_4032000000000000_403c71bdca59fc0c -408199999999999a_4032000000000000_404f49f49f49f4a0 -4093333333333333_4032000000000000_4051111111111111 -40a028f5c28f5c29_4032000000000000_406cba9876543210 -40b004189374bc6a_4032000000000000_407c790f3f086b67 -40c00068db8bac71_4032000000000000_408c7281864da457 -40dd1745d1745d17_4032000000000000_4099dbcc48676f31 -40e5555555555555_4032000000000000_40a2f684bda12f68 -40f999999999999a_4032000000000000_40b6c16c16c16c17 -410c71c71c71c71c_4032000000000000_40c948b0fcd6e9e0 -4000000000000000_4041000000000000_3fbe1e1e1e1e1e1e -4018000000000000_4041000000000000_3fc6969696969697 -4024000000000000_4041000000000000_3fd2d2d2d2d2d2d3 -4032000000000000_4041000000000000_3fe0f0f0f0f0f0f1 -4041000000000000_4041000000000000_3ff0000000000000 -405c000000000000_4041000000000000_400a5a5a5a5a5a5a -406e000000000000_4041000000000000_401c3c3c3c3c3c3c -407ffff583a53b8e_4041000000000000_402e1e143faa9268 -408199999999999a_4041000000000000_4030909090909091 -4093333333333333_4041000000000000_4042121212121212 -40a028f5c28f5c29_4041000000000000_405e6b3804d19e6b -40b004189374bc6a_4041000000000000_406e25d3e863448b -40c00068db8bac71_4041000000000000_407e1ee37f25085c -40dd1745d1745d17_4041000000000000_408b6132a7041b61 -40e5555555555555_4041000000000000_4094141414141414 -40f999999999999a_4041000000000000_40a8181818181818 -410c71c71c71c71c_4041000000000000_40bac5701ac5701a -4000000000000000_405c000000000000_3fa2492492492492 -4018000000000000_405c000000000000_3fbb6db6db6db6db -4024000000000000_405c000000000000_3fc6db6db6db6db7 -4032000000000000_405c000000000000_3fd4924924924925 -4041000000000000_405c000000000000_3fe36db6db6db6db -405c000000000000_405c000000000000_3ff0000000000000 -406e000000000000_405c000000000000_4001249249249249 -407ffff583a53b8e_405c000000000000_4012491e945e6b2d -408199999999999a_405c000000000000_40241d41d41d41d5 -4093333333333333_405c000000000000_4035f15f15f15f16 -40a028f5c28f5c29_405c000000000000_404277f44c118de6 -40b004189374bc6a_405c000000000000_40524dd2f1a9fbe7 -40c00068db8bac71_405c000000000000_4062499c689fa081 -40dd1745d1745d17_405c000000000000_40709f959c427e56 -40e5555555555555_405c000000000000_4088618618618618 -40f999999999999a_405c000000000000_409d41d41d41d41e -410c71c71c71c71c_405c000000000000_40a0410410410410 -4000000000000000_406e000000000000_3f91111111111111 -4018000000000000_406e000000000000_3fa999999999999a -4024000000000000_406e000000000000_3fb5555555555555 -4032000000000000_406e000000000000_3fc3333333333333 -4041000000000000_406e000000000000_3fd2222222222222 -405c000000000000_406e000000000000_3fedddddddddddde -406e000000000000_406e000000000000_3ff0000000000000 -407ffff583a53b8e_406e000000000000_4001110b796930d4 -408199999999999a_406e000000000000_4012c5f92c5f92c6 -4093333333333333_406e000000000000_40247ae147ae147b -40a028f5c28f5c29_406e000000000000_40313cc1e098ead6 -40b004189374bc6a_406e000000000000_4041156f8c384071 -40c00068db8bac71_406e000000000000_40511180ea2e95ce -40dd1745d1745d17_406e000000000000_406f07c1f07c1f07 -40e5555555555555_406e000000000000_4076c16c16c16c16 -40f999999999999a_406e000000000000_408b4e81b4e81b4f -410c71c71c71c71c_406e000000000000_409e573ac901e573 -4000000000000000_407ffff583a53b8e_3f8000053e2f1a08 -4018000000000000_407ffff583a53b8e_3f980007dd46a70b -4024000000000000_407ffff583a53b8e_3fa400068dbae089 -4032000000000000_407ffff583a53b8e_3fb20005e5f4fd48 -4041000000000000_407ffff583a53b8e_3fc1000592120ba8 -405c000000000000_407ffff583a53b8e_3fdc00092cd26d8d -406e000000000000_407ffff583a53b8e_3fee0009d49850ce -407ffff583a53b8e_407ffff583a53b8e_3ff0000000000000 -408199999999999a_407ffff583a53b8e_4001999f5e009ca2 -4093333333333333_407ffff583a53b8e_401333397dd21f3c -40a028f5c28f5c29_407ffff583a53b8e_402028fb0e2a73e4 -40b004189374bc6a_407ffff583a53b8e_4030041dd2fb6fd0 -40c00068db8bac71_407ffff583a53b8e_4040006e19dd229c -40dd1745d1745d17_407ffff583a53b8e_405d174f59ca00c8 -40e5555555555555_407ffff583a53b8e_4065555c52e9780a -40f999999999999a_407ffff583a53b8e_407999a1fd1829a6 -410c71c71c71c71c_407ffff583a53b8e_408c71d06e8ca00d -4000000000000000_408199999999999a_3f7d1745d1745d17 -4018000000000000_408199999999999a_3f85d1745d1745d1 -4024000000000000_408199999999999a_3f922e8ba2e8ba2e -4032000000000000_408199999999999a_3fa05d1745d1745d -4041000000000000_408199999999999a_3fbee8ba2e8ba2e8 -405c000000000000_408199999999999a_3fc9745d1745d174 -406e000000000000_408199999999999a_3fdb45d1745d1745 -407ffff583a53b8e_408199999999999a_3fed173c4921d90c -408199999999999a_408199999999999a_3ff0000000000000 -4093333333333333_408199999999999a_4001745d1745d174 -40a028f5c28f5c29_408199999999999a_401d61bed61bed61 -40b004189374bc6a_408199999999999a_402d1eb851eb851d -40c00068db8bac71_408199999999999a_403d180477e6ade4 -40dd1745d1745d17_408199999999999a_404a723f789854a0 -40e5555555555555_408199999999999a_405364d9364d9364 -40f999999999999a_408199999999999a_406745d1745d1746 -410c71c71c71c71c_408199999999999a_4079dbcc48676f30 -4000000000000000_4093333333333333_3f6aaaaaaaaaaaab -4018000000000000_4093333333333333_3f74000000000000 -4024000000000000_4093333333333333_3f80aaaaaaaaaaab -4032000000000000_4093333333333333_3f9e000000000000 -4041000000000000_4093333333333333_3fac555555555556 -405c000000000000_4093333333333333_3fb7555555555556 -406e000000000000_4093333333333333_3fc9000000000000 -407ffff583a53b8e_4093333333333333_3fdaaaa1edb45c4c -408199999999999a_4093333333333333_3fed555555555556 -4093333333333333_4093333333333333_3ff0000000000000 -40a028f5c28f5c29_4093333333333333_400aeeeeeeeeeeef -40b004189374bc6a_4093333333333333_401ab17e4b17e4b1 -40c00068db8bac71_4093333333333333_402aab596de8ca12 -40dd1745d1745d17_4093333333333333_40383e0f83e0f83e -40e5555555555555_4093333333333333_4041c71c71c71c72 -40f999999999999a_4093333333333333_4055555555555556 -410c71c71c71c71c_4093333333333333_4067b425ed097b42 -4000000000000000_40a028f5c28f5c29_3f5faee41e6a7498 -4018000000000000_40a028f5c28f5c29_3f67c32b16cfd772 -4024000000000000_40a028f5c28f5c29_3f73cd4e930288df -4032000000000000_40a028f5c28f5c29_3f81d260511be196 -4041000000000000_40a028f5c28f5c29_3f90d4e930288df1 -405c000000000000_40a028f5c28f5c29_3fabb9079a9d2605 -406e000000000000_40a028f5c28f5c29_3fbdb3f5dc83cd4f -407ffff583a53b8e_40a028f5c28f5c29_3fcfaed9bca398bf -408199999999999a_40a028f5c28f5c29_3fd16cfd7720f354 -4093333333333333_40a028f5c28f5c29_3fe30288df0cac5b -40a028f5c28f5c29_40a028f5c28f5c29_3ff0000000000000 -40b004189374bc6a_40a028f5c28f5c29_400fb70081c635bb -40c00068db8bac71_40a028f5c28f5c29_401fafb3c1f3a182 -40dd1745d1745d17_40a028f5c28f5c29_402ccd899003afd0 -40e5555555555555_40a028f5c28f5c29_40351f42bef1a310 -40f999999999999a_40a028f5c28f5c29_404958b67ebb907a -410c71c71c71c71c_40a028f5c28f5c29_405c29ae53ecd96a -4000000000000000_40b004189374bc6a_3f4ff7d0f16c2e0a -4018000000000000_40b004189374bc6a_3f57f9dcb5112287 -4024000000000000_40b004189374bc6a_3f63fae296e39cc6 -4032000000000000_40b004189374bc6a_3f71fb6587ccd9e5 -4041000000000000_40b004189374bc6a_3f80fba700417875 -405c000000000000_40b004189374bc6a_3f9bf8d6d33ea848 -406e000000000000_40b004189374bc6a_3fadf853e2556b29 -407ffff583a53b8e_40b004189374bc6a_3fbff7c677bfebb5 -408199999999999a_40b004189374bc6a_3fc1951951951953 -4093333333333333_40b004189374bc6a_3fd32e4a2a741b9f -40a028f5c28f5c29_40b004189374bc6a_3fe024d3c19930d9 -40b004189374bc6a_40b004189374bc6a_3ff0000000000000 -40c00068db8bac71_40b004189374bc6a_400ff8a272e15ca2 -40dd1745d1745d17_40b004189374bc6a_401d0fd53890e409 -40e5555555555555_40b004189374bc6a_40254fe0a0f2c95b -40f999999999999a_40b004189374bc6a_4039930d8df024d5 -410c71c71c71c71c_40b004189374bc6a_404c6a80d6990c7a -4000000000000000_40c00068db8bac71_3f3fff2e4e46e7a8 -4018000000000000_40c00068db8bac71_3f47ff62bab52dbe -4024000000000000_40c00068db8bac71_3f53ff7cf0ec50c9 -4032000000000000_40c00068db8bac71_3f61ff8a0c07e24f -4041000000000000_40c00068db8bac71_3f70ff909995ab11 -405c000000000000_40c00068db8bac71_3f8bff48847e0ab3 -406e000000000000_40c00068db8bac71_3f9dff3b6962792e -407ffff583a53b8e_40c00068db8bac71_3fafff23d230d9a4 -408199999999999a_40c00068db8bac71_3fb1992644a6ff6a -4093333333333333_40c00068db8bac71_3fc332b5622a8afe -40a028f5c28f5c29_40c00068db8bac71_3fd0288bdd4a34fd -40b004189374bc6a_40c00068db8bac71_3fe003af9fc0ed8b -40c00068db8bac71_40c00068db8bac71_3ff0000000000000 -40dd1745d1745d17_40c00068db8bac71_400d16872fe35e3c -40e5555555555555_40c00068db8bac71_401554c989849a70 -40f999999999999a_40c00068db8bac71_402998f1d838b954 -410c71c71c71c71c_40c00068db8bac71_403c710cb75b7895 -4000000000000000_40dd1745d1745d17_3f2199999999999a -4018000000000000_40dd1745d1745d17_3f3a666666666667 -4024000000000000_40dd1745d1745d17_3f46000000000000 -4032000000000000_40dd1745d1745d17_3f53cccccccccccd -4041000000000000_40dd1745d1745d17_3f62b33333333333 -405c000000000000_40dd1745d1745d17_3f7ecccccccccccd -406e000000000000_40dd1745d1745d17_3f80800000000000 -407ffff583a53b8e_40dd1745d1745d17_3f919993d5347a5b -408199999999999a_40dd1745d1745d17_3fa35c28f5c28f5d -4093333333333333_40dd1745d1745d17_3fb51eb851eb851f -40a028f5c28f5c29_40dd1745d1745d17_3fc1c6a7ef9db22d -40b004189374bc6a_40dd1745d1745d17_3fd19e1b089a0275 -40c00068db8bac71_40dd1745d1745d17_3fe19a0cf1800a7c -40dd1745d1745d17_40dd1745d1745d17_3ff0000000000000 -40e5555555555555_40dd1745d1745d17_4007777777777777 -40f999999999999a_40dd1745d1745d17_401c28f5c28f5c2a -410c71c71c71c71c_40dd1745d1745d17_402f49f49f49f49f -4000000000000000_40e5555555555555_3f18000000000000 -4018000000000000_40e5555555555555_3f22000000000000 -4024000000000000_40e5555555555555_3f3e000000000000 -4032000000000000_40e5555555555555_3f4b000000000000 -4041000000000000_40e5555555555555_3f59800000000000 -405c000000000000_40e5555555555555_3f65000000000000 -406e000000000000_40e5555555555555_3f76800000000000 -407ffff583a53b8e_40e5555555555555_3f87fff822bbecab -408199999999999a_40e5555555555555_3f9a666666666667 -4093333333333333_40e5555555555555_3faccccccccccccd -40a028f5c28f5c29_40e5555555555555_3fb83d70a3d70a3e -40b004189374bc6a_40e5555555555555_3fc80624dd2f1a9f -40c00068db8bac71_40e5555555555555_3fd8009d495182aa -40dd1745d1745d17_40e5555555555555_3fe5d1745d1745d2 -40e5555555555555_40e5555555555555_3ff0000000000000 -40f999999999999a_40e5555555555555_4003333333333334 -410c71c71c71c71c_40e5555555555555_4015555555555555 -4000000000000000_40f999999999999a_3f04000000000000 -4018000000000000_40f999999999999a_3f1e000000000000 -4024000000000000_40f999999999999a_3f29000000000000 -4032000000000000_40f999999999999a_3f36800000000000 -4041000000000000_40f999999999999a_3f45400000000000 -405c000000000000_40f999999999999a_3f51800000000000 -406e000000000000_40f999999999999a_3f62c00000000000 -407ffff583a53b8e_40f999999999999a_3f73fff972474538 -408199999999999a_40f999999999999a_3f86000000000000 -4093333333333333_40f999999999999a_3f97ffffffffffff -40a028f5c28f5c29_40f999999999999a_3fa4333333333333 -40b004189374bc6a_40f999999999999a_3fb4051eb851eb84 -40c00068db8bac71_40f999999999999a_3fc40083126e978d -40dd1745d1745d17_40f999999999999a_3fd22e8ba2e8ba2e -40e5555555555555_40f999999999999a_3feaaaaaaaaaaaaa -40f999999999999a_40f999999999999a_3ff0000000000000 -410c71c71c71c71c_40f999999999999a_4001c71c71c71c71 -4000000000000000_410c71c71c71c71c_3ef2000000000000 -4018000000000000_410c71c71c71c71c_3f0b000000000000 -4024000000000000_410c71c71c71c71c_3f16800000000000 -4032000000000000_410c71c71c71c71c_3f24400000000000 -4041000000000000_410c71c71c71c71c_3f33200000000000 -405c000000000000_410c71c71c71c71c_3f4f800000000000 -406e000000000000_410c71c71c71c71c_3f50e00000000000 -407ffff583a53b8e_410c71c71c71c71c_3f61fffa1a0cf180 -408199999999999a_410c71c71c71c71c_3f73ccccccccccce -4093333333333333_410c71c71c71c71c_3f8599999999999a -40a028f5c28f5c29_410c71c71c71c71c_3f922e147ae147ae -40b004189374bc6a_410c71c71c71c71c_3fa2049ba5e353f8 -40c00068db8bac71_410c71c71c71c71c_3fb20075f6fd21ff -40dd1745d1745d17_410c71c71c71c71c_3fc05d1745d1745d -40e5555555555555_410c71c71c71c71c_3fd8000000000000 -40f999999999999a_410c71c71c71c71c_3fecccccccccccce -410c71c71c71c71c_410c71c71c71c71c_3ff0000000000000 +0000000000000_0000000000000_0000000000000 +8000000000000_0000000000000_8000000000000 +4000000000000_0000000000000_4000000000000 +2000000000000_0000000000000_2000000000000 +1000000000000_0000000000000_1000000000000 +c000000000000_0000000000000_c000000000000 +e000000000000_0000000000000_e000000000000 +ffff583a53b8e_0000000000000_ffff583a53b8e +199999999999a_0000000000000_199999999999a +3333333333333_0000000000000_3333333333333 +028f5c28f5c29_0000000000000_028f5c28f5c29 +004189374bc6a_0000000000000_004189374bc6a +00068db8bac71_0000000000000_00068db8bac71 +d1745d1745d17_0000000000000_d1745d1745d17 +5555555555555_0000000000000_5555555555555 +999999999999a_0000000000000_999999999999a +c71c71c71c71c_0000000000000_c71c71c71c71c +0000000000000_8000000000000_5555555555555 +8000000000000_8000000000000_0000000000000 +4000000000000_8000000000000_aaaaaaaaaaaab +2000000000000_8000000000000_8000000000000 +1000000000000_8000000000000_6aaaaaaaaaaab +c000000000000_8000000000000_2aaaaaaaaaaab +e000000000000_8000000000000_4000000000000 +ffff583a53b8e_8000000000000_5554e57c37d09 +199999999999a_8000000000000_7777777777778 +3333333333333_8000000000000_9999999999999 +028f5c28f5c29_8000000000000_58bf258bf258c +004189374bc6a_8000000000000_55acb6f46508d +00068db8bac71_8000000000000_555e124ba3b41 +d1745d1745d17_8000000000000_364d9364d9365 +5555555555555_8000000000000_c71c71c71c71c +999999999999a_8000000000000_1111111111111 +c71c71c71c71c_8000000000000_2f684bda12f68 +0000000000000_4000000000000_999999999999a +8000000000000_4000000000000_3333333333333 +4000000000000_4000000000000_0000000000000 +2000000000000_4000000000000_ccccccccccccd +1000000000000_4000000000000_b333333333333 +c000000000000_4000000000000_6666666666666 +e000000000000_4000000000000_8000000000000 +ffff583a53b8e_4000000000000_99991361dc93e +199999999999a_4000000000000_c28f5c28f5c2a +3333333333333_4000000000000_eb851eb851eb8 +028f5c28f5c29_4000000000000_9db22d0e56042 +004189374bc6a_4000000000000_9a027525460aa +00068db8bac71_4000000000000_99a415f45e0b5 +d1745d1745d17_4000000000000_745d1745d1746 +5555555555555_4000000000000_1111111111111 +999999999999a_4000000000000_47ae147ae147b +c71c71c71c71c_4000000000000_6c16c16c16c16 +0000000000000_2000000000000_c71c71c71c71c +8000000000000_2000000000000_5555555555555 +4000000000000_2000000000000_1c71c71c71c72 +2000000000000_2000000000000_0000000000000 +1000000000000_2000000000000_e38e38e38e38e +c000000000000_2000000000000_8e38e38e38e39 +e000000000000_2000000000000_aaaaaaaaaaaab +ffff583a53b8e_2000000000000_c71bdca59fc0c +199999999999a_2000000000000_f49f49f49f4a0 +3333333333333_2000000000000_1111111111111 +028f5c28f5c29_2000000000000_cba9876543210 +004189374bc6a_2000000000000_c790f3f086b67 +00068db8bac71_2000000000000_c7281864da457 +d1745d1745d17_2000000000000_9dbcc48676f31 +5555555555555_2000000000000_2f684bda12f68 +999999999999a_2000000000000_6c16c16c16c17 +c71c71c71c71c_2000000000000_948b0fcd6e9e0 +0000000000000_1000000000000_e1e1e1e1e1e1e +8000000000000_1000000000000_6969696969697 +4000000000000_1000000000000_2d2d2d2d2d2d3 +2000000000000_1000000000000_0f0f0f0f0f0f1 +1000000000000_1000000000000_0000000000000 +c000000000000_1000000000000_a5a5a5a5a5a5a +e000000000000_1000000000000_c3c3c3c3c3c3c +ffff583a53b8e_1000000000000_e1e143faa9268 +199999999999a_1000000000000_0909090909091 +3333333333333_1000000000000_2121212121212 +028f5c28f5c29_1000000000000_e6b3804d19e6b +004189374bc6a_1000000000000_e25d3e863448b +00068db8bac71_1000000000000_e1ee37f25085c +d1745d1745d17_1000000000000_b6132a7041b61 +5555555555555_1000000000000_4141414141414 +999999999999a_1000000000000_8181818181818 +c71c71c71c71c_1000000000000_ac5701ac5701a +0000000000000_c000000000000_2492492492492 +8000000000000_c000000000000_b6db6db6db6db +4000000000000_c000000000000_6db6db6db6db7 +2000000000000_c000000000000_4924924924925 +1000000000000_c000000000000_36db6db6db6db +c000000000000_c000000000000_0000000000000 +e000000000000_c000000000000_1249249249249 +ffff583a53b8e_c000000000000_2491e945e6b2d +199999999999a_c000000000000_41d41d41d41d5 +3333333333333_c000000000000_5f15f15f15f16 +028f5c28f5c29_c000000000000_277f44c118de6 +004189374bc6a_c000000000000_24dd2f1a9fbe7 +00068db8bac71_c000000000000_2499c689fa081 +d1745d1745d17_c000000000000_09f959c427e56 +5555555555555_c000000000000_8618618618618 +999999999999a_c000000000000_d41d41d41d41e +c71c71c71c71c_c000000000000_0410410410410 +0000000000000_e000000000000_1111111111111 +8000000000000_e000000000000_999999999999a +4000000000000_e000000000000_5555555555555 +2000000000000_e000000000000_3333333333333 +1000000000000_e000000000000_2222222222222 +c000000000000_e000000000000_dddddddddddde +e000000000000_e000000000000_0000000000000 +ffff583a53b8e_e000000000000_1110b796930d4 +199999999999a_e000000000000_2c5f92c5f92c6 +3333333333333_e000000000000_47ae147ae147b +028f5c28f5c29_e000000000000_13cc1e098ead6 +004189374bc6a_e000000000000_1156f8c384071 +00068db8bac71_e000000000000_11180ea2e95ce +d1745d1745d17_e000000000000_f07c1f07c1f07 +5555555555555_e000000000000_6c16c16c16c16 +999999999999a_e000000000000_b4e81b4e81b4f +c71c71c71c71c_e000000000000_e573ac901e573 +0000000000000_ffff583a53b8e_000053e2f1a08 +8000000000000_ffff583a53b8e_80007dd46a70b +4000000000000_ffff583a53b8e_400068dbae089 +2000000000000_ffff583a53b8e_20005e5f4fd48 +1000000000000_ffff583a53b8e_1000592120ba8 +c000000000000_ffff583a53b8e_c00092cd26d8d +e000000000000_ffff583a53b8e_e0009d49850ce +ffff583a53b8e_ffff583a53b8e_0000000000000 +199999999999a_ffff583a53b8e_1999f5e009ca2 +3333333333333_ffff583a53b8e_333397dd21f3c +028f5c28f5c29_ffff583a53b8e_028fb0e2a73e4 +004189374bc6a_ffff583a53b8e_0041dd2fb6fd0 +00068db8bac71_ffff583a53b8e_0006e19dd229c +d1745d1745d17_ffff583a53b8e_d174f59ca00c8 +5555555555555_ffff583a53b8e_5555c52e9780a +999999999999a_ffff583a53b8e_999a1fd1829a6 +c71c71c71c71c_ffff583a53b8e_c71d06e8ca00d +0000000000000_199999999999a_d1745d1745d17 +8000000000000_199999999999a_5d1745d1745d1 +4000000000000_199999999999a_22e8ba2e8ba2e +2000000000000_199999999999a_05d1745d1745d +1000000000000_199999999999a_ee8ba2e8ba2e8 +c000000000000_199999999999a_9745d1745d174 +e000000000000_199999999999a_b45d1745d1745 +ffff583a53b8e_199999999999a_d173c4921d90c +199999999999a_199999999999a_0000000000000 +3333333333333_199999999999a_1745d1745d174 +028f5c28f5c29_199999999999a_d61bed61bed61 +004189374bc6a_199999999999a_d1eb851eb851d +00068db8bac71_199999999999a_d180477e6ade4 +d1745d1745d17_199999999999a_a723f789854a0 +5555555555555_199999999999a_364d9364d9364 +999999999999a_199999999999a_745d1745d1746 +c71c71c71c71c_199999999999a_9dbcc48676f30 +0000000000000_3333333333333_aaaaaaaaaaaab +8000000000000_3333333333333_4000000000000 +4000000000000_3333333333333_0aaaaaaaaaaab +2000000000000_3333333333333_e000000000000 +1000000000000_3333333333333_c555555555556 +c000000000000_3333333333333_7555555555556 +e000000000000_3333333333333_9000000000000 +ffff583a53b8e_3333333333333_aaaa1edb45c4c +199999999999a_3333333333333_d555555555556 +3333333333333_3333333333333_0000000000000 +028f5c28f5c29_3333333333333_aeeeeeeeeeeef +004189374bc6a_3333333333333_ab17e4b17e4b1 +00068db8bac71_3333333333333_aab596de8ca12 +d1745d1745d17_3333333333333_83e0f83e0f83e +5555555555555_3333333333333_1c71c71c71c72 +999999999999a_3333333333333_5555555555556 +c71c71c71c71c_3333333333333_7b425ed097b42 +0000000000000_028f5c28f5c29_faee41e6a7498 +8000000000000_028f5c28f5c29_7c32b16cfd772 +4000000000000_028f5c28f5c29_3cd4e930288df +2000000000000_028f5c28f5c29_1d260511be196 +1000000000000_028f5c28f5c29_0d4e930288df1 +c000000000000_028f5c28f5c29_bb9079a9d2605 +e000000000000_028f5c28f5c29_db3f5dc83cd4f +ffff583a53b8e_028f5c28f5c29_faed9bca398bf +199999999999a_028f5c28f5c29_16cfd7720f354 +3333333333333_028f5c28f5c29_30288df0cac5b +028f5c28f5c29_028f5c28f5c29_0000000000000 +004189374bc6a_028f5c28f5c29_fb70081c635bb +00068db8bac71_028f5c28f5c29_fafb3c1f3a182 +d1745d1745d17_028f5c28f5c29_ccd899003afd0 +5555555555555_028f5c28f5c29_51f42bef1a310 +999999999999a_028f5c28f5c29_958b67ebb907a +c71c71c71c71c_028f5c28f5c29_c29ae53ecd96a +0000000000000_004189374bc6a_ff7d0f16c2e0a +8000000000000_004189374bc6a_7f9dcb5112287 +4000000000000_004189374bc6a_3fae296e39cc6 +2000000000000_004189374bc6a_1fb6587ccd9e5 +1000000000000_004189374bc6a_0fba700417875 +c000000000000_004189374bc6a_bf8d6d33ea848 +e000000000000_004189374bc6a_df853e2556b29 +ffff583a53b8e_004189374bc6a_ff7c677bfebb5 +199999999999a_004189374bc6a_1951951951953 +3333333333333_004189374bc6a_32e4a2a741b9f +028f5c28f5c29_004189374bc6a_024d3c19930d9 +004189374bc6a_004189374bc6a_0000000000000 +00068db8bac71_004189374bc6a_ff8a272e15ca2 +d1745d1745d17_004189374bc6a_d0fd53890e409 +5555555555555_004189374bc6a_54fe0a0f2c95b +999999999999a_004189374bc6a_9930d8df024d5 +c71c71c71c71c_004189374bc6a_c6a80d6990c7a +0000000000000_00068db8bac71_fff2e4e46e7a8 +8000000000000_00068db8bac71_7ff62bab52dbe +4000000000000_00068db8bac71_3ff7cf0ec50c9 +2000000000000_00068db8bac71_1ff8a0c07e24f +1000000000000_00068db8bac71_0ff909995ab11 +c000000000000_00068db8bac71_bff48847e0ab3 +e000000000000_00068db8bac71_dff3b6962792e +ffff583a53b8e_00068db8bac71_fff23d230d9a4 +199999999999a_00068db8bac71_1992644a6ff6a +3333333333333_00068db8bac71_332b5622a8afe +028f5c28f5c29_00068db8bac71_0288bdd4a34fd +004189374bc6a_00068db8bac71_003af9fc0ed8b +00068db8bac71_00068db8bac71_0000000000000 +d1745d1745d17_00068db8bac71_d16872fe35e3c +5555555555555_00068db8bac71_554c989849a70 +999999999999a_00068db8bac71_998f1d838b954 +c71c71c71c71c_00068db8bac71_c710cb75b7895 +0000000000000_d1745d1745d17_199999999999a +8000000000000_d1745d1745d17_a666666666667 +4000000000000_d1745d1745d17_6000000000000 +2000000000000_d1745d1745d17_3cccccccccccd +1000000000000_d1745d1745d17_2b33333333333 +c000000000000_d1745d1745d17_ecccccccccccd +e000000000000_d1745d1745d17_0800000000000 +ffff583a53b8e_d1745d1745d17_19993d5347a5b +199999999999a_d1745d1745d17_35c28f5c28f5d +3333333333333_d1745d1745d17_51eb851eb851f +028f5c28f5c29_d1745d1745d17_1c6a7ef9db22d +004189374bc6a_d1745d1745d17_19e1b089a0275 +00068db8bac71_d1745d1745d17_19a0cf1800a7c +d1745d1745d17_d1745d1745d17_0000000000000 +5555555555555_d1745d1745d17_7777777777777 +999999999999a_d1745d1745d17_c28f5c28f5c2a +c71c71c71c71c_d1745d1745d17_f49f49f49f49f +0000000000000_5555555555555_8000000000000 +8000000000000_5555555555555_2000000000000 +4000000000000_5555555555555_e000000000000 +2000000000000_5555555555555_b000000000000 +1000000000000_5555555555555_9800000000000 +c000000000000_5555555555555_5000000000000 +e000000000000_5555555555555_6800000000000 +ffff583a53b8e_5555555555555_7fff822bbecab +199999999999a_5555555555555_a666666666667 +3333333333333_5555555555555_ccccccccccccd +028f5c28f5c29_5555555555555_83d70a3d70a3e +004189374bc6a_5555555555555_80624dd2f1a9f +00068db8bac71_5555555555555_8009d495182aa +d1745d1745d17_5555555555555_5d1745d1745d2 +5555555555555_5555555555555_0000000000000 +999999999999a_5555555555555_3333333333334 +c71c71c71c71c_5555555555555_5555555555555 +0000000000000_999999999999a_4000000000000 +8000000000000_999999999999a_e000000000000 +4000000000000_999999999999a_9000000000000 +2000000000000_999999999999a_6800000000000 +1000000000000_999999999999a_5400000000000 +c000000000000_999999999999a_1800000000000 +e000000000000_999999999999a_2c00000000000 +ffff583a53b8e_999999999999a_3fff972474538 +199999999999a_999999999999a_6000000000000 +3333333333333_999999999999a_7ffffffffffff +028f5c28f5c29_999999999999a_4333333333333 +004189374bc6a_999999999999a_4051eb851eb84 +00068db8bac71_999999999999a_40083126e978d +d1745d1745d17_999999999999a_22e8ba2e8ba2e +5555555555555_999999999999a_aaaaaaaaaaaaa +999999999999a_999999999999a_0000000000000 +c71c71c71c71c_999999999999a_1c71c71c71c71 +0000000000000_c71c71c71c71c_2000000000000 +8000000000000_c71c71c71c71c_b000000000000 +4000000000000_c71c71c71c71c_6800000000000 +2000000000000_c71c71c71c71c_4400000000000 +1000000000000_c71c71c71c71c_3200000000000 +c000000000000_c71c71c71c71c_f800000000000 +e000000000000_c71c71c71c71c_0e00000000000 +ffff583a53b8e_c71c71c71c71c_1fffa1a0cf180 +199999999999a_c71c71c71c71c_3ccccccccccce +3333333333333_c71c71c71c71c_599999999999a +028f5c28f5c29_c71c71c71c71c_22e147ae147ae +004189374bc6a_c71c71c71c71c_2049ba5e353f8 +00068db8bac71_c71c71c71c71c_20075f6fd21ff +d1745d1745d17_c71c71c71c71c_05d1745d1745d +5555555555555_c71c71c71c71c_8000000000000 +999999999999a_c71c71c71c71c_cccccccccccce +c71c71c71c71c_c71c71c71c71c_0000000000000 +838d071a0e342_2cfc59f8b3f16_49a082c638aeb +4f029e053c0a8_88d711ae235c4_b4a0ece3271c9 +f297e52fca5fa_2bf657ecafd96_a98512f9eeb0d +b3c5678acf15a_39f673ece7d9d_6352102e4640a +7ea8fd51faa3f_1fec3fd87fb10_543bc490cb0f8 +157a2af455e8b_63bec77d8efb2_8f5aa9c461ea7 +46f88df11be24_5e38bc7178e2f_de02518ff11b4 +fbc3f787ef0fe_890f121e243c4_4ab569d997a57 +c4038807100e2_a57f4afe95fd2_1288d4a86eec2 +c46388c7118e2_c7bd8f7b1ef64_fc3c0db5c0f41 +d2ada55b4ab6a_26e44dc89b914_952163b89177d +a01f403e807d0_508ea11d423a8_3c8542614b454 +58ceb19d633ac_eacdd59bab376_67b2c4ee8dfbc +850f0a1e143c2_66b2cd659acb3_15aafa9a4052d +9b5536aa6d54e_c911922324464_ccc482a9a6c6e +ee79dcf3b9e77_deb3bd677acf0_086f8140e09d3 +ddd5bbab7756f_acad595ab2b56_1d5b37e16e3c5 +c227844f089e1_94f729ee53dca_1c90f7056c3ff +63a4c7498e932_5b0ab6156c2ae_0658624bef7e8 +33426684cd09a_d3b1a7634ec6a_505df1d3f1b78 +6a78d4f1a9e35_76a8ed51daa3b_ef5829a397e70 +faabf557eaafe_205e40bc81790_c1ccc2258957c +366e6cdcd9b9b_f55deabbd577a_3d03db89df0ea +bccb7996f32de_68b6d16da2db4_3bac1e9001f3a +c7b58f6b1ed64_c205840b08161_033c49b0072ea +f4f3e9e7d3cfa_07300e601cc04_e7458ab6189b4 +5198a33146629_c1c7838f071e1_804c455579c2e +3e347c68f8d1f_96ed2dda5bb4c_905e9ad06352b +0b1c16382c706_f4bfe97fd2ffa_111c61df4bc8f +51b2a36546ca9_0f321e643cc88_3ec697dd8b4c6 +711ee23dc47b8_ea3fd47fa8ff5_817f4b51aef1e +927f24fe49fc9_1e6c3cd879b0f_67beb22961724 +91dd23ba47749_4086810d021a0_40f6cd64dffd4 +7ef0fde1fbc40_3c9a7934f269e_35a3c4ab1f1b3 +7a1af435e86bd_67f4cfe99fd34_0ce852fd89dc2 +df7dbefb7df70_6d4cda99b5337_5006384057f3c +5bb4b7696ed2e_61c8c39187231_f73412a7f0202 +0b0c16182c306_291c5238a4714_cc315b5b2088e +85b90b7216e43_b25364a6c94d9_cb6b9bf169534 +18da31b46368c_669ccd399a733_90fad7506dd95 +c5ff8bff17fe3_3eac7d58fab1f_6cb5c8ae7a795 +57c2af855f0ac_3ae075c0eb81e_177ba071374b0 +4c40988131026_4df69bed37da7_fd607b0904ec4 +e31fc63f8c7f2_096212c425885_d20ada41d6c2a +a6b14d629ac54_660acc15982b3_2e399a99dd192 +ad215a42b4856_bb8b7716ee2de_ef5c5e2748e33 +f013e027c04f8_3bb87770eee1e_923dca6b59f30 +d6a7ad4f5a9ec_f79bef37de6fc_de7f2e8fb400a +c7558eab1d564_6e76dcedb9db7_3e14e46513b97 +ac915922b2456_cf339e673cce8_d9b7aa9bed9f7 +28a45148a2914_47a68f4d1e9a4_cf8b6269a6fff +22a445488a911_dd3bba7774eee_37d0a8b5fce1c +c00d801b00360_353e6a7cd4f9b_72e8dbe5def6a +23d447a88f512_4b6a96d52daa6_c2d7a9ad4c41c +cd859b0b36167_380c7018e031c_7aa02c18d7d1b +9027204e409c8_b7316e62dcc5c_d27ce580270df +32926524ca499_fd65facbf597e_34233a1906bfd +40028005000a0_6e3cdc79b8f37_bf5f9320a4186 +c15982b305660_dc65b8cb7196e_e2ee52292b278 +e511ca2394472_fa63f4c7e98fd_ea715edac7509 +6538ca7194e32_6ea4dd49ba937_f2d7a8effa805 +208c411882310_752aea55d4aba_8be60428bbcdb +3ce279c4f389e_fc6df8dbf1b7e_3f1c277ac926a +a71f4e3e9c7d4_9aaf355e6abce_07c0ce55c58a2 +3dec7bd8f7b1f_7472e8e5d1cba_b50b8e69c4a11 +ca3b947728ee5_142c285850b0a_a8c3128c04a9f +79f4f3e9e7d3d_27104e209c414_47eb3b20c609b +3ee87dd0fba20_f1ebe3d7c7af9_47ecd9096e767 +9d313a6274c4e_fcf9f9f3f3e7e_9fa5969ddde22 +7a2ef45de8bbd_ccb9997332e66_a445af00e1996 +be837d06fa0e0_6176c2ed85db1_43646a3e4403c +7adaf5b5eb6be_86e30dc61b8c4_f03d907f0efb5 +191c32386470d_981f303e607cc_60a90d7f12e32 +58e0b1c16382c_24b2496492c92_2da39d62040b9 +c78f8f1f1e3e4_b6036c06d80db_0a4176105d842 +7236e46dc8db9_b45f68bed17da_b2603b8c18750 +186630cc6198c_f67becf7d9efb_1db5955bc96be +8d231a46348c6_bd817b02f605f_c8697bbb99686 +943b287650eca_a34b46968d2d2_ed9b4b5915f61 +c81b9037206e4_301a6034c0698_7ff5e5d9a4b66 +4d569aad355a7_486690cd219a4_03d95cf345712 +af1b5e36bc6d8_4afc95f92bf26_4d70007bc146c +90bd217a42f48_6b1ed63dac7b6_1a855bf8e7dd2 +4e7c9cf939f27_71cce399c7339_cf1b757a501f1 +90d121a243448_7ce8f9d1f3a3e_0d60ff3a676de +9b4d369a6d34e_6a74d4e9a9d35_227fbe5016ddf +216242c485891_4186830d061a1_ccd142460b129 +0926124c24985_fa23f447e88fd_0c37e42e47f36 +1d503aa07540f_60c8c19183230_9e142bed1c14a +a58f4b1e963d3_59b6b36d66dad_3829ee931bdfa +8d951b2a36547_5bc0b7816f02e_24aeae5edd06a +90c1218243048_79c2f385e70bd_0f94ec8426a0f +29e653cca7995_9d7f3afe75fce_70dd7e45f1330 +2c125824b0496_8e011c0238047_8204833d1f2e7 +4ace959d2b3a6_df45be8b7d170_61657c7030ace +d5c7ab8f571eb_d84bb097612ec_fd45d6f93dc6e +e541ca8395072_98433086610cc_30477c50e4409 +8a6314c6298c5_2b0e561cac396_519b1e972c72a +a7ab4f569ead4_b0c5618ac3158_f53b5aadcc06d +438a87150e2a2_1b5036a06d40e_24597c9801866 +d09fa13f427e8_30fc61f8c3f18_85ff47547f906 +6c5cd8b9b1736_5a12b425684ad_0d87835a1c635 +d6d7adaf5b5ec_232846508ca12_9dfcf6b831d81 +433e867d0cfa2_2d605ac0b5817_129349ec50fdb +7adaf5b5eb6be_6152c2a5854b1_127fcbd4b4f63 +813d027a04f40_80b5016a02d40_005a80b700811 +5a16b42d685ad_868d0d1a1a344_c5b61a26024de +1ee03dc07b80f_85010a0214042_7994b2736d2df +9b6d36da6db4e_bb9f773eee7de_dad757b532090 +8e8f1d1e3a3c8_5818b0316062c_2884d9bc7e5d3 +cd4d9a9b35366_974b2e965d2cc_21f2725bbaefe +445488a911522_abb15762aec56_8443358ca6e8f +8d591ab235646_c9f793ef27de5_bc3a975592739 +e341c6838d072_e3d7c7af8f5f2_ff614414ffcb2 +116e22dc45b89_ccf399e733ce6_2fb6221648f6f +e849d093a1274_a4e549ca93952_28fd72be99708 +2a46548ca9195_4d249a4934926_ca696952447a3 +2a905520aa415_4900920124024_d0a18f60946de +d78baf175e2ec_894d129a25344_32edf1293a076 +094e129c25385_350a6a14d429a_b78a93320a4db +056e0adc15b83_5baeb75d6ebae_80fbd2da9eb39 +9f193e327c650_85210a4214842_1115b7402e61d +8bc917922f246_27564eac9d594_5711babc13575 +d2c7a58f4b1ea_0888111022204_c3b9becfa23f3 +06a40d481a903_60ccc19983330_7d282d4eba182 +9dc73b8e771cf_05380a7014e03_9582e7dbcca3a +a06740ce819d0_ea4bd497a92f5_b2d60c6f05a12 +5ff2bfe57fcb0_babd757aeaf5e_970152d880fb8 +6554caa995533_fb75f6ebedd7e_68870b8b4a360 +98e731ce639cc_1cc039807300e_6f9de3e3eeb8a +38ba7174e2e9c_cc97992f325e6_5ba1f62fade09 +dee3bdc77b8f0_bcfd79faf3f5e_13808cf384b8c +037c06f80df02_bd537aa6f54de_2a5595b836538 +6b18d631ac636_5caeb95d72bae_0a954087d4680 +34326864d0c9a_2ee25dc4bb898_047d8462783c0 +1386270c4e18a_1d943b287650f_edf911068c5d6 +28bc5178a2f14_c9cb9397272e5_4bdecbdecbdec +0a5414a829505_ca6794cf299e5_2977814bbc0a6 +995932b26564c_6710ce219c434_23d9856c2db29 +3aa27544ea89d_2ecc5d98bb317_0a01c88e32b05 +9d433a86750ce_54f6a9ed53daa_36487aaafac18 +9aeb35d66bace_f6cfed9fdb3fc_a26d6b80ae214 +60c8c19183230_2f345e68bcd18_29dc5dbf86d64 +4cd299a5334a6_0dde1bbc37787_3bb85176f36a6 +24de49bc93792_02ac05580ab01_21d7d6fd41500 +e285c50b8a172_f541ea83d507a_ecdd1118f74a4 +a03b407680ed0_f4a3e947d28fa_a9ad081e2b97f +a18b4316862d1_0a04140828105_91d2a2067b23b +59eeb3dd67bad_25764aec95d93_2dc5affcba861 +1b2436486c90e_328a6514ca299_d8eae2e673183 +157c2af855f0b_06de0dbc1b783_0e3c5a067b88b +f21be437c86f9_eb6dd6dbadb76_037ad126ca43e +e871d0e3a1c74_dd99bb337666f_05d0045af0d1c +26204c4098813_2bfa57f4afe96_f60325a16e1e4 +117622ec45d89_a6a94d529aa54_4b4374a1972f5 +bca37946f28de_1a38347068e0d_93545af7a8a20 +28f651eca3d94_180e301c6038c_0f745dc177b56 +1f283e507ca10_064e0c9c19383_184145017aaf8 +c327864f0c9e2_f4fbe9f7d3efa_cd131d6e548a6 +07240e481c904_a5874b0e961d3_3f9e38327c076 +1ba837506ea0e_6d8cdb19b6337_8d4c54c332579 +4f4a9e953d2a8_04c2098413082_492c6cfa5ad0b +e2a3c5478a8f2_c2038407080e1_128f5c28f5c29 +827104e209c41_2a7054e0a9c15_4b7d0c41eb1aa +c34f869f0d3e2_e17fc2ff85ff0_dfe6368c4868e +7fe2ffc5ff8c0_e009c01380270_9972593cc04eb +bc1b7836f06de_3c2a7854f0a9e_67982711bcf1d +0d361a6c34d87_9b0136026c04e_4f5d31a90a2a7 +e03fc07f80ff0_8107020e041c0_3f4fcca2c71e9 +adab5b56b6ad7_fd49fa93f527e_aff4e0d68472a +9ad335a66b4ce_7f10fe21fc440_128d06353ee3a +96f92df25be4c_e53fca7f94ff2_ad68b32dec986 +0b6c16d82db06_e203c407880f1_1c0edf120edf1 +1bb437686ed0e_85270a4e149c2_754376232242a +942f285e50bca_028a05140a281_9036f4e41e92a +6316c62d8c5b2_7a24f449e893d_e0c8907fded3a +316462c8c5919_8205040a08141_950f250fb99e4 +c6678ccf199e3_5ab8b5716ae2d_4f81d4dcfabeb +b2a16542ca85a_e9add35ba6b75_c671322b496d1 +abc35786af0d6_b4ad695ad2b5a_f58c4ba570d08 +6d48da91b5237_055a0ab415683_65cdfb4930e2c +36846d08da11b_f295e52bca57a_3edf2c94581b9 +80b9017202e40_31ba6374c6e99_422550ba50a63 +a50d4a1a94352_20c2418483090_7548ebd48ebd5 +43d287a50f4a2_5606ac0d581ab_e4bff1c74706b +b425684ad095a_09c2138427085_a421b7451e1a8 +f41fe83fd07fa_c137826f04de0_1d02e96d3bc26 +dfd5bfab7f570_a24d449a89351_25a87dbb3226e +3e587cb0f961f_a2c345868b0d2_85399e7da18c2 +d9b9b37366e6d_3cc47988f311e_7ed902df7393d +b8917122e245c_56d6adad5b5ac_48f9b0139a064 +0cda19b433686_7c28f851f0a3e_6a17134018947 +e5c1cb8397073_3e067c0cf819f_8704bded82a5d +870b0e161c2c4_7e94fd29fa53f_05a96574b33ae +dae5b5cb6b96e_588cb1196232c_60d925e959757 +1fb43f687ed10_372c6e58dcb1c_d9623b2bde16b +1d903b207640f_5cfab9f573eae_a2f5cc6b61161 +34386870d0e1a_6fa2df45be8b8_ad40acb29de66 +d40ba817502ea_827d04fa09f41_360579a085a36 +d1cba397472e9_6924d249a4934_4a2ee86f6d59c +dee1bdc37b870_b6876d0eda1dc_178e86ba2c6c3 +a4bf497e92fd2_94d929b25364a_0a0daf3f0d7df +f407e80fd01fa_760aec15d82bb_563a640e499ea +85670ace159c2_5bd6b7ad6f5ae_1e96fe7e56982 +5366a6cd4d9aa_0240048009001_5071a1388349b +fa6bf4d7e9afd_6e9add35ba6b7_61a24b49a6a8a +2cfc59f8b3f16_28cc5198a3314_039cab91d58f2 +88a1114222844_94032806500ca_f1930288df0ca +506ca0d941b28_5780af015e02c_f573152a3b1f4 +286650cca1994_6fc2df85bf0b8_9ca65fb79a5da +3e1e7c3cf879f_33926724ce49a_08c7591d148c7 +b87170e2e1c5c_385c70b8e171c_68f8b1b27c1a9 +31d263a4c7499_6c52d8a5b14b6_adc8ed28b6596 +c6338c6718ce3_d49fa93f527ea_f03e242cd49cb +3ebc7d78faf1f_016202c405881_3d06179f84a99 +83a307460e8c2_5892b125624ac_1ffe839948c3d +15162a2c5458b_b47768eed1dda_4509d0c3c285d +42a6854d0a9a1_59fab3f567ead_dd7a05c7e706d +893f127e24fc4_de7fbcff79fef_a4c7545318809 +4ddc9bb937727_144a28945128a_35581cf4bc722 +744ae895d12ba_606ac0d581ab0_0e70190fde388 +76f6ededdbdbc_d41ba837506ea_9a1f7b1a81ec4 +06220c4418883_e75fcebf9d7f4_1360bde37cb68 +32986530ca619_a2234446888d1_776b38b5d721c +2118423084610_3c6478c8f191e_d3d35eda7b6ec +99a9335266a4d_a5b54b6a96d53_f15f9245801b5 +d6ffadff5bfec_d7b1af635ec6c_ff3ec8bce8698 +282c5058a0b14_36ae6d5cdab9b_e8172cf29f5ef +9fc33f867f0d0_6f4cde99bd338_21c6f7456c12a +919d233a46749_16fa2df45be8c_708930e4f521a +6182c305860b1_b95d72bae575c_9a15f5b6a26b6 +82c5058a0b142_cb7f96ff2dfe6_aef61a194c44b +e227c44f889f1_19c833906720d_b60a34efa74e0 +a90f521ea43d4_8c99193232646_125f2eb18b9de +ba7574eae9d5d_7382e705ce0ba_30e367052b119 +d767aecf5d9ec_c6198c3318663_09c180358ee29 +62b2c5658acb1_d533aa6754cea_830d556c9d00e +a08f411e823d0_9eb13d627ac50_01271725446ef +70b4e169c2d38_397a72f4e5e9d_2d1a0e8c01f08 +3ef07de0fbc20_7ef8fdf1fbe40_aa64b316b912e +9f753eea7dd50_12a025404a809_8347eb156782f +2202440488091_0fda1fb43f688_11191a47a11f4 +b837706ee0ddc_d9d5b3ab6756d_dbac8acdbd8d8 +f915f22be457c_a8935126a24d4_308b4973215a2 +f511ea23d447a_59dcb3b96772d_72e1b429fbbb7 +93ad275a4eb4a_a429485290a52_ebe96fc1783f8 +f50bea17d42fa_ed57daafb55f6_03ff51a432f3b +6f60dec1bd838_96592cb25964b_cee5d45c79a73 +d9bdb37b66f6d_686ad0d5a1ab4_507e14773e436 +4b26964d2c9a6_d823b047608ec_671bb8b264b82 +a65b4cb6996d3_e603cc07980f3_bcf0329161f9b +9839307260e4c_63aec75d8ebb2_25d0d53af124c +7850f0a1e143c_3086610cc2198_3c5a0156ff471 +206040c081810_77ceef9ddf3bc_88e1e8c651e53 +b16162c2c5858_fe11fc23f847f_b3051ffc1c376 +b9db73b6e76dd_faf3f5e7ebcfe_be419603b96d5 +ab335666accd6_b827704ee09dc_f0ee9d5986a39 +60a2c145828b0_15a42b485690b_45261d769fd29 +0c7418e831d06_06ee0ddc1bb83_0560c6247b796 +8d5b1ab6356c6_fc7bf8f7f1efe_901a6eab66a13 +5768aed15da2c_d7f1afe35fc6c_748e3526e888e +218e431c86391_6194c32986531_a349e171715a3 +ca07940f281e5_184430886110c_a25f365b6a73c +c1a5834b06961_85930b26164c3_27799d0465095 +278c4f189e314_da4fb49f693ed_3f0841a58ab93 +f41fe83fd07fa_6008c01180230_6bb112ccc53ca +839d073a0e742_1ef43de87bd10_59cd13d0cca36 +de7fbcff79fef_d781af035e06c_03cbe4a1aeb36 +a6d14da29b454_fa59f4b3e967d_ab88ca653092a +f79fef3fde7fc_80e501ca03940_4ef83098bb71b +24d449a893512_4c129825304a6_c37e4a1b45a01 +87850f0a1e144_de85bd0b7a170_a2e91dc9d707e +bc017802f005e_c2e585cb0b962_f82ce3c43953d +4cbc997932f26_96832d065a0cc_a31477a7d52cf +16682cd059a0b_63f0c7e18fc32_9078ec39f76ce +1f2c3e587cb10_98d331a6634cc_67a58376b46ce +847f08fe11fc2_4d7a9af535ea7_2a3c1e9c8f763 +e875d0eba1d74_acb15962b2c56_23b0e458ffb4c +c9239247248e4_ed17da2fb45f6_daaacbe508e21 +c9c39387270e5_5d98bb317662f_4f353eeff3d36 +8f451e8a3d148_6162c2c5858b1_213d4e5494261 +c7258e4b1c964_bfbb7f76feee0_043d40b38a91b +a0ef41de83bd0_3f427e84fd0a0_4e523150ca12d +d06ba0d741ae8_03fc07f80ff02_c94d81c9e32e9 +77e6efcddf9bc_7296e52dca5b9_03ab814771f3a +7f78fef1fde40_5362a6c54d8aa_214157f936076 +3fc67f8cff1a0_726ee4ddc9bb9_b9fb87882e0b8 +6422c845908b2_ea1bd437a86f5_740b08dd15903 +e18fc31f863f1_80cb0196032c0_406122bde7c20 +357c6af8d5f1b_e9e3d3c7a78f5_437435908f300 +30c26184c3098_2dca5b94b7297_0284b494c51f7 +c0bd817b02f60_dc0db81b7036e_e29fcf7756c52 +d1ffa3ff47fe9_d66bacd759aeb_fb2fe853ac1fa +ed8fdb1fb63f7_5aecb5d96bb2e_6c3499d61c546 +f313e627cc4fa_56baad755aeab_74c8a781f2f99 +afe95fd2bfa58_daddb5bb6b76e_d1afc3afb8e77 +6c94d929b2536_a7994f329e654_b8aa8b3d603fe +3f6a7ed4fdaa0_0aa815502aa05_32a6a579ef92f +64fcc9f993f32_9fe33fc67f8d0_b77ce238c94a8 +6c2ad855b0ab6_c39187230e462_9ce701a02074f +0d401a8035007_9133226644cc8_579c22efb03cb +691ed23da47b4_00b8017002e00_681bfc1ac4f7f +8ee11dc23b848_f817f02fe05fc_9522b782e064e +e3dfc7bf8f7f2_d629ac5358a6b_077739e69eeb8 +c38d871b0e362_f7cbef97df2fc_cae7d09d464ce +c215842b08561_df39be737ce70_e0dd90710d716 +ce339c6738ce7_d969b2d365a6c_f3dff9ea9495e +5c3ab87570eae_1c9839307260e_393db5f107e80 +2d9c5b38b6717_46ac8d591ab23_d8b7d2664e939 +8e0d1c1a38347_b9b97372e6e5d_cd60efcb7a1a4 +6084c10982130_7822f045e08bc_dfd9e2901f4f0 +744ae895d12ba_b1cf639ec73d9_b76503d859a09 +b32d665accb5a_0ede1dbc3b787_9b4a795ca3735 +301e603cc0798_cc439887310e6_524d97b57772c +4e7a9cf539ea7_d1bfa37f46fe9_6fb1cf3be7c7b +87f30fe61fcc4_e8afd15fa2bf4_9aa5d2252544c +208e411c82390_061a0c3418683_19d68c97462c6 +bdbf7b7ef6fdf_125624ac49589_9ff455cb898b2 +b6d56daadb55c_9bf937f26fe4e_10b0df02ed6e3 +72eee5ddcbbba_531aa6354c6aa_18075c5d24734 +a1ab435686ad1_e5d3cba7974f3_b82b793b6184e +f1b3e367c6cf9_bdf37be6f7cdf_1db54c87e9530 +796af2d5e5abd_13c027804f00a_5e62a0dc43833 +b3d767aecf5da_a8e551caa3954_0698422a042bb +1d083a107420e_2a345468a8d15_e9624a918e3c4 +7f1cfe39fc740_8e851d0a3a148_ec34c6e1c5b14 +4228845108a21_ac3b5876b0ed6_812d4dcf89edf +ef15de2bbc578_8edd1dba3b748_3dc1df22b985d +eebfdd7fbaff8_b125624ac4958_2468be6d34524 +c47588eb11d62_07f60fec1fd84_b6d0113715e5d +f417e82fd05fa_9dcb3b96772cf_3563f9bc5ebc7 +d1eda3db47b69_3dc87b90f721f_7757c78ea950d +038007000e002_393e727ce4f9d_a827bd7e6f887 +de8bbd177a2f0_89ad135a26b45_37306ea1e4f64 +7454e8a9d153a_5506aa0d541aa_1780198614f30 +557eaafd55fab_096212c425885_496bae7c339c2 +539aa7354e6aa_c0d581ab03560_8365d5fa8dfb3 +1b8837106e20e_457e8afd15fa3_bdfe67027211f +d519aa335466a_c1bd837b06f61_0b0520a7c82de +61bec37d86fb1_c7658ecb1d964_8db6b77336845 +bdef7bdef7bdf_c4f389e713ce2_f811cdc4955aa +cdef9bdf37be7_16c02d805b00b_a83bfbd6a48dc +e0afc15f82bf0_85f90bf217e43_3b8caf9639ad7 +d077a0ef41de8_167a2cf459e8b_aafa572991f84 +42f685ed0bda2_605cc0b981730_d5480367db43a +7f96ff2dfe5c0_39387270e4e1d_3983929aa4b4f +0482090412082_04f609ec13d82_ff1c675046636 +d04fa09f413e8_854b0a96152c2_3154fa249f100 +9fc73f8e7f1d0_4a9095212a425_41fdfaa9dc253 +84b1096212c42_e02bc05780af0_9e74edb8fd625 +9c0f381e703ce_522ea45d48ba9_37ec9a0128bfa +a7c14f829f054_997332e665ccc_08f1a88b1e212 +490a9215242a4_b6bf6d7edafdc_7ffa2a3fb13a5 +eec7dd8fbb1f8_ad515aa2b5456_270903bb4b265 +9bed37da6fb4e_005200a401480_9b696f0d4bd85 +d825b04b6096c_b6876d0eda1dc_13a0138e90115 +c6018c0318063_12d425a84b509_a6e6db365b033 +dfb7bf6f7edf0_07dc0fb81f704_d16da8ff1cf6a +9cc939927324e_d049a09341268_c734b4bd0261d +a0a5414a82950_e517ca2f945f2_b7c187101256e +6b88d711ae236_a6774cee99dd3_b8943d2aa2fdb +3cba7974f2e9e_5376a6ed4ddaa_ddb5a525e26c4 +466a8cd519aa3_4030806100c20_04fa7bfe2d0ff +e145c28b85170_79a6f34de69bd_463dcb50a333e +7712ee25dc4bc_11fe23fc47f89_5e717eda9c6af +c16582cb05960_07400e801d004_b50505a13a5b5 +1ab235646ac8d_fa61f4c3e987d_1dd504f2f0368 +5de4bbc97792f_9bb7376e6edce_b31e8e55e8147 +89ab135626ac5_ad835b06b60d7_d545705a992ed +729ae535ca6b9_a4d549aa93552_c2e40a529c2e4 +a097412e825d0_246c48d891b12_6cb3b7bf0d0e9 +6138c27184e30_acbb5976b2ed6_a5d3075eecb95 +82f105e20bc42_c7cd8f9b1f364_b2a5ff7275f9d +71a0e341c6839_8f471e8e3d1c8_d9faee41e6a74 +ef25de4bbc978_8e1b1c36386c7_3e6702cb167cc +bfcb7f96ff2e0_8f211e423c848_1f36c17f3eef1 +bc237846f08de_c5618ac315862_f59002e4d6bb3 +2f0c5e18bc318_c21f843f087e1_58b51373fb0f2 +98833106620cc_c06980d301a60_d2713aca9d4c3 +3b007600ec01e_cd4d9a9b35366_5d9ec9147a36e +a31346268c4d2_1f7a3ef47de90_75303a546efb8 +fdd3fba7f74ff_685ed0bda17b4_6a2bfa733234a +f4f1e9e3d3c7a_ec8fd91fb23f6_045b60cb7b2c1 +441a8835106a2_a0a1414282850_8e4b2fc05342e +b52b6a56d4ada_430e861d0c3a2_5a6d2f75ea2ec +06360c6c18d83_537ea6fd4dfaa_8b725f9a935a5 +cdc79b8f371e7_baff75feebfde_0ada89325bc26 +1f283e507ca10_d86fb0df61bec_373473ff7df26 +da6db4db69b6d_4fc89f913f228_69b3c520810a1 +98df31be637cc_5272a4e549ca9_3544b130d610f +6870d0e1a1c34_fa5ff4bfe97fd_6c71d91640c2a +6618cc3198633_a107420e841d0_b7a5d5e42a035 +207440e881d10_b70b6e16dc2dc_5062d5f644fcf +e1bfc37f86ff1_68a2d145a28b4_55f914248f0a7 +f179e2f3c5e78_2e905d20ba417_a4ea676644e4b +ebb3d767aecf6_2aac5558aab15_a57339f8b3699 +d577aaef55dea_baf375e6ebcde_0f5330a82fae7 +fb2bf657ecafe_e4f3c9e793cf2_0bbab674dd52d +477a8ef51dea4_ffa9ff53fea80_47b19a381bdcf +fe91fd23fa480_30a06140c2818_ad11d6ba80c08 +033a06740ce82_cd539aa7354e6_1fb36b2345f50 +60cac195832b0_58bab17562eac_05fccc21b270f +262e4c5c98b93_88f911f223e44_7f48f044a5e64 +0c26184c30986_6016c02d805b0_85efa9a7d0a5a +4a24944928925_ceb99d733ae68_6d4ca188f4293 +c29f853f0a7e2_6ecedd9dbb3b8_3a7edf0e2a770 +b16162c2c5858_8809101220244_1aff9635dd376 +a3c347868f0d2_9f3d3e7a7cf50_02c9f15906ae4 +1c30386070c0e_2d665accb5997_e2c31f481b131 +38007000e001c_a27544ea89d51_7dbf15610f2ce +5ffcbff97ff30_6b96d72dae5b6_efa991f5db3b6 +d989b3136626d_34386870d0e1a_894efdc987e33 +57eeafdd5fbac_e457c8af915f2_6b925af68f63f +d2a1a5434a86a_d671ace359c6b_fbd9c10da491a +46fc8df91bf24_429c85390a721_0378c63d0435b +097612ec25d85_cc27984f309e6_275edddcd4014 +438a87150e2a2_5a40b4816902d_de6aa461cdeb7 +9187230e461c9_cbfd97fb2ff66_beed57afe43e0 +c47b88f711ee2_8b4916922d246_250aef27ed423 +fa61f4c3e987d_621ec43d887b1_6e12c61bb8624 +e7c9cf939f274_208e411c82390_b0c1304fa0676 +b415682ad055a_79c8f391e723d_2781522657272 +8aa5154a2a946_e203c407880f1_a331ece131ecf +60f4c1e983d30_062e0c5c18b83_58a2f250775f4 +cb0396072c0e6_926324c6498c9_2406ae2a77c4e +6d00da01b4036_430086010c022_2149ea4406c2f +0abe157c2af85_906b20d641ac8_5512d742e97ba +c2b5856b0ad62_845b08b6116c2_291a4e7cb6d93 +0c2a185430a86_5398a7314e62a_944ddc09deefa +f561eac3d587a_0e441c8839107_daeab959545b4 +402a805500aa0_fc5bf8b7f16fe_42757ecbcc920 +b9017202e405c_eba3d747ae8f6_cb44cce776023 +ddcdbb9b7736f_afc95f92bf258_1b486759ba44e +ff99ff33fe680_3cb07960f2c1e_9d8f517d4182e +db5fb6bf6d7ee_f6dfedbfdb7fc_e40008253a23b +940b2816502ca_f4fbe9f7d3efa_9ced8e44b2eae +610ac215842b0_d939b27364e6c_7df81d0b4c1b0 +8a6b14d629ac5_80d501aa03540_066083383d3e8 +cce999d333a66_eb41d683ad076_e05fc1db02106 +5de0bbc17782f_4a5094a129425_0f29690634d61 +e09fc13f827f0_07ee0fdc1fb84_d22ef40abafea +13f227e44fc8a_95b92b7256e4b_5c3a6d0379b29 +307060e0c1c18_ee01dc03b8077_3b86fa53edaf1 +3d667accf599f_ad895b12b6257_7a55e8bf0eea1 +6bdcd7b9af736_78a8f151e2a3c_ee9abe67da520 +2c9c5938b2716_d5e3abc7578eb_478d0ab1345f1 +97b32f665eccc_abd557aaaf556_e7e7e0b277aac +395a72b4e569d_ff85ff0bfe180_39a52fa6ba07d +d1afa35f46be9_4bd697ad2f5a6_67421e5a62571 +6a32d465a8cb5_b2496492c9259_ab0317189693f +b5896b12d625b_38ac7158e2b1c_663b2b3f68efe +5b50b6a16d42e_27164e2c9c594_2d4f5e6a69996 +fb97f72fee5fe_44a8895112a22_903f939334948 +bad775aeeb5de_095e12bc25785_ab359673dba45 +68e0d1c1a3834_beb17d62fac60_9da3811285f99 +32b46568cad19_d80fb01f603ec_4ca7458292601 +a8b35166a2cd4_67fccff99ff34_2e05089e02a23 +180030006000c_5e0cbc197832f_998af91a8749b +27be4f7c9ef94_0d421a8435087_192e59d97e37a +b7cd6f9adf35c_3a307460e8c1d_66595ce558b1d +88b3116622cc4_7b74f6e9edd3e_08ef20c4d5ae2 +99833306660cd_eeb7dd6fbadf8_a7d15ca74ef4d +ca47948f291e5_07f80ff01fe04_bc71ce01fc324 +8eb71d6e3adc8_703ce079c0f38_1530238b17fda +b6e16dc2db85c_6460c8c191832_3b43c4660793a +e885d10ba2174_ac35586ab0d56_240eed822904c +b5a96b52d6a5b_f5a1eb43d687b_beb509d81ae39 +aa6554caa9955_fee5fdcbfb980_ab50b21378e08 +95212a425484a_66cccd999b334_210e3e0ac2272 +128425084a109_10d821b043608_019196de0245c +673ace759ceb4_af455e8abd158_aa7932ef4a6dc +4fa29f453e8a8_13da27b44f68a_377b0e1fba654 +06ee0ddc1bb83_447c88f911f22_9edf0ad46a7c4 +bc6178c2f185e_d76daedb5db6c_e29fe28a29bcf +5f5cbeb97d730_af255e4abc958_a14116c826db1 +781af035e06bc_acc35986b30d6_c11e99bfd03bc +0c5c18b831706_3bec77d8efb1e_b2ea6e4bbabd9 +b5456a8ad515a_9235246a48d49_165148ad170c6 +6c92d925b24b6_ffb7ff6ffee00_6cc625698dab0 +95432a86550ca_9e3b3c7678ecf_f4ea00808ce93 +bd137a26f44de_e751cea39d474_d39df99f3f54f +e9bdd37ba6f75_21e443c887911_b07c30284ac9f +5670ace159c2b_0aac15582ab05_48bc5782c75df +b37566eacdd5a_7ad6f5adeb5be_26429593bab10 +a35746ae8d5d2_fb95f72bee57e_a6fcda06e545d +b6a76d4eda9dc_0cb4196832d06_a1ea6dd96dadb +e8a7d14fa29f4_47ec8fd91fb24_7d7a5e0facc23 +fcdbf9b7f36fe_5a26b44d689ad_785525038c357 +7702ee05dc0bc_e75dcebb9d774_89f75314eac99 +9c3f387e70fce_b54b6a96d52da_e2ac5fcab9b16 +5df8bbf177e2f_cc95992b32566_850a1665f81f7 +9c7b38f671ece_7faeff5dfebc0_1336deab6027b +388a7114e229c_5202a405480a9_d96b8ce030793 +5112a225444a8_71c8e391c7239_d2b5183c88cc1 +2b485690ad216_ba017402e805d_5aad01f0f330a +0130026004c01_e1edc3db87b71_113c45ac1389f +abf757eeafdd6_7a9af535ea6bd_21604b0e84524 +350c6a18d431a_82c905920b242_9918ede81ed1a +2a8c5518aa315_8cbf197e32fc6_8146816fcd820 +80b3016602cc0_915922b245648_eac2cca581d9f diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv new file mode 100644 index 000000000..9e8a35167 --- /dev/null +++ b/pipelined/testbench/testbench-fp.sv @@ -0,0 +1,1561 @@ + +`include "wally-config.vh" +`include "tests-fp.vh" + +// steps to run FMA Tests +// 1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh +// 2) go to riscv-wally/pipelined/testbench/fp/Tests +// 3) run ./sim-fma-batch +module testbenchfp; + parameter TEST="none"; + + string Tests[]; // list of tests to be run + string FmaRneTests[]; // list of FMA round to nearest even tests to run + string FmaRuTests[]; // list of FMA round up tests to run + string FmaRdTests[]; // list of FMA round down tests to run + string FmaRzTests[]; // list of FMA round twords zero + string FmaRnmTests[]; // list of FMA round to nearest max magnitude + logic [2:0] OpCtrl[]; // list of op controls + logic [2:0] Unit[]; // list of units being tested + logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100 + logic [1:0] Fmt[]; // list of formats for the other units + logic [1:0] FmaFmt[]; // list of formats for the FMA + + + logic clk=0; + logic [31:0] TestNum=0; // index for the test + logic [31:0] OpCtrlNum=0; // index for OpCtrl + logic [31:0] errors=0; // how many errors + logic [31:0] VectorNum=0; // index for test vector + logic [31:0] FrmNum=0; // index for rounding mode + logic [`FLEN*4+7:0] TestVectors[46464:0]; // list of test vectors + logic [`FLEN*4+7:0] FmaRneVectors[6133248:0]; // list of fma rne test vectors + logic [`FLEN*4+7:0] FmaRuVectors[6133248:0]; // list of fma ru test vectors + logic [`FLEN*4+7:0] FmaRdVectors[6133248:0]; // list of fma rd test vectors + logic [`FLEN*4+7:0] FmaRzVectors[6133248:0]; // list of fma rz test vectors + logic [`FLEN*4+7:0] FmaRnmVectors[6133248:0]; // list of fma rnm test vectors + + logic [1:0] FmaFmtVal, FmtVal; // value of the current Fmt + logic [2:0] UnitVal, OpCtrlVal, FrmVal; // vlaue of the currnet Unit/OpCtrl/FrmVal + logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRneX, FmaRneY, FmaRneZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRzX, FmaRzY, FmaRzZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRuX, FmaRuY, FmaRuZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRdX, FmaRdY, FmaRdZ; // inputs read from TestFloat + logic [`FLEN-1:0] FmaRnmX, FmaRnmY, FmaRnmZ; // inputs read from TestFloat + logic [`XLEN-1:0] SrcA; // integer input + logic [`FLEN-1:0] Ans; // correct answer from TestFloat + logic [`FLEN-1:0] FmaRneAns, FmaRzAns, FmaRuAns, FmaRdAns, FmaRnmAns; // flags read form testfloat + logic [`FLEN-1:0] Res; // result from other units + logic [`FLEN-1:0] FmaRneRes, FmaRzRes, FmaRuRes, FmaRdRes, FmaRnmRes; // results from FMA + logic [4:0] AnsFlg; // correct flags read from testfloat + logic [4:0] FmaRneAnsFlg, FmaRzAnsFlg, FmaRuAnsFlg, FmaRdAnsFlg, FmaRnmAnsFlg; // flags read form testfloat + logic [4:0] ResFlg; // Result flags + logic [4:0] FmaRneResFlg, FmaRzResFlg, FmaRuResFlg, FmaRdResFlg, FmaRnmResFlg; // flags read form testfloat + logic [`FPSIZES/3:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad + logic [`FLEN-1:0] FmaRes, DivRes, CmpRes, CvtRes, CvtFpRes; // Results from each unit + logic [4:0] FmaFlg, CvtFpFlg, DivFlg, CvtIntFlg, CmpFlg; // Outputed flags + logic ResNaN, FmaRneResNaN, FmaRzResNaN, FmaRuResNaN, FmaRdResNaN, FmaRnmResNaN; // is the outputed result NaN + logic AnsNaN, FmaRneAnsNaN, FmaRzAnsNaN, FmaRuAnsNaN, FmaRdAnsNaN, FmaRnmAnsNaN; // is the correct answer NaN + logic NaNGood, FmaRneNaNGood, FmaRzNaNGood, FmaRuNaNGood, FmaRdNaNGood, FmaRnmNaNGood; // is the NaN answer correct + logic XSgn, YSgn, ZSgn; // sign of the inputs + logic FmaRneXSgn, FmaRneYSgn, FmaRneZSgn; + logic FmaRzXSgn, FmaRzYSgn, FmaRzZSgn; + logic FmaRuXSgn, FmaRuYSgn, FmaRuZSgn; + logic FmaRdXSgn, FmaRdYSgn, FmaRdZSgn; + logic FmaRnmXSgn, FmaRnmYSgn, FmaRnmZSgn; + logic [`NE-1:0] XExp, YExp, ZExp; // exponent of the inputs + logic [`NE-1:0] FmaRneXExp, FmaRneYExp, FmaRneZExp; + logic [`NE-1:0] FmaRzXExp, FmaRzYExp, FmaRzZExp; + logic [`NE-1:0] FmaRuXExp, FmaRuYExp, FmaRuZExp; + logic [`NE-1:0] FmaRdXExp, FmaRdYExp, FmaRdZExp; + logic [`NE-1:0] FmaRnmXExp, FmaRnmYExp, FmaRnmZExp; + logic [`NF:0] XMan, YMan, ZMan; // mantissas of the inputs + logic [`NF:0] FmaRneXMan, FmaRneYMan, FmaRneZMan; + logic [`NF:0] FmaRzXMan, FmaRzYMan, FmaRzZMan; + logic [`NF:0] FmaRuXMan, FmaRuYMan, FmaRuZMan; + logic [`NF:0] FmaRdXMan, FmaRdYMan, FmaRdZMan; + logic [`NF:0] FmaRnmXMan, FmaRnmYMan, FmaRnmZMan; + logic XNorm; // is X normal + logic XNaN, YNaN, ZNaN; // is the input NaN + logic FmaRneXNaN, FmaRneYNaN, FmaRneZNaN; + logic FmaRzXNaN, FmaRzYNaN, FmaRzZNaN; + logic FmaRuXNaN, FmaRuYNaN, FmaRuZNaN; + logic FmaRdXNaN, FmaRdYNaN, FmaRdZNaN; + logic FmaRnmXNaN, FmaRnmYNaN, FmaRnmZNaN; + logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN + logic FmaRneXSNaN, FmaRneYSNaN, FmaRneZSNaN; + logic FmaRzXSNaN, FmaRzYSNaN, FmaRzZSNaN; + logic FmaRuXSNaN, FmaRuYSNaN, FmaRuZSNaN; + logic FmaRdXSNaN, FmaRdYSNaN, FmaRdZSNaN; + logic FmaRnmXSNaN, FmaRnmYSNaN, FmaRnmZSNaN; + logic XDenorm, YDenorm, ZDenorm; // is the input denormalized + logic FmaRneXDenorm, FmaRneYDenorm, FmaRneZDenorm; + logic FmaRzXDenorm, FmaRzYDenorm, FmaRzZDenorm; + logic FmaRuXDenorm, FmaRuYDenorm, FmaRuZDenorm; + logic FmaRdXDenorm, FmaRdYDenorm, FmaRdZDenorm; + logic FmaRnmXDenorm, FmaRnmYDenorm, FmaRnmZDenorm; + logic XInf, YInf, ZInf; // is the input infinity + logic FmaRneXInf, FmaRneYInf, FmaRneZInf; + logic FmaRzXInf, FmaRzYInf, FmaRzZInf; + logic FmaRuXInf, FmaRuYInf, FmaRuZInf; + logic FmaRdXInf, FmaRdYInf, FmaRdZInf; + logic FmaRnmXInf, FmaRnmYInf, FmaRnmZInf; + logic XZero, YZero, ZZero; // is the input zero + logic FmaRneXZero, FmaRneYZero, FmaRneZZero; + logic FmaRzXZero, FmaRzYZero, FmaRzZZero; + logic FmaRuXZero, FmaRuYZero, FmaRuZZero; + logic FmaRdXZero, FmaRdYZero, FmaRdZZero; + logic FmaRnmXZero, FmaRnmYZero, FmaRnmZZero; + logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones + logic ZOrigDenorm, FmaRneZOrigDenorm, FmaRzZOrigDenorm, FmaRuZOrigDenorm, FmaRdZOrigDenorm, FmaRnmZOrigDenorm; // is the original precision dnormalized + + // in-between FMA signals + logic Mult; + logic [`NE+1:0] ProdExpE, FmaRneProdExp, FmaRzProdExp, FmaRuProdExp, FmaRdProdExp, FmaRnmProdExp; + logic AddendStickyE, FmaRneAddendSticky, FmaRzAddendSticky, FmaRuAddendSticky, FmaRdAddendSticky, FmaRnmAddendSticky; + logic KillProdE, FmaRneKillProd, FmaRzKillProd, FmaRuKillProd, FmaRdKillProd, FmaRnmKillProd; + logic [$clog2(3*`NF+7)-1:0] NormCntE, FmaRneNormCnt, FmaRzNormCnt, FmaRuNormCnt, FmaRdNormCnt, FmaRnmNormCnt; + logic [3*`NF+5:0] SumE, FmaRneSum, FmaRzSum, FmaRuSum, FmaRdSum, FmaRnmSum; + logic InvZE, FmaRneInvZ, FmaRzInvZ, FmaRuInvZ, FmaRdInvZ, FmaRnmInvZ; + logic NegSumE, FmaRneNegSum, FmaRzNegSum, FmaRuNegSum, FmaRdNegSum, FmaRnmNegSum; + logic ZSgnEffE, FmaRneZSgnEff, FmaRzZSgnEff, FmaRuZSgnEff, FmaRdZSgnEff, FmaRnmZSgnEff; + logic PSgnE, FmaRnePSgn, FmaRzPSgn, FmaRuPSgn, FmaRdPSgn, FmaRnmPSgn; + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||| ||||||| ||| ||||||| |||||||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||| ||||||| ||| ||||||| |||||||| ||||||||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // select tests relevent to the specified configuration + // cvtint - test integer conversion unit (fcvtint) + // cvtfp - test floating-point conversion unit (fcvtfp) + // cmp - test comparison unit's LT, LE, EQ opperations (fcmp) + // add - test addition + // sub - test subtraction + // div - test division + // sqrt - test square root + // all - test all of the above + initial begin + $display("TEST is %s", TEST); + if (`Q_SUPPORTED) begin // if Quad percision is supported + if (TEST === "cvtint"| TEST === "all") begin // if testing integer conversion + // add the 128-bit cvtint tests to the to-be-tested list + Tests = {Tests, f128rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b11}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions + Tests = {Tests, f128rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if the floating-point conversions are being tested + if(`D_SUPPORTED) begin // if double precision is supported + // add the 128 <-> 64 bit conversions to the to-be-tested list + Tests = {Tests, f128f64cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b01, 3'b11}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if(`F_SUPPORTED) begin // if single precision is supported + // add the 128 <-> 32 bit conversions to the to-be-tested list + Tests = {Tests, f128f32cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b00, 3'b11}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if(`ZFH_SUPPORTED) begin // if half precision is supported + // add the 128 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f128f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b11}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested + // add the compare tests/op-ctrls/unit/fmt + Tests = {Tests, f128cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the addition tests/op-ctrls/unit/fmt + Tests = {Tests, f128add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + // add the subtraction tests/op-ctrls/unit/fmt + Tests = {Tests, f128sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the multiply tests/op-ctrls/unit/fmt + Tests = {Tests, f128mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the divide tests/op-ctrls/unit/fmt + Tests = {Tests, f128div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested + // add the square-root tests/op-ctrls/unit/fmt + Tests = {Tests, f128sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested + // add each rounding mode to it's own list of tests + // - fma tests are very long, so run all rounding modes in parallel + FmaRneTests = {FmaRneTests, "f128_mulAdd_rne.tv"}; + FmaRzTests = {FmaRzTests, "f128_mulAdd_rz.tv"}; + FmaRuTests = {FmaRuTests, "f128_mulAdd_ru.tv"}; + FmaRdTests = {FmaRdTests, "f128_mulAdd_rd.tv"}; + FmaRnmTests = {FmaRnmTests, "f128_mulAdd_rnm.tv"}; + // add the format for the Fma + for(int i = 0; i<5; i++) begin + FmaFmt = {FmaFmt, 2'b11}; + end + end + end + if (`D_SUPPORTED) begin // if double precision is supported + if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested + Tests = {Tests, f64rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b01}; + end + if (`XLEN == 64) begin // if 64-bit integers are being supported + Tests = {Tests, f64rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested + if(`F_SUPPORTED) begin // if single precision is supported + // add the 64 <-> 32 bit conversions to the to-be-tested list + Tests = {Tests, f64f32cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b00, 3'b01}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if(`ZFH_SUPPORTED) begin // if half precision is supported + // add the 64 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f64f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b01}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested + // add each rounding mode to it's own list of tests + // - fma tests are very long, so run all rounding modes in parallel + FmaRneTests = {FmaRneTests, "f64_mulAdd_rne.tv"}; + FmaRzTests = {FmaRzTests, "f64_mulAdd_rz.tv"}; + FmaRuTests = {FmaRuTests, "f64_mulAdd_ru.tv"}; + FmaRdTests = {FmaRdTests, "f64_mulAdd_rd.tv"}; + FmaRnmTests = {FmaRnmTests, "f64_mulAdd_rnm.tv"}; + for(int i = 0; i<5; i++) begin + FmaFmt = {FmaFmt, 2'b01}; + end + end + end + if (`F_SUPPORTED) begin // if single precision being supported + if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested + Tests = {Tests, f32rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b00}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported + Tests = {Tests, f32rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested + if(`ZFH_SUPPORTED) begin + // add the 32 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f32f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b00}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<10; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiply is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested + // add each rounding mode to it's own list of tests + // - fma tests are very long, so run all rounding modes in parallel + FmaRneTests = {FmaRneTests, "f32_mulAdd_rne.tv"}; + // FmaRzTests = {FmaRzTests, "f32_mulAdd_rz.tv"}; + // FmaRuTests = {FmaRuTests, "f32_mulAdd_ru.tv"}; + // FmaRdTests = {FmaRdTests, "f32_mulAdd_rd.tv"}; + // FmaRnmTests = {FmaRnmTests, "f32_mulAdd_rnm.tv"}; + // for(int i = 0; i<5; i++) begin + FmaFmt = {FmaFmt, 2'b00}; + // end + end + end + if (`ZFH_SUPPORTED) begin // if half precision supported + if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested + Tests = {Tests, f16rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported + Tests = {Tests, f16rv64cvtint, f16rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested + // add each rounding mode to it's own list of tests + // - fma tests are very long, so run all rounding modes in parallel + FmaRneTests = {FmaRneTests, "f16_mulAdd_rne.tv"}; + // FmaRzTests = {FmaRzTests, "f16_mulAdd_rz.tv"}; + // FmaRuTests = {FmaRuTests, "f16_mulAdd_ru.tv"}; + // FmaRdTests = {FmaRdTests, "f16_mulAdd_rd.tv"}; + // FmaRnmTests = {FmaRnmTests, "f16_mulAdd_rnm.tv"}; + // for(int i = 0; i<5; i++) begin + FmaFmt = {FmaFmt, 2'b10}; + // end + end + end + + // check if nothing is being tested + if (Tests.size() == 0 & FmaRneTests.size() == 0 & FmaRuTests.size() == 0 & FmaRdTests.size() == 0 & FmaRzTests.size() == 0 & FmaRnmTests.size() == 0) begin + $display("TEST %s not supported in this configuration", TEST); + $stop; + end + end + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||||| |||||||| ||||||||| ||||||| ||||||||| |||||||| ||||||| ||||||||| + // ||| ||| ||| ||| ||| || || ||| ||| ||| ||| + // |||||||| |||||||| ||||||||| || || ||| |||||||| ||||||| ||| + // ||| || ||| ||| ||| || || ||| ||| ||| ||| + // ||| ||| |||||||| ||| ||| ||||||| ||| |||||||| ||||||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // Read the first test + initial begin + $display("\n\nRunning %s vectors", Tests[TestNum]); + $readmemh({`PATH, Tests[TestNum]}, TestVectors); + $readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors); + $readmemh({`PATH, FmaRuTests[TestNum]}, FmaRuVectors); + $readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors); + $readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors); + $readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors); + // set the test index to 0 + TestNum = 0; + end + + // set a the signals for all tests + always_comb FmaFmtVal = FmaFmt[TestNum]; + always_comb UnitVal = Unit[TestNum]; + always_comb FmtVal = Fmt[TestNum]; + always_comb OpCtrlVal = OpCtrl[OpCtrlNum]; + always_comb FrmVal = Frm[FrmNum]; + assign Mult = OpCtrlVal === 3'b100; + + // modify the format signal if only 2 percisions supported + // - 1 for the larger precision + // - 0 for the smaller precision + always_comb begin + if(`FPSIZES/3 === 1) ModFmt = FmtVal; + else ModFmt = FmtVal === `FMT; + if(`FPSIZES/3 === 1) FmaModFmt = FmaFmtVal; + else FmaModFmt = FmaFmtVal === `FMT; + end + + // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector + readfmavectors readfmarnevectors (.clk, .TestVector(FmaRneVectors[VectorNum]), .Ans(FmaRneAns), .AnsFlg(FmaRneAnsFlg), + .XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn), + .XExpE(FmaRneXExp), .YExpE(FmaRneYExp), .ZExpE(FmaRneZExp), + .XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan), + .XNaNE(FmaRneXNaN), .YNaNE(FmaRneYNaN), .ZNaNE(FmaRneZNaN), .ZOrigDenormE(FmaRneZOrigDenorm), + .XSNaNE(FmaRneXSNaN), .YSNaNE(FmaRneYSNaN), .ZSNaNE(FmaRneZSNaN), + .XDenormE(FmaRneXDenorm), .YDenormE(FmaRneYDenorm), .ZDenormE(FmaRneZDenorm), + .XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero), + .XInfE(FmaRneXInf), .YInfE(FmaRneYInf), .ZInfE(FmaRneZInf), .FmaModFmt, .FmaFmt(FmaFmtVal), + .X(FmaRneX), .Y(FmaRneY), .Z(FmaRneZ)); + readfmavectors readfmarzvectors (.clk, .TestVector(FmaRzVectors[VectorNum]), .Ans(FmaRzAns), .AnsFlg(FmaRzAnsFlg), + .XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), .FmaModFmt, + .XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp), + .XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan), + .XNaNE(FmaRzXNaN), .YNaNE(FmaRzYNaN), .ZNaNE(FmaRzZNaN), .ZOrigDenormE(FmaRzZOrigDenorm), + .XSNaNE(FmaRzXSNaN), .YSNaNE(FmaRzYSNaN), .ZSNaNE(FmaRzZSNaN), + .XDenormE(FmaRzXDenorm), .YDenormE(FmaRzYDenorm), .ZDenormE(FmaRzZDenorm), + .XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero), + .XInfE(FmaRzXInf), .YInfE(FmaRzYInf), .ZInfE(FmaRzZInf), .FmaFmt(FmaFmtVal), + .X(FmaRzX), .Y(FmaRzY), .Z(FmaRzZ)); + readfmavectors readfmaruvectors (.clk, .TestVector(FmaRuVectors[VectorNum]), .Ans(FmaRuAns), .AnsFlg(FmaRuAnsFlg), + .XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), .FmaModFmt, + .XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp), + .XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan), + .XNaNE(FmaRuXNaN), .YNaNE(FmaRuYNaN), .ZNaNE(FmaRuZNaN), .ZOrigDenormE(FmaRuZOrigDenorm), + .XSNaNE(FmaRuXSNaN), .YSNaNE(FmaRuYSNaN), .ZSNaNE(FmaRuZSNaN), + .XDenormE(FmaRuXDenorm), .YDenormE(FmaRuYDenorm), .ZDenormE(FmaRuZDenorm), + .XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero), + .XInfE(FmaRuXInf), .YInfE(FmaRuYInf), .ZInfE(FmaRuZInf), .FmaFmt(FmaFmtVal), + .X(FmaRuX), .Y(FmaRuY), .Z(FmaRuZ)); + readfmavectors readfmardvectors (.clk, .TestVector(FmaRdVectors[VectorNum]), .Ans(FmaRdAns), .AnsFlg(FmaRdAnsFlg), + .XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), .FmaModFmt, + .XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp), + .XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan), + .XNaNE(FmaRdXNaN), .YNaNE(FmaRdYNaN), .ZNaNE(FmaRdZNaN), .ZOrigDenormE(FmaRdZOrigDenorm), + .XSNaNE(FmaRdXSNaN), .YSNaNE(FmaRdYSNaN), .ZSNaNE(FmaRdZSNaN), + .XDenormE(FmaRdXDenorm), .YDenormE(FmaRdYDenorm), .ZDenormE(FmaRdZDenorm), + .XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero), + .XInfE(FmaRdXInf), .YInfE(FmaRdYInf), .ZInfE(FmaRdZInf), .FmaFmt(FmaFmtVal), + .X(FmaRdX), .Y(FmaRdY), .Z(FmaRdZ)); + readfmavectors readfmarnmvectors (.clk, .TestVector(FmaRnmVectors[VectorNum]), .Ans(FmaRnmAns), .AnsFlg(FmaRnmAnsFlg), + .XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), .FmaModFmt, + .XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp), + .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), .ZOrigDenormE(FmaRnmZOrigDenorm), + .XNaNE(FmaRnmXNaN), .YNaNE(FmaRnmYNaN), .ZNaNE(FmaRnmZNaN), + .XSNaNE(FmaRnmXSNaN), .YSNaNE(FmaRnmYSNaN), .ZSNaNE(FmaRnmZSNaN), + .XDenormE(FmaRnmXDenorm), .YDenormE(FmaRnmYDenorm), .ZDenormE(FmaRnmZDenorm), + .XZeroE(FmaRnmXZero), .YZeroE(FmaRnmYZero), .ZZeroE(FmaRnmZZero), + .XInfE(FmaRnmXInf), .YInfE(FmaRnmYInf), .ZInfE(FmaRnmZInf), .FmaFmt(FmaFmtVal), + .X(FmaRnmX), .Y(FmaRnmY), .Z(FmaRnmZ)); + readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, + .XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), .Unit (UnitVal), + .XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), .TestNum, .OpCtrl(OpCtrlVal), + .XManE(XMan), .YManE(YMan), .ZManE(ZMan), .ZOrigDenormE(ZOrigDenorm), + .XNaNE(XNaN), .YNaNE(YNaN), .ZNaNE(ZNaN), + .XSNaNE(XSNaN), .YSNaNE(YSNaN), .ZSNaNE(ZSNaN), + .XDenormE(XDenorm), .YDenormE(YDenorm), .ZDenormE(ZDenorm), + .XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero), + .XInfE(XInf), .YInfE(YInf), .ZInfE(ZInf),.XNormE(XNorm), .XExpMaxE(XExpMax), + .X, .Y, .Z); + + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||| ||| ||| ||||||||| + // ||| ||| ||| ||| ||| + // ||| ||| ||| ||| ||| + // ||| ||| ||| ||| ||| + // ||||||| ||||||||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // instantiate devices under test + // - one fma for each precison + // - all the units for the other tests (including fma for add/sub/mul) + fma1 fma1rne(.XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn), + .XExpE(FmaRneXExp), .YExpE(FmaRneYExp), .ZExpE(FmaRneZExp), + .XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan), + .XDenormE(FmaRneXDenorm), .YDenormE(FmaRneYDenorm), .ZDenormE(FmaRneZDenorm), + .XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRneSum), .NegSumE(FmaRneNegSum), .InvZE(FmaRneInvZ), + .NormCntE(FmaRneNormCnt), .ZSgnEffE(FmaRneZSgnEff), .PSgnE(FmaRnePSgn), + .ProdExpE(FmaRneProdExp), .AddendStickyE(FmaRneAddendSticky), .KillProdE(FmaRneSumKillProd)); + fma2 fma2rne(.XSgnM(FmaRneXSgn), .YSgnM(FmaRneYSgn), + .ZExpM(FmaRneZExp), .ZOrigDenormM(FmaRneZOrigDenorm), + .XManM(FmaRneXMan), .YManM(FmaRneYMan), .ZManM(FmaRneZMan), + .XNaNM(FmaRneXNaN), .YNaNM(FmaRneYNaN), .ZNaNM(FmaRneZNaN), + .XZeroM(FmaRneXZero), .YZeroM(FmaRneYZero), .ZZeroM(FmaRneZZero), + .XInfM(FmaRneXInf), .YInfM(FmaRneYInf), .ZInfM(FmaRneZInf), + .XSNaNM(FmaRneXSNaN), .YSNaNM(FmaRneYSNaN), .ZSNaNM(FmaRneZSNaN), + .KillProdM(FmaRneSumKillProd), .AddendStickyM(FmaRneAddendSticky), .ProdExpM(FmaRneProdExp), + .SumM((FmaRneSum)), .NegSumM(FmaRneNegSum), .InvZM(FmaRneInvZ), .NormCntM(FmaRneNormCnt), .ZSgnEffM(FmaRneZSgnEff), + .PSgnM(FmaRnePSgn), .FmtM(FmaModFmt), .FrmM(`RNE), + .FMAFlgM(FmaRneResFlg), .FMAResM(FmaRneRes), .Mult(1'b0)); + fma1 fma1rz(.XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), + .XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp), + .XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan), + .XDenormE(FmaRzXDenorm), .YDenormE(FmaRzYDenorm), .ZDenormE(FmaRzZDenorm), + .XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRzSum), .NegSumE(FmaRzNegSum), .InvZE(FmaRzInvZ), + .NormCntE(FmaRzNormCnt), .ZSgnEffE(FmaRzZSgnEff), .PSgnE(FmaRzPSgn), + .ProdExpE(FmaRzProdExp), .AddendStickyE(FmaRzAddendSticky), .KillProdE(FmaRzSumKillProd)); + fma2 fma2rz(.XSgnM(FmaRzXSgn), .YSgnM(FmaRzYSgn), + .ZExpM(FmaRzZExp), .ZOrigDenormM(FmaRzZOrigDenorm), + .XManM(FmaRzXMan), .YManM(FmaRzYMan), .ZManM(FmaRzZMan), + .XNaNM(FmaRzXNaN), .YNaNM(FmaRzYNaN), .ZNaNM(FmaRzZNaN), + .XZeroM(FmaRzXZero), .YZeroM(FmaRzYZero), .ZZeroM(FmaRzZZero), + .XInfM(FmaRzXInf), .YInfM(FmaRzYInf), .ZInfM(FmaRzZInf), + .XSNaNM(FmaRzXSNaN), .YSNaNM(FmaRzYSNaN), .ZSNaNM(FmaRzZSNaN), + .KillProdM(FmaRzSumKillProd), .AddendStickyM(FmaRzAddendSticky), .ProdExpM(FmaRzProdExp), + .SumM((FmaRzSum)), .NegSumM(FmaRzNegSum), .InvZM(FmaRzInvZ), .NormCntM(FmaRzNormCnt), .ZSgnEffM(FmaRzZSgnEff), + .PSgnM(FmaRzPSgn), .FmtM(FmaModFmt), .FrmM(`RZ), + .FMAFlgM(FmaRzResFlg), .FMAResM(FmaRzRes), .Mult(1'b0)); + fma1 fma1ru(.XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), + .XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp), + .XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan), + .XDenormE(FmaRuXDenorm), .YDenormE(FmaRuYDenorm), .ZDenormE(FmaRuZDenorm), + .XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRuSum), .NegSumE(FmaRuNegSum), .InvZE(FmaRuInvZ), + .NormCntE(FmaRuNormCnt), .ZSgnEffE(FmaRuZSgnEff), .PSgnE(FmaRuPSgn), + .ProdExpE(FmaRuProdExp), .AddendStickyE(FmaRuAddendSticky), .KillProdE(FmaRuSumKillProd)); + fma2 fma2ru(.XSgnM(FmaRuXSgn), .YSgnM(FmaRuYSgn), + .ZExpM(FmaRuZExp), .ZOrigDenormM(FmaRuZOrigDenorm), + .XManM(FmaRuXMan), .YManM(FmaRuYMan), .ZManM(FmaRuZMan), + .XNaNM(FmaRuXNaN), .YNaNM(FmaRuYNaN), .ZNaNM(FmaRuZNaN), + .XZeroM(FmaRuXZero), .YZeroM(FmaRuYZero), .ZZeroM(FmaRuZZero), + .XInfM(FmaRuXInf), .YInfM(FmaRuYInf), .ZInfM(FmaRuZInf), + .XSNaNM(FmaRuXSNaN), .YSNaNM(FmaRuYSNaN), .ZSNaNM(FmaRuZSNaN), + .KillProdM(FmaRuSumKillProd), .AddendStickyM(FmaRuAddendSticky), .ProdExpM(FmaRuProdExp), + .SumM((FmaRuSum)), .NegSumM(FmaRuNegSum), .InvZM(FmaRuInvZ), .NormCntM(FmaRuNormCnt), .ZSgnEffM(FmaRuZSgnEff), + .PSgnM(FmaRuPSgn), .FmtM(FmaModFmt), .FrmM(`RU), + .FMAFlgM(FmaRuResFlg), .FMAResM(FmaRuRes), .Mult(1'b0)); + fma1 fma1rd(.XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), + .XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp), + .XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan), + .XDenormE(FmaRdXDenorm), .YDenormE(FmaRdYDenorm), .ZDenormE(FmaRdZDenorm), + .XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRdSum), .NegSumE(FmaRdNegSum), .InvZE(FmaRdInvZ), + .NormCntE(FmaRdNormCnt), .ZSgnEffE(FmaRdZSgnEff), .PSgnE(FmaRdPSgn), + .ProdExpE(FmaRdProdExp), .AddendStickyE(FmaRdAddendSticky), .KillProdE(FmaRdSumKillProd)); + fma2 fma2rd(.XSgnM(FmaRdXSgn), .YSgnM(FmaRdYSgn), + .ZExpM(FmaRdZExp), .ZOrigDenormM(FmaRdZOrigDenorm), + .XManM(FmaRdXMan), .YManM(FmaRdYMan), .ZManM(FmaRdZMan), + .XNaNM(FmaRdXNaN), .YNaNM(FmaRdYNaN), .ZNaNM(FmaRdZNaN), + .XZeroM(FmaRdXZero), .YZeroM(FmaRdYZero), .ZZeroM(FmaRdZZero), + .XInfM(FmaRdXInf), .YInfM(FmaRdYInf), .ZInfM(FmaRdZInf), + .XSNaNM(FmaRdXSNaN), .YSNaNM(FmaRdYSNaN), .ZSNaNM(FmaRdZSNaN), + .KillProdM(FmaRdSumKillProd), .AddendStickyM(FmaRdAddendSticky), .ProdExpM(FmaRdProdExp), + .SumM((FmaRdSum)), .NegSumM(FmaRdNegSum), .InvZM(FmaRdInvZ), .NormCntM(FmaRdNormCnt), .ZSgnEffM(FmaRdZSgnEff), + .PSgnM(FmaRdPSgn), .FmtM(FmaModFmt), .FrmM(`RD), + .FMAFlgM(FmaRdResFlg), .FMAResM(FmaRdRes), .Mult(1'b0)); + fma1 fma1rnm(.XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), + .XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp), + .XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan), + .XDenormE(FmaRnmXDenorm), .YDenormE(FmaRnmYDenorm), .ZDenormE(FmaRnmZDenorm), + .XZeroE(FmaRnmXZero), .YZeroE(FmaRnmYZero), .ZZeroE(FmaRnmZZero), + .FOpCtrlE(3'b0), .FmtE(FmaModFmt), .SumE(FmaRnmSum), .NegSumE(FmaRnmNegSum), .InvZE(FmaRnmInvZ), + .NormCntE(FmaRnmNormCnt), .ZSgnEffE(FmaRnmZSgnEff), .PSgnE(FmaRnmPSgn), + .ProdExpE(FmaRnmProdExp), .AddendStickyE(FmaRnmAddendSticky), .KillProdE(FmaRnmSumKillProd)); + fma2 fma2rnm(.XSgnM(FmaRnmXSgn), .YSgnM(FmaRnmYSgn), + .ZExpM(FmaRnmZExp), .ZOrigDenormM(FmaRnmZOrigDenorm), + .XManM(FmaRnmXMan), .YManM(FmaRnmYMan), .ZManM(FmaRnmZMan), + .XNaNM(FmaRnmXNaN), .YNaNM(FmaRnmYNaN), .ZNaNM(FmaRnmZNaN), + .XZeroM(FmaRnmXZero), .YZeroM(FmaRnmYZero), .ZZeroM(FmaRnmZZero), + .XInfM(FmaRnmXInf), .YInfM(FmaRnmYInf), .ZInfM(FmaRnmZInf), + .XSNaNM(FmaRnmXSNaN), .YSNaNM(FmaRnmYSNaN), .ZSNaNM(FmaRnmZSNaN), + .KillProdM(FmaRnmSumKillProd), .AddendStickyM(FmaRnmAddendSticky), .ProdExpM(FmaRnmProdExp), + .SumM((FmaRnmSum)), .NegSumM(FmaRnmNegSum), .InvZM(FmaRnmInvZ), .NormCntM(FmaRnmNormCnt), .ZSgnEffM(FmaRnmZSgnEff), + .PSgnM(FmaRnmPSgn), .FmtM(FmaModFmt), .FrmM(`RNM), + .FMAFlgM(FmaRnmResFlg), .FMAResM(FmaRnmRes), .Mult(1'b0)); + fma1 fma1(.XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), + .XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), + .XManE(XMan), .YManE(YMan), .ZManE(ZMan), + .XDenormE(XDenorm), .YDenormE(YDenorm), .ZDenormE(ZDenorm), + .XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero), + .FOpCtrlE(OpCtrlVal), .FmtE(ModFmt), .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, + .ProdExpE, .AddendStickyE, .KillProdE); + fma2 fma2(.XSgnM(XSgn), .YSgnM(YSgn), + .ZExpM(ZExp), .ZOrigDenormM(ZOrigDenorm), + .XManM(XMan), .YManM(YMan), .ZManM(ZMan), + .XNaNM(XNaN), .YNaNM(YNaN), .ZNaNM(ZNaN), + .XZeroM(XZero), .YZeroM(YZero), .ZZeroM(ZZero), + .XInfM(XInf), .YInfM(YInf), .ZInfM(ZInf), + .XSNaNM(XSNaN), .YSNaNM(YSNaN), .ZSNaNM(ZSNaN), + .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), + .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(ModFmt), .FrmM(FrmVal), + .FMAFlgM(FmaFlg), .FMAResM(FmaRes), .Mult); + // fcvtfp fcvtfp (.XExpE(XExp), .XManE(XMan), .XSgnE(XSgn), .XZeroE(XZero), .XDenormE(XDenorm), .XInfE(XInf), + // .XNaNE(XNaN), .XSNaNE(XSNaN), .FrmE(Frmal), .FmtE(ModFmt), .CvtFpRes, .CvtFpFlgE); + fcmp fcmp (.FmtE(ModFmt), .FOpCtrlE(OpCtrlVal), .XSgnE(XSgn), .YSgnE(YSgn), .XExpE(XExp), .YExpE(YExp), + .XManE(XMan), .YManE(YMan), .XZeroE(XZero), .YZeroE(YZero), + .XNaNE(XNaN), .YNaNE(YNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .FSrcXE(X), .FSrcYE(Y), .CmpNVE(CmpFlg[4]), .CmpResE(CmpRes)); + // fcvtint fcvtint (.XSgnE(XSgn), .XExpE(XExp), .XManE(XMan), .XZeroE(XZero), .XNaNE(XNaN), .XInfE(XInf), + // .XDenormE(XDenorm), .ForwardedSrcAE(SrcA), .FOpCtrlE, .FmtE(ModFmt), .FrmE(Frmal), + // .CvtRes, .CvtFlgE); + // *** integrade divide and squareroot + // fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmVal[1:0]), .op_type(FOpCtrlQ), + // .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1), + // .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload, + // .FDivBusyE, .done(FDivSqrtDoneE), .AS_Res(FDivRes), .Flg(FDivFlg)); + + assign CmpFlg[3:0] = 0; + + // produce clock + always begin + clk = 1; #5; clk = 0; #5; + end + +/////////////////////////////////////////////////////////////////////////////////////////////// + +// ||||| ||| |||||||||| ||||| ||| +// ||||||| ||| ||| ||| ||||||| ||| +// |||| ||| ||| |||||||||| |||| ||| ||| +// |||| ||| ||| ||| ||| |||| ||| ||| +// |||| ||| ||| ||| ||| |||| ||| ||| +// |||| |||||| ||| ||| |||| |||||| + +/////////////////////////////////////////////////////////////////////////////////////////////// + + //Check if the correct answer and result is a NaN + always_comb begin + case (FmaFmtVal) + 4'b11: begin // quad + FmaRneAnsNaN = &FmaRneAns[`Q_LEN-2:`Q_NF]&(|FmaRneAns[`Q_NF-1:0]); + FmaRneResNaN = &FmaRneRes[`Q_LEN-2:`Q_NF]&(|FmaRneRes[`Q_NF-1:0]); + FmaRzAnsNaN = &FmaRzAns[`Q_LEN-2:`Q_NF]&(|FmaRzAns[`Q_NF-1:0]); + FmaRzResNaN = &FmaRzRes[`Q_LEN-2:`Q_NF]&(|FmaRzRes[`Q_NF-1:0]); + FmaRuAnsNaN = &FmaRuAns[`Q_LEN-2:`Q_NF]&(|FmaRuAns[`Q_NF-1:0]); + FmaRuResNaN = &FmaRuRes[`Q_LEN-2:`Q_NF]&(|FmaRuRes[`Q_NF-1:0]); + FmaRdAnsNaN = &FmaRdAns[`Q_LEN-2:`Q_NF]&(|FmaRdAns[`Q_NF-1:0]); + FmaRdResNaN = &FmaRdRes[`Q_LEN-2:`Q_NF]&(|FmaRdRes[`Q_NF-1:0]); + FmaRnmAnsNaN = &FmaRnmAns[`Q_LEN-2:`Q_NF]&(|FmaRnmAns[`Q_NF-1:0]); + FmaRnmResNaN = &FmaRnmRes[`Q_LEN-2:`Q_NF]&(|FmaRnmRes[`Q_NF-1:0]); + end + 4'b01: begin // double + FmaRneAnsNaN = &FmaRneAns[`D_LEN-2:`D_NF]&(|FmaRneAns[`D_NF-1:0]); + FmaRneResNaN = &FmaRneRes[`D_LEN-2:`D_NF]&(|FmaRneRes[`D_NF-1:0]); + FmaRzAnsNaN = &FmaRzAns[`D_LEN-2:`D_NF]&(|FmaRzAns[`D_NF-1:0]); + FmaRzResNaN = &FmaRzRes[`D_LEN-2:`D_NF]&(|FmaRzRes[`D_NF-1:0]); + FmaRuAnsNaN = &FmaRuAns[`D_LEN-2:`D_NF]&(|FmaRuAns[`D_NF-1:0]); + FmaRuResNaN = &FmaRuRes[`D_LEN-2:`D_NF]&(|FmaRuRes[`D_NF-1:0]); + FmaRdAnsNaN = &FmaRdAns[`D_LEN-2:`D_NF]&(|FmaRdAns[`D_NF-1:0]); + FmaRdResNaN = &FmaRdRes[`D_LEN-2:`D_NF]&(|FmaRdRes[`D_NF-1:0]); + FmaRnmAnsNaN = &FmaRnmAns[`D_LEN-2:`D_NF]&(|FmaRnmAns[`D_NF-1:0]); + FmaRnmResNaN = &FmaRnmRes[`D_LEN-2:`D_NF]&(|FmaRnmRes[`D_NF-1:0]); + end + 4'b00: begin // single + FmaRneAnsNaN = &FmaRneAns[`S_LEN-2:`S_NF]&(|FmaRneAns[`S_NF-1:0]); + FmaRneResNaN = &FmaRneRes[`S_LEN-2:`S_NF]&(|FmaRneRes[`S_NF-1:0]); + FmaRzAnsNaN = &FmaRzAns[`S_LEN-2:`S_NF]&(|FmaRzAns[`S_NF-1:0]); + FmaRzResNaN = &FmaRzRes[`S_LEN-2:`S_NF]&(|FmaRzRes[`S_NF-1:0]); + FmaRuAnsNaN = &FmaRuAns[`S_LEN-2:`S_NF]&(|FmaRuAns[`S_NF-1:0]); + FmaRuResNaN = &FmaRuRes[`S_LEN-2:`S_NF]&(|FmaRuRes[`S_NF-1:0]); + FmaRdAnsNaN = &FmaRdAns[`S_LEN-2:`S_NF]&(|FmaRdAns[`S_NF-1:0]); + FmaRdResNaN = &FmaRdRes[`S_LEN-2:`S_NF]&(|FmaRdRes[`S_NF-1:0]); + FmaRnmAnsNaN = &FmaRnmAns[`S_LEN-2:`S_NF]&(|FmaRnmAns[`S_NF-1:0]); + FmaRnmResNaN = &FmaRnmRes[`S_LEN-2:`S_NF]&(|FmaRnmRes[`S_NF-1:0]); + end + 4'b10: begin // half + FmaRneAnsNaN = &FmaRneAns[`H_LEN-2:`H_NF]&(|FmaRneAns[`H_NF-1:0]); + FmaRneResNaN = &FmaRneRes[`H_LEN-2:`H_NF]&(|FmaRneRes[`H_NF-1:0]); + FmaRzAnsNaN = &FmaRzAns[`H_LEN-2:`H_NF]&(|FmaRzAns[`H_NF-1:0]); + FmaRzResNaN = &FmaRzRes[`H_LEN-2:`H_NF]&(|FmaRzRes[`H_NF-1:0]); + FmaRuAnsNaN = &FmaRuAns[`H_LEN-2:`H_NF]&(|FmaRuAns[`H_NF-1:0]); + FmaRuResNaN = &FmaRuRes[`H_LEN-2:`H_NF]&(|FmaRuRes[`H_NF-1:0]); + FmaRdAnsNaN = &FmaRdAns[`H_LEN-2:`H_NF]&(|FmaRdAns[`H_NF-1:0]); + FmaRdResNaN = &FmaRdRes[`H_LEN-2:`H_NF]&(|FmaRdRes[`H_NF-1:0]); + FmaRnmAnsNaN = &FmaRnmAns[`H_LEN-2:`H_NF]&(|FmaRnmAns[`H_NF-1:0]); + FmaRnmResNaN = &FmaRnmRes[`H_LEN-2:`H_NF]&(|FmaRnmRes[`H_NF-1:0]); + end + endcase + end + + + always_comb begin + if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin + // an integer output can't be a NaN + AnsNaN = 1'b0; + ResNaN = 1'b0; + end + else begin + case (FmtVal) + 4'b11: begin // quad + AnsNaN = &Ans[`FLEN-2:`NF]&(|Ans[`NF-1:0]); + ResNaN = &FmaRes[`FLEN-2:`NF]&(|FmaRes[`NF-1:0]); + end + 4'b01: begin // double + AnsNaN = &Ans[`LEN1-2:`NF1]&(|Ans[`NF1-1:0]); + ResNaN = &FmaRes[`LEN1-2:`NF1]&(|FmaRes[`NF1-1:0]); + end + 4'b00: begin // single + AnsNaN = &Ans[`LEN2-2:`NF2]&(|Ans[`NF2-1:0]); + ResNaN = &FmaRes[`LEN2-2:`NF2]&(|FmaRes[`NF2-1:0]); + end + 4'b10: begin // half + AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); + ResNaN = &FmaRes[`H_LEN-2:`H_NF]&(|FmaRes[`H_NF-1:0]); + end + endcase + end + end + + // check results on falling edge of clk + always @(negedge clk) begin + + // select the result to check + case (UnitVal) + `FMAUNIT: Res = FmaRes; + `DIVUNIT: Res = DivRes; + `CMPUNIT: Res = CmpRes; + `CVTINTUNIT: Res = CvtRes; + `CVTFPUNIT: Res = CvtFpRes; + endcase + + // select the flag to check + case (UnitVal) + `FMAUNIT: ResFlg = FmaFlg; + `DIVUNIT: ResFlg = DivFlg; + `CMPUNIT: ResFlg = CmpFlg; + `CVTINTUNIT: ResFlg = CvtIntFlg; + `CVTFPUNIT: ResFlg = CvtFpFlg; + endcase + + // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: + // - the sign of the NaN does not matter for the opperations being tested + // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter + case (FmaFmtVal) + 4'b11: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRneXNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneX[`Q_LEN-2:`Q_NF],1'b1,FmaRneX[`Q_NF-2:0]})) | + (FmaRneYNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneY[`Q_LEN-2:`Q_NF],1'b1,FmaRneY[`Q_NF-2:0]})) | + (FmaRneZNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneZ[`Q_LEN-2:`Q_NF],1'b1,FmaRneZ[`Q_NF-2:0]}))); + 4'b01: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRneXNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneX[`D_LEN-2:`D_NF],1'b1,FmaRneX[`D_NF-2:0]})) | + (FmaRneYNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneY[`D_LEN-2:`D_NF],1'b1,FmaRneY[`D_NF-2:0]})) | + (FmaRneZNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneZ[`D_LEN-2:`D_NF],1'b1,FmaRneZ[`D_NF-2:0]}))); + 4'b00: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRneXNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneX[`S_LEN-2:`S_NF],1'b1,FmaRneX[`S_NF-2:0]})) | + (FmaRneYNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneY[`S_LEN-2:`S_NF],1'b1,FmaRneY[`S_NF-2:0]})) | + (FmaRneZNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneZ[`S_LEN-2:`S_NF],1'b1,FmaRneZ[`S_NF-2:0]}))); + 4'b10: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRneXNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneX[`H_LEN-2:`H_NF],1'b1,FmaRneX[`H_NF-2:0]})) | + (FmaRneYNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneY[`H_LEN-2:`H_NF],1'b1,FmaRneY[`H_NF-2:0]})) | + (FmaRneZNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneZ[`H_LEN-2:`H_NF],1'b1,FmaRneZ[`H_NF-2:0]}))); + endcase + case (FmaFmtVal) + 4'b11: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRzXNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzX[`Q_LEN-2:`Q_NF],1'b1,FmaRzX[`Q_NF-2:0]})) | + (FmaRzYNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzY[`Q_LEN-2:`Q_NF],1'b1,FmaRzY[`Q_NF-2:0]})) | + (FmaRzZNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzZ[`Q_LEN-2:`Q_NF],1'b1,FmaRzZ[`Q_NF-2:0]}))); + 4'b01: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRzXNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzX[`D_LEN-2:`D_NF],1'b1,FmaRzX[`D_NF-2:0]})) | + (FmaRzYNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzY[`D_LEN-2:`D_NF],1'b1,FmaRzY[`D_NF-2:0]})) | + (FmaRzZNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzZ[`D_LEN-2:`D_NF],1'b1,FmaRzZ[`D_NF-2:0]}))); + 4'b00: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRzXNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzX[`S_LEN-2:`S_NF],1'b1,FmaRzX[`S_NF-2:0]})) | + (FmaRzYNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzY[`S_LEN-2:`S_NF],1'b1,FmaRzY[`S_NF-2:0]})) | + (FmaRzZNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzZ[`S_LEN-2:`S_NF],1'b1,FmaRzZ[`S_NF-2:0]}))); + 4'b10: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRzXNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzX[`H_LEN-2:`H_NF],1'b1,FmaRzX[`H_NF-2:0]})) | + (FmaRzYNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzY[`H_LEN-2:`H_NF],1'b1,FmaRzY[`H_NF-2:0]})) | + (FmaRzZNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzZ[`H_LEN-2:`H_NF],1'b1,FmaRzZ[`H_NF-2:0]}))); + endcase + case (FmaFmtVal) + 4'b11: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRuXNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuX[`Q_LEN-2:`Q_NF],1'b1,FmaRuX[`Q_NF-2:0]})) | + (FmaRuYNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuY[`Q_LEN-2:`Q_NF],1'b1,FmaRuY[`Q_NF-2:0]})) | + (FmaRuZNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuZ[`Q_LEN-2:`Q_NF],1'b1,FmaRuZ[`Q_NF-2:0]}))); + 4'b01: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF{1'b0}}})) | + (FmaRuXNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuX[`D_LEN-2:`D_NF],1'b1,FmaRuX[`D_NF-2:0]})) | + (FmaRuYNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuY[`D_LEN-2:`D_NF],1'b1,FmaRuY[`D_NF-2:0]})) | + (FmaRuZNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuZ[`D_LEN-2:`D_NF],1'b1,FmaRuZ[`D_NF-2:0]}))); + 4'b00: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRuXNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuX[`S_LEN-2:`S_NF],1'b1,FmaRuX[`S_NF-2:0]})) | + (FmaRuYNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuY[`S_LEN-2:`S_NF],1'b1,FmaRuY[`S_NF-2:0]})) | + (FmaRuZNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuZ[`S_LEN-2:`S_NF],1'b1,FmaRuZ[`S_NF-2:0]}))); + 4'b10: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRuXNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuX[`H_LEN-2:`H_NF],1'b1,FmaRuX[`H_NF-2:0]})) | + (FmaRuYNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuY[`H_LEN-2:`H_NF],1'b1,FmaRuY[`H_NF-2:0]})) | + (FmaRuZNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuZ[`H_LEN-2:`H_NF],1'b1,FmaRuZ[`H_NF-2:0]}))); + endcase + case (FmaFmtVal) + 4'b11: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRdXNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdX[`Q_LEN-2:`Q_NF],1'b1,FmaRdX[`Q_NF-2:0]})) | + (FmaRdYNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdY[`Q_LEN-2:`Q_NF],1'b1,FmaRdY[`Q_NF-2:0]})) | + (FmaRdZNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdZ[`Q_LEN-2:`Q_NF],1'b1,FmaRdZ[`Q_NF-2:0]}))); + 4'b01: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRdXNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdX[`D_LEN-2:`D_NF],1'b1,FmaRdX[`D_NF-2:0]})) | + (FmaRdYNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdY[`D_LEN-2:`D_NF],1'b1,FmaRdY[`D_NF-2:0]})) | + (FmaRdZNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdZ[`D_LEN-2:`D_NF],1'b1,FmaRdZ[`D_NF-2:0]}))); + 4'b00: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRdXNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdX[`S_LEN-2:`S_NF],1'b1,FmaRdX[`S_NF-2:0]})) | + (FmaRdYNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdY[`S_LEN-2:`S_NF],1'b1,FmaRdY[`S_NF-2:0]})) | + (FmaRdZNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdZ[`S_LEN-2:`S_NF],1'b1,FmaRdZ[`S_NF-2:0]}))); + 4'b10: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRdXNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdX[`H_LEN-2:`H_NF],1'b1,FmaRdX[`H_NF-2:0]})) | + (FmaRdYNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdY[`H_LEN-2:`H_NF],1'b1,FmaRdY[`H_NF-2:0]})) | + (FmaRdZNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdZ[`H_LEN-2:`H_NF],1'b1,FmaRdZ[`H_NF-2:0]}))); + endcase + case (FmaFmtVal) + 4'b11: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (FmaRnmXNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmX[`Q_LEN-2:`Q_NF],1'b1,FmaRnmX[`Q_NF-2:0]})) | + (FmaRnmYNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmY[`Q_LEN-2:`Q_NF],1'b1,FmaRnmY[`Q_NF-2:0]})) | + (FmaRnmZNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmZ[`Q_LEN-2:`Q_NF],1'b1,FmaRnmZ[`Q_NF-2:0]}))); + 4'b01: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (FmaRnmXNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmX[`D_LEN-2:`D_NF],1'b1,FmaRnmX[`D_NF-2:0]})) | + (FmaRnmYNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmY[`D_LEN-2:`D_NF],1'b1,FmaRnmY[`D_NF-2:0]})) | + (FmaRnmZNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmZ[`D_LEN-2:`D_NF],1'b1,FmaRnmZ[`D_NF-2:0]}))); + 4'b00: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (FmaRnmXNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmX[`S_LEN-2:`S_NF],1'b1,FmaRnmX[`S_NF-2:0]})) | + (FmaRnmYNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmY[`S_LEN-2:`S_NF],1'b1,FmaRnmY[`S_NF-2:0]})) | + (FmaRnmZNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmZ[`S_LEN-2:`S_NF],1'b1,FmaRnmZ[`S_NF-2:0]}))); + 4'b10: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (FmaRnmXNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmX[`H_LEN-2:`H_NF],1'b1,FmaRnmX[`H_NF-2:0]})) | + (FmaRnmYNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmY[`H_LEN-2:`H_NF],1'b1,FmaRnmY[`H_NF-2:0]})) | + (FmaRnmZNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmZ[`H_LEN-2:`H_NF],1'b1,FmaRnmZ[`H_NF-2:0]}))); + endcase + if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) + case (FmtVal) + 4'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | + (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); + 4'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | + (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); + 4'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | + (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); + 4'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | + (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]}))); + endcase + else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format + case (OpCtrlVal[1:0]) + 2'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); + 2'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); + 2'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); + 2'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); + endcase + else NaNGood = 1'b0; // integers can't be NaNs + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||||| ||||||| ||| |||||| + // ||| ||| ||| ||| ||| ||| ||| + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // check if the non-fma test is correct + if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(UnitVal !== `CMPUNIT)) begin + errors += 1; + $display("There is an error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end + // in The RISC-V Instruction Set Manual (2019) section 11.8 specifies that + // if a any of the inputs to the EQ LT LE opperations then the opperation should return a 0 + else if ((UnitVal === `CMPUNIT)&(XNaN|YNaN)&(Res !== (`FLEN)'(0))) begin + errors += 1; + $display("There is an error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end + + // check if the fma tests are correct + if(~((FmaRneRes === FmaRneAns | FmaRneNaNGood | FmaRneNaNGood === 1'bx) & (FmaRneResFlg === FmaRneAnsFlg | FmaRneAnsFlg === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RNE"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRneX, FmaRneY, FmaRneZ, FmaRneRes, FmaRneResFlg, FmaRneAns, FmaRneAnsFlg); + $stop; + end + if(~((FmaRzRes === FmaRzAns | FmaRzNaNGood | FmaRzNaNGood === 1'bx) & (FmaRzResFlg === FmaRzAnsFlg | FmaRzAnsFlg === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RZ"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRzX, FmaRzY, FmaRzZ, FmaRzRes, FmaRzResFlg, FmaRzAns, FmaRzAnsFlg); + $stop; + end + if(~((FmaRuRes === FmaRuAns | FmaRuNaNGood | FmaRuNaNGood === 1'bx) & (FmaRuResFlg === FmaRuAnsFlg | FmaRuAnsFlg === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RU"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRuX, FmaRuY, FmaRuZ, FmaRuRes, FmaRuResFlg, FmaRuAns, FmaRuAnsFlg); + $stop; + end + if(~((FmaRdRes === FmaRdAns | FmaRdNaNGood | FmaRdNaNGood === 1'bx) & (FmaRdResFlg === FmaRdAnsFlg | FmaRdAnsFlg === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RD"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRdX, FmaRdY, FmaRdZ, FmaRdRes, FmaRdResFlg, FmaRdAns, FmaRdAnsFlg); + $stop; + end + if(~((FmaRnmRes === FmaRnmAns | FmaRnmNaNGood | FmaRnmNaNGood === 1'bx) & (FmaRnmResFlg === FmaRnmAnsFlg | FmaRnmAnsFlg === 5'bx))) begin + errors += 1; + $display("There is an error in FMA - RNM"); + $display("inputs: %h %h %h\n Res: %h %h\n Ans: %h %h", FmaRnmX, FmaRnmY, FmaRnmZ, FmaRnmRes, FmaRnmResFlg, FmaRnmAns, FmaRnmAnsFlg); + $stop; + end + + VectorNum += 1; // increment the vector + + // check to see if there more vectors in this test + // *** fix this so that fma and other run sepratly - re-add fma num + if (TestVectors[VectorNum][0] === 1'bx & + FmaRneVectors[VectorNum][0] === 1'bx & + FmaRzVectors[VectorNum][0] === 1'bx & + FmaRuVectors[VectorNum][0] === 1'bx & + FmaRdVectors[VectorNum][0] === 1'bx & + FmaRnmVectors[VectorNum][0] === 1'bx) begin // if reached the end of file + + // increment the test + TestNum += 1; + + // read next files + $readmemh({`PATH, Tests[TestNum]}, TestVectors); + $readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors); + $readmemh({`PATH, FmaRuTests[TestNum]}, FmaRuVectors); + $readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors); + $readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors); + $readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors); + + // set the vector index back to 0 + VectorNum = 0; + // incemet the operation if all the rounding modes have been tested + if(FrmNum === 4) OpCtrlNum += 1; + // increment the rounding mode or loop back to rne + if(FrmNum < 4) FrmNum += 1; + else FrmNum = 0; + + // if no more Tests - finish + if(Tests[TestNum] === "" & + FmaRneTests[TestNum] === "" & + FmaRzTests[TestNum] === "" & + FmaRuTests[TestNum] === "" & + FmaRdTests[TestNum] === "" & + FmaRnmTests[TestNum] === "") begin + $display("\nAll Tests completed with %d errors\n", errors); + $stop; + end + + $display("Running %s vectors", Tests[TestNum]); + end + end +endmodule + + + + + + + + + + + + + +module readfmavectors ( + input logic clk, + input logic [`FPSIZES/3:0] FmaModFmt, // the modified format + input logic [1:0] FmaFmt, // the format of the FMA inputs + input logic [`FLEN*4+7:0] TestVector, // the test vector + output logic [`FLEN-1:0] Ans, // the correct answer + output logic ZOrigDenormE, // is z denormalized in it's original precision + output logic [4:0] AnsFlg, // the correct flag + output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ + output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) + output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN + output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN + output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero + output logic XInfE, YInfE, ZInfE, // is XYZ infinity + output logic [`FLEN-1:0] X, Y, Z // inputs +); + + logic XNormE, XExpMaxE; // signals the unpacker outputs but isn't used in FMA + // apply test vectors on rising edge of clk + // Format of vectors Inputs(1/2/3)_AnsFlg + always @(posedge clk) begin + #1; + AnsFlg = TestVector[4:0]; + case (FmaFmt) + 2'b11: begin // quad + X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)]; + Y = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Z = TestVector[8+2*(`Q_LEN)-1:8+`Q_LEN]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+4*(`D_LEN)-1:8+3*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+`D_LEN]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+4*(`S_LEN)-1:8+3*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+`S_LEN]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+4*(`H_LEN)-1:8+3*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+`H_LEN]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + + unpack unpack(.X, .Y, .Z, .FmtE(FmaModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, + .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, + .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, + .XExpMaxE, .ZOrigDenormE); +endmodule + + + + + + + + + + + + + + + + + +module readvectors ( + input logic clk, + input logic [`FLEN*4+7:0] TestVector, + input logic [`FPSIZES/3:0] ModFmt, + input logic [1:0] Fmt, + input logic [2:0] Unit, + input logic [31:0] VectorNum, + input logic [31:0] TestNum, + input logic [2:0] OpCtrl, + output logic [`FLEN-1:0] Ans, + output logic [`XLEN-1:0] SrcA, + output logic [4:0] AnsFlg, + output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ + output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) + output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN + output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN + output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized + output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero + output logic XInfE, YInfE, ZInfE, // is XYZ infinity + output logic XNormE, XExpMaxE, + output logic ZOrigDenormE, + output logic [`FLEN-1:0] X, Y, Z +); + + // apply test vectors on rising edge of clk + // Format of vectors Inputs(1/2/3)_AnsFlg + always @(posedge clk) begin + #1; + AnsFlg = TestVector[4:0]; + case (Unit) + `FMAUNIT: + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, `Q_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, `D_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; + else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, `S_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; + else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, `H_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; + else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + `DIVUNIT: + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + `CMPUNIT: + case (Fmt) + 2'b11: begin // quad + X = TestVector[12+2*(`Q_LEN)-1:12+(`Q_LEN)]; + Y = TestVector[12+(`Q_LEN)-1:12]; + Ans = TestVector[8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+2*(`D_LEN)-1:12+(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+(`D_LEN)-1:12]}; + Ans = TestVector[8]; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+2*(`S_LEN)-1:12+(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+(`S_LEN)-1:12]}; + Ans = TestVector[8]; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+3*(`H_LEN)-1:12+(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]}; + Ans = TestVector[8]; + end + endcase + `CVTFPUNIT: + case (Fmt) + 2'b11: begin // quad + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`Q_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`Q_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`Q_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`Q_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b01: begin // double + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b00: begin // single + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b10: begin // half + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + endcase + + `CVTINTUNIT: + case (Fmt) + 2'b11: begin // quad + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2], OpCtrl[0]}) + 2'b11: begin // long -> quad + SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // int -> quad + // correctly sign extend the integer depending on if it's a signed/unsigned test + SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b10: begin // quad -> long + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // double -> long + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; + Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + end + endcase + end + 2'b01: begin // double + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2], OpCtrl[0]}) + 2'b11: begin // long -> double + SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]; + Ans = TestVector[8+(`D_LEN-1):8]; + end + 2'b01: begin // int -> double + // correctly sign extend the integer depending on if it's a signed/unsigned test + SrcA = {{`XLEN-32{TestVector[8+`D_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]}; + Ans = TestVector[8+(`D_LEN-1):8]; + end + 2'b10: begin // double -> long + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // double -> int + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; + Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + end + endcase + end + 2'b00: begin // single + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2], OpCtrl[0]}) + 2'b11: begin // long -> single + SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]; + Ans = TestVector[8+(`S_LEN-1):8]; + end + 2'b01: begin // int -> single + // correctly sign extend the integer depending on if it's a signed/unsigned test + SrcA = {{`XLEN-32{TestVector[8+`S_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]}; + Ans = TestVector[8+(`S_LEN-1):8]; + end + 2'b10: begin // single -> long + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // single -> int + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; + Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + end + endcase + end + 2'b10: begin // half + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2], OpCtrl[0]}) + 2'b11: begin // long -> half + SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]; + Ans = TestVector[8+(`H_LEN-1):8]; + end + 2'b01: begin // int -> half + // correctly sign extend the integer depending on if it's a signed/unsigned test + SrcA = {{`XLEN-32{TestVector[8+`H_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]}; + Ans = TestVector[8+(`H_LEN-1):8]; + end + 2'b10: begin // half -> long + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // half -> int + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; + Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}}, TestVector[8+(`XLEN-1):8]}; + end + endcase + end + endcase + endcase + end + + unpack unpack(.X, .Y, .Z, .FmtE(ModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, + .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, + .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, + .XExpMaxE, .ZOrigDenormE); +endmodule \ No newline at end of file diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index f405af48f..31add80a2 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -27,15 +27,6 @@ `include "wally-config.vh" -`define DEBUG_TRACE 0 -// Debug Levels -// 0: don't check against QEMU -// 1: print disagreements with QEMU, but only halt on PCW disagreements -// 2: halt on any disagreement with QEMU except CSRs -// 3: halt on all disagreements with QEMU -// 4: print memory accesses whenever they happen -// 5: print everything - module testbench; /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////// CONFIG //////////////////////////////////// @@ -45,8 +36,15 @@ module testbench; parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim parameter CHECKPOINT = 0; parameter RISCV_DIR = "/opt/riscv"; - parameter NO_IE_MTIME_CHECKPOINT = 0; - + parameter NO_SPOOFING = 0; + parameter DEBUG_TRACE = 0; + // Debug Levels + // 0: don't check against QEMU + // 1: print disagreements with QEMU, but only halt on PCW disagreements + // 2: halt on any disagreement with QEMU except CSRs + // 3: halt on all disagreements with QEMU + // 4: print memory accesses whenever they happen + // 5: print everything @@ -95,7 +93,7 @@ module testbench; logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ string ExpectedCSRArray``STAGE[10:0]; \ - logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; + logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? `DECLARE_TRACE_SCANNER_SIGNALS(E) `DECLARE_TRACE_SCANNER_SIGNALS(M) // M-stage expected values @@ -218,7 +216,7 @@ module testbench; /////////////////////////////// Cache Issue /////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// logic probe; - if (NO_IE_MTIME_CHECKPOINT) + if (NO_SPOOFING) assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c & testbench.dut.core.InstrM != 32'h14021273 & testbench.dut.core.InstrValidM; @@ -358,7 +356,7 @@ module testbench; `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin `INIT_CHECKPOINT_VAL(MIE, [11:0]); `INIT_CHECKPOINT_VAL(MIP, [11:0]); end @@ -395,7 +393,7 @@ module testbench; // ========== INITIALIZATION ========== initial begin - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin force `MEIP = 0; force `SEIP = 0; force `UART_IP = 0; @@ -405,7 +403,7 @@ module testbench; $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR); if (CHECKPOINT!=0) $sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT); - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); + $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); // *** initialize these using zeroes rather than reading from files, see testbench.sv $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"}; ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"}; @@ -462,7 +460,7 @@ module testbench; release `INSTRET; end // Get the E-stage trace reader ahead of the M-stage trace reader - matchCountE = $fgets(lineE,traceFileE); + matchCountE = $fgets(lineE,traceFileE); // *** look at removing? end /////////////////////////////////////////////////////////////////////////////// @@ -482,7 +480,7 @@ module testbench; if (checkInstrM) begin \ // read 1 line of the trace file \ matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \ - if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ + if(DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ // extract PC, Instr \ matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \ if (`"STAGE`"=="M") begin \ @@ -547,16 +545,16 @@ module testbench; if(`"STAGE`"=="M") begin \ // override on special conditions \ if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \ - if(!NO_IE_MTIME_CHECKPOINT) begin \ - $display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \ + if(!NO_SPOOFING) begin \ + $display("%tns, %d instrs: Overwrite UART's Register in memory stage.", $time, AttemptedInstructionCount); \ force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ end \ end else \ - if(!NO_IE_MTIME_CHECKPOINT) \ + if(!NO_SPOOFING) \ release dut.core.ieu.dp.ReadDataM; \ if(textM.substr(0,5) == "rdtime") begin \ //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \ - if(!NO_IE_MTIME_CHECKPOINT) \ + if(!NO_SPOOFING) \ force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ end \ end \ @@ -566,14 +564,14 @@ module testbench; `define checkEQ(NAME, VAL, EXPECTED) \ if(VAL != EXPECTED) begin \ $display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \ - if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \ + if ((NAME == "PCW") | (DEBUG_TRACE >= 2)) fault = 1; \ end `define checkCSR(CSR) \ begin \ if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ - if(`DEBUG_TRACE >= 3) fault = 1; \ + if(DEBUG_TRACE >= 3) fault = 1; \ end \ end @@ -633,7 +631,7 @@ module testbench; if(~dut.core.StallW) begin if(textW.substr(0,5) == "rdtime") begin //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); - if(!NO_IE_MTIME_CHECKPOINT) + if(!NO_SPOOFING) release dut.uncore.clint.clint.MTIME; end //if (ExpectedIEUAdrM == 'h10000005) begin @@ -656,15 +654,15 @@ module testbench; // turn on waves if (AttemptedInstructionCount == INSTR_WAVEON) $stop; // end sim - if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop; + if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end fault = 0; - if (`DEBUG_TRACE >= 1) begin + if (DEBUG_TRACE >= 1) begin `checkEQ("PCW",PCW,ExpectedPCW) //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of // compressed to uncompressed conversion `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) #2; // delay 2 ns. - if(`DEBUG_TRACE >= 5) begin + if(DEBUG_TRACE >= 5) begin $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); end @@ -674,13 +672,13 @@ module testbench; `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) end if (MemOpW.substr(0,2) == "Mem") begin - if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); + if(DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) if(MemOpW == "MemR" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); + if(DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); + if(DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) end end @@ -702,7 +700,7 @@ module testbench; "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) "mip": begin `checkCSR(`CSR_BASE.csrm.MIP_REGW) - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) force `MEIP = 0; if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) @@ -718,9 +716,9 @@ module testbench; if (fault == 1) begin errorCount +=1; $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); - $stop; + $stop; $stop; end - end // if (`DEBUG_TRACE >= 1) + end // if (DEBUG_TRACE >= 1) end // if (checkInstrW) end // always @ (negedge clk) @@ -734,7 +732,7 @@ module testbench; always @(negedge clk) begin if(checkInterruptM) begin if((interruptInstrCount+1) == AttemptedInstructionCount) begin - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin case (interruptCauseVal) 11: begin force `MEIP = 1; @@ -765,7 +763,7 @@ module testbench; end end end - + diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index d070aa3f2..4ebd37785 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -327,11 +327,21 @@ logic [3:0] dummy; .done(DCacheFlushDone)); // initialize the branch predictor - if (`BPRED_ENABLED == 1) - initial begin - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); - end + if (`BPRED_ENABLED == 1) + begin + genvar adrindex; + + // Initializing all zeroes into the branch predictor memory. + for(adrindex = 0; adrindex < 1024; adrindex++) begin + initial begin + force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + #1; + release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; + release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end + end + end endmodule module riscvassertions; diff --git a/pipelined/testbench/tests-fp.vh b/pipelined/testbench/tests-fp.vh new file mode 100644 index 000000000..d285454bb --- /dev/null +++ b/pipelined/testbench/tests-fp.vh @@ -0,0 +1,587 @@ +/////////////////////////////////////////// +// tests.vh +// +// Written: David_Harris@hmc.edu 7 October 2021 +// Modified: +// +// Purpose: List of tests to apply +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + +`define PATH "../../tests/fp/vectors/" +`define ADD_OPCTRL 3'b110 +`define MUL_OPCTRL 3'b100 +`define SUB_OPCTRL 3'b111 +`define FADD_OPCTRL 3'b000 +`define DIV_OPCTRL 3'b000 +`define SQRT_OPCTRL 3'b001 +`define LE_OPCTRL 3'b011 +`define LT_OPCTRL 3'b001 +`define EQ_OPCTRL 3'b010 +`define TO_UI_OPCTRL 3'b011 +`define TO_I_OPCTRL 3'b001 +`define TO_UL_OPCTRL 3'b111 +`define TO_L_OPCTRL 3'b101 +`define FROM_UI_OPCTRL 3'b010 +`define FROM_I_OPCTRL 3'b000 +`define FROM_UL_OPCTRL 3'b110 +`define FROM_L_OPCTRL 3'b100 +`define RNE 3'b000 +`define RZ 3'b001 +`define RU 3'b011 +`define RD 3'b010 +`define RNM 3'b100 +`define FMAUNIT 0 +`define DIVUNIT 1 +`define CVTINTUNIT 2 +`define CVTFPUNIT 3 +`define CMPUNIT 4 + +string f16rv32cvtint[] = '{ + "f16_to_i32_rne.tv", + "f16_to_i32_rz.tv", + "f16_to_i32_ru.tv", + "f16_to_i32_rd.tv", + "f16_to_i32_rnm.tv", + "f16_to_ui32_rne.tv", + "f16_to_ui32_rz.tv", + "f16_to_ui32_ru.tv", + "f16_to_ui32_rd.tv", + "f16_to_ui32_rnm.tv", + "ui32_to_f16_rne.tv", + "ui32_to_f16_rz.tv", + "ui32_to_f16_ru.tv", + "ui32_to_f16_rd.tv", + "ui32_to_f16_rnm.tv", + "i32_to_f16_rne.tv", + "i32_to_f16_rz.tv", + "i32_to_f16_ru.tv", + "i32_to_f16_rd.tv", + "i32_to_f16_rnm.tv" +}; + +string f16rv64cvtint[] = '{ + "f16_to_ui64_rne.tv", + "f16_to_ui64_rz.tv", + "f16_to_ui64_ru.tv", + "f16_to_ui64_rd.tv", + "f16_to_ui64_rnm.tv", + "f16_to_i64_rne.tv", + "f16_to_i64_rz.tv", + "f16_to_i64_ru.tv", + "f16_to_i64_rd.tv", + "f16_to_i64_rnm.tv", + "ui64_to_f16_rne.tv", + "ui64_to_f16_rz.tv", + "ui64_to_f16_ru.tv", + "ui64_to_f16_rd.tv", + "ui64_to_f16_rnm.tv", + "i64_to_f16_rne.tv", + "i64_to_f16_rz.tv", + "i64_to_f16_ru.tv", + "i64_to_f16_rd.tv", + "i64_to_f16_rnm.tv" +}; + +string f32rv32cvtint[] = '{ + "ui32_to_f32_rne.tv", + "ui32_to_f32_rz.tv", + "ui32_to_f32_ru.tv", + "ui32_to_f32_rd.tv", + "ui32_to_f32_rnm.tv", + "i32_to_f32_rne.tv", + "i32_to_f32_rz.tv", + "i32_to_f32_ru.tv", + "i32_to_f32_rd.tv", + "i32_to_f32_rnm.tv", + "f32_to_ui32_rne.tv", + "f32_to_ui32_rz.tv", + "f32_to_ui32_ru.tv", + "f32_to_ui32_rd.tv", + "f32_to_ui32_rnm.tv", + "f32_to_i32_rne.tv", + "f32_to_i32_rz.tv", + "f32_to_i32_ru.tv", + "f32_to_i32_rd.tv", + "f32_to_i32_rnm.tv" +}; + +string f32rv64cvtint[] = '{ + "ui64_to_f32_rne.tv", + "ui64_to_f32_rz.tv", + "ui64_to_f32_ru.tv", + "ui64_to_f32_rd.tv", + "ui64_to_f32_rnm.tv", + "i64_to_f32_rne.tv", + "i64_to_f32_rz.tv", + "i64_to_f32_ru.tv", + "i64_to_f32_rd.tv", + "i64_to_f32_rnm.tv", + "f32_to_ui64_rne.tv", + "f32_to_ui64_rz.tv", + "f32_to_ui64_ru.tv", + "f32_to_ui64_rd.tv", + "f32_to_ui64_rnm.tv", + "f32_to_i64_rne.tv", + "f32_to_i64_rz.tv", + "f32_to_i64_ru.tv", + "f32_to_i64_rd.tv", + "f32_to_i64_rnm.tv" +}; + + +string f64rv32cvtint[] = '{ + "ui32_to_f64_rne.tv", + "ui32_to_f64_rz.tv", + "ui32_to_f64_ru.tv", + "ui32_to_f64_rd.tv", + "ui32_to_f64_rnm.tv", + "i32_to_f64_rne.tv", + "i32_to_f64_rz.tv", + "i32_to_f64_ru.tv", + "i32_to_f64_rd.tv", + "i32_to_f64_rnm.tv", + "f64_to_ui32_rne.tv", + "f64_to_ui32_rz.tv", + "f64_to_ui32_ru.tv", + "f64_to_ui32_rd.tv", + "f64_to_ui32_rnm.tv", + "f64_to_i32_rne.tv", + "f64_to_i32_rz.tv", + "f64_to_i32_ru.tv", + "f64_to_i32_rd.tv", + "f64_to_i32_rnm.tv" +}; + +string f64rv64cvtint[] = '{ + "ui64_to_f64_rne.tv", + "ui64_to_f64_rz.tv", + "ui64_to_f64_ru.tv", + "ui64_to_f64_rd.tv", + "ui64_to_f64_rnm.tv", + "i64_to_f64_rne.tv", + "i64_to_f64_rz.tv", + "i64_to_f64_ru.tv", + "i64_to_f64_rd.tv", + "i64_to_f64_rnm.tv", + "f64_to_ui64_rne.tv", + "f64_to_ui64_rz.tv", + "f64_to_ui64_ru.tv", + "f64_to_ui64_rd.tv", + "f64_to_ui64_rnm.tv", + "f64_to_i64_rne.tv", + "f64_to_i64_rz.tv", + "f64_to_i64_ru.tv", + "f64_to_i64_rd.tv", + "f64_to_i64_rnm.tv" +}; + +string f128rv64cvtint[] = '{ + "ui64_to_f128_rne.tv", + "ui64_to_f128_rz.tv", + "ui64_to_f128_ru.tv", + "ui64_to_f128_rd.tv", + "ui64_to_f128_rnm.tv", + "i64_to_f128_rne.tv", + "i64_to_f128_rz.tv", + "i64_to_f128_ru.tv", + "i64_to_f128_rd.tv", + "i64_to_f128_rnm.tv", + "f128_to_ui64_rne.tv", + "f128_to_ui64_rz.tv", + "f128_to_ui64_ru.tv", + "f128_to_ui64_rd.tv", + "f128_to_ui64_rnm.tv", + "f128_to_i64_rne.tv", + "f128_to_i64_rz.tv", + "f128_to_i64_ru.tv", + "f128_to_i64_rd.tv", + "f128_to_i64_rnm.tv" +}; + +string f128rv32cvtint[] = '{ + "ui32_to_f128_rne.tv", + "ui32_to_f128_rz.tv", + "ui32_to_f128_ru.tv", + "ui32_to_f128_rd.tv", + "ui32_to_f128_rnm.tv", + "i32_to_f128_rne.tv", + "i32_to_f128_rz.tv", + "i32_to_f128_ru.tv", + "i32_to_f128_rd.tv", + "i32_to_f128_rnm.tv", + "f128_to_ui32_rne.tv", + "f128_to_ui32_rz.tv", + "f128_to_ui32_ru.tv", + "f128_to_ui32_rd.tv", + "f128_to_ui32_rnm.tv", + "f128_to_i32_rne.tv", + "f128_to_i32_rz.tv", + "f128_to_i32_ru.tv", + "f128_to_i32_rd.tv", + "f128_to_i32_rnm.tv" +}; + + +string f32f16cvt[] = '{ + "f32_to_f16_rne.tv", + "f32_to_f16_rz.tv", + "f32_to_f16_ru.tv", + "f32_to_f16_rd.tv", + "f32_to_f16_rnm.tv", + "f16_to_f32_rne.tv", + "f16_to_f32_rz.tv", + "f16_to_f32_ru.tv", + "f16_to_f32_rd.tv", + "f16_to_f32_rnm.tv" +}; + +string f64f16cvt[] = '{ + "f64_to_f16_rne.tv", + "f64_to_f16_rz.tv", + "f64_to_f16_ru.tv", + "f64_to_f16_rd.tv", + "f64_to_f16_rnm.tv", + "f16_to_f64_rne.tv", + "f16_to_f64_rz.tv", + "f16_to_f64_ru.tv", + "f16_to_f64_rd.tv", + "f16_to_f64_rnm.tv" +}; + +string f128f16cvt[] = '{ + "f128_to_f16_rne.tv", + "f128_to_f16_rz.tv", + "f128_to_f16_ru.tv", + "f128_to_f16_rd.tv", + "f128_to_f16_rnm.tv", + "f16_to_f128_rne.tv", + "f16_to_f128_rz.tv", + "f16_to_f128_ru.tv", + "f16_to_f128_rd.tv", + "f16_to_f128_rnm.tv" +}; + +string f64f32cvt[] = '{ + "f64_to_f32_rne.tv", + "f64_to_f32_rz.tv", + "f64_to_f32_ru.tv", + "f64_to_f32_rd.tv", + "f64_to_f32_rnm.tv", + "f32_to_f64_rne.tv", + "f32_to_f64_rz.tv", + "f32_to_f64_ru.tv", + "f32_to_f64_rd.tv", + "f32_to_f64_rnm.tv" +}; + + +string f128f32cvt[] = '{ + "f128_to_f32_rne.tv", + "f128_to_f32_rz.tv", + "f128_to_f32_ru.tv", + "f128_to_f32_rd.tv", + "f128_to_f32_rnm.tv", + "f32_to_f128_rne.tv", + "f32_to_f128_rz.tv", + "f32_to_f128_ru.tv", + "f32_to_f128_rd.tv", + "f32_to_f128_rnm.tv" +}; + + +string f128f64cvt[] = '{ + "f64_to_f128_rne.tv", + "f64_to_f128_rz.tv", + "f64_to_f128_ru.tv", + "f64_to_f128_rd.tv", + "f64_to_f128_rnm.tv", + "f128_to_f64_rne.tv", + "f128_to_f64_rz.tv", + "f128_to_f64_ru.tv", + "f128_to_f64_rd.tv", + "f128_to_f64_rnm.tv" +}; + +string f16add[] = '{ + "f16_add_rne.tv", + "f16_add_rz.tv", + "f16_add_ru.tv", + "f16_add_rd.tv", + "f16_add_rnm.tv" +}; + +string f32add[] = '{ + "f32_add_rne.tv", + "f32_add_rz.tv", + "f32_add_ru.tv", + "f32_add_rd.tv", + "f32_add_rnm.tv" +}; + +string f64add[] = '{ + "f64_add_rne.tv", + "f64_add_rz.tv", + "f64_add_ru.tv", + "f64_add_rd.tv", + "f64_add_rnm.tv" +}; + +string f128add[] = '{ + "f128_add_rne.tv", + "f128_add_rz.tv", + "f128_add_ru.tv", + "f128_add_rd.tv", + "f128_add_rnm.tv" +}; + +string f16sub[] = '{ + "f16_sub_rne.tv", + "f16_sub_rz.tv", + "f16_sub_ru.tv", + "f16_sub_rd.tv", + "f16_sub_rnm.tv" +}; + +string f32sub[] = '{ + "f32_sub_rne.tv", + "f32_sub_rz.tv", + "f32_sub_ru.tv", + "f32_sub_rd.tv", + "f32_sub_rnm.tv" +}; + +string f64sub[] = '{ + "f64_sub_rne.tv", + "f64_sub_rz.tv", + "f64_sub_ru.tv", + "f64_sub_rd.tv", + "f64_sub_rnm.tv" +}; + +string f128sub[] = '{ + "f128_sub_rne.tv", + "f128_sub_rz.tv", + "f128_sub_ru.tv", + "f128_sub_rd.tv", + "f128_sub_rnm.tv" +}; + +string f16mul[] = '{ + "f16_mul_rne.tv", + "f16_mul_rz.tv", + "f16_mul_ru.tv", + "f16_mul_rd.tv", + "f16_mul_rnm.tv" +}; + +string f32mul[] = '{ + "f32_mul_rne.tv", + "f32_mul_rz.tv", + "f32_mul_ru.tv", + "f32_mul_rd.tv", + "f32_mul_rnm.tv" +}; + +string f64mul[] = '{ + "f64_mul_rne.tv", + "f64_mul_rz.tv", + "f64_mul_ru.tv", + "f64_mul_rd.tv", + "f64_mul_rnm.tv" +}; + +string f128mul[] = '{ + "f128_mul_rne.tv", + "f128_mul_rz.tv", + "f128_mul_ru.tv", + "f128_mul_rd.tv", + "f128_mul_rnm.tv" +}; + +string f16div[] = '{ + "f16_div_rne.tv", + "f16_div_rz.tv", + "f16_div_ru.tv", + "f16_div_rd.tv", + "f16_div_rnm.tv" +}; + +string f32div[] = '{ + "f32_div_rne.tv", + "f32_div_rz.tv", + "f32_div_ru.tv", + "f32_div_rd.tv", + "f32_div_rnm.tv" +}; + +string f64div[] = '{ + "f64_div_rne.tv", + "f64_div_rz.tv", + "f64_div_ru.tv", + "f64_div_rd.tv", + "f64_div_rnm.tv" +}; + +string f128div[] = '{ + "f128_div_rne.tv", + "f128_div_rz.tv", + "f128_div_ru.tv", + "f128_div_rd.tv", + "f128_div_rnm.tv" +}; + +string f16sqrt[] = '{ + "f16_sqrt_rne.tv", + "f16_sqrt_rz.tv", + "f16_sqrt_ru.tv", + "f16_sqrt_rd.tv", + "f16_sqrt_rnm.tv" +}; + +string f32sqrt[] = '{ + "f32_sqrt_rne.tv", + "f32_sqrt_rz.tv", + "f32_sqrt_ru.tv", + "f32_sqrt_rd.tv", + "f32_sqrt_rnm.tv" +}; + +string f64sqrt[] = '{ + "f64_sqrt_rne.tv", + "f64_sqrt_rz.tv", + "f64_sqrt_ru.tv", + "f64_sqrt_rd.tv", + "f64_sqrt_rnm.tv" +}; + +string f128sqrt[] = '{ + "f128_sqrt_rne.tv", + "f128_sqrt_rz.tv", + "f128_sqrt_ru.tv", + "f128_sqrt_rd.tv", + "f128_sqrt_rnm.tv" +}; + +string f16cmp[] = '{ + "f16_eq_rne.tv", + "f16_eq_rz.tv", + "f16_eq_ru.tv", + "f16_eq_rd.tv", + "f16_eq_rnm.tv", + "f16_le_rne.tv", + "f16_le_rz.tv", + "f16_le_ru.tv", + "f16_le_rd.tv", + "f16_le_rnm.tv", + "f16_lt_rne.tv", + "f16_lt_rz.tv", + "f16_lt_ru.tv", + "f16_lt_rd.tv", + "f16_lt_rnm.tv" +}; + +string f32cmp[] = '{ + "f32_eq_rne.tv", + "f32_eq_rz.tv", + "f32_eq_ru.tv", + "f32_eq_rd.tv", + "f32_eq_rnm.tv", + "f32_le_rne.tv", + "f32_le_rz.tv", + "f32_le_ru.tv", + "f32_le_rd.tv", + "f32_le_rnm.tv", + "f32_lt_rne.tv", + "f32_lt_rz.tv", + "f32_lt_ru.tv", + "f32_lt_rd.tv", + "f32_lt_rnm.tv" +}; + +string f64cmp[] = '{ + "f64_eq_rne.tv", + "f64_eq_rz.tv", + "f64_eq_ru.tv", + "f64_eq_rd.tv", + "f64_eq_rnm.tv", + "f64_le_rne.tv", + "f64_le_rz.tv", + "f64_le_ru.tv", + "f64_le_rd.tv", + "f64_le_rnm.tv", + "f64_lt_rne.tv", + "f64_lt_rz.tv", + "f64_lt_ru.tv", + "f64_lt_rd.tv", + "f64_lt_rnm.tv" +}; + +string f128cmp[] = '{ + "f128_eq_rne.tv", + "f128_eq_rz.tv", + "f128_eq_ru.tv", + "f128_eq_rd.tv", + "f128_eq_rnm.tv", + "f128_le_rne.tv", + "f128_le_rz.tv", + "f128_le_ru.tv", + "f128_le_rd.tv", + "f128_le_rnm.tv", + "f128_lt_rne.tv", + "f128_lt_rz.tv", + "f128_lt_ru.tv", + "f128_lt_rd.tv", + "f128_lt_rnm.tv" +}; + +string f16fma[] = '{ + "f16_mulAdd_rne.tv", + "f16_mulAdd_rz.tv", + "f16_mulAdd_ru.tv", + "f16_mulAdd_rd.tv", + "f16_mulAdd_rnm.tv" +}; + +string f32fma[] = '{ + "f32_mulAdd_rne.tv", + "f32_mulAdd_rz.tv", + "f32_mulAdd_ru.tv", + "f32_mulAdd_rd.tv", + "f32_mulAdd_rnm.tv" +}; + +string f64fma[] = '{ + "f64_mulAdd_rne.tv", + "f64_mulAdd_rz.tv", + "f64_mulAdd_ru.tv", + "f64_mulAdd_rd.tv", + "f64_mulAdd_rnm.tv" +}; + +string f128fma[] = '{ + "f128_mulAdd_rne.tv", + "f128_mulAdd_rz.tv", + "f128_mulAdd_ru.tv", + "f128_mulAdd_rd.tv", + "f128_mulAdd_rnm.tv" +}; + + + diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 49ff0ff5c..dba197f5f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -962,7 +962,7 @@ string imperas32f[] = '{ "rv64i_m/I/andi-01", "6010", "rv64i_m/I/auipc-01", "2010", "rv64i_m/I/beq-01", "47010", - "rv64i_m/I/bge-01", "46010", + "rv64i_m/I/bge-01", "47010", "rv64i_m/I/bgeu-01", "56010", "rv64i_m/I/blt-01", "4d010", "rv64i_m/I/bltu-01", "57010", diff --git a/synthDC/Synopsys_stack_trace_12580.txt b/synthDC/Synopsys_stack_trace_12580.txt new file mode 100644 index 000000000..ca9522e03 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_12580.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 12580 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_32764.txt b/synthDC/Synopsys_stack_trace_32764.txt new file mode 100644 index 000000000..f845fa3f8 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_32764.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 32764 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_52064.txt b/synthDC/Synopsys_stack_trace_52064.txt new file mode 100644 index 000000000..f62c1acfc --- /dev/null +++ b/synthDC/Synopsys_stack_trace_52064.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 52064 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_55441.txt b/synthDC/Synopsys_stack_trace_55441.txt new file mode 100644 index 000000000..0e7a3c988 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_55441.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 55441 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57184.txt b/synthDC/Synopsys_stack_trace_57184.txt new file mode 100644 index 000000000..a016d47c4 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_57184.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 57184 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57185.txt b/synthDC/Synopsys_stack_trace_57185.txt new file mode 100644 index 000000000..dec54674a --- /dev/null +++ b/synthDC/Synopsys_stack_trace_57185.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 57185 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/crte_000012580.txt b/synthDC/crte_000012580.txt new file mode 100644 index 000000000..2bc74daac --- /dev/null +++ b/synthDC/crte_000012580.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +12580 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 23:44:09 UTC 2022 (1652744649) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000032764.txt b/synthDC/crte_000032764.txt new file mode 100644 index 000000000..87eaa3c4c --- /dev/null +++ b/synthDC/crte_000032764.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +32764 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Tue May 17 00:05:18 UTC 2022 (1652745918) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 dest +0x00000000 15204364 harris 644 790528 3 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000052064.txt b/synthDC/crte_000052064.txt new file mode 100644 index 000000000..2eef81a43 --- /dev/null +++ b/synthDC/crte_000052064.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +52064 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Thu May 12 21:44:48 UTC 2022 (1652391888) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 dest +0x00000000 15204364 harris 644 790528 2 dest +0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000055441.txt b/synthDC/crte_000055441.txt new file mode 100644 index 000000000..7bd6f6855 --- /dev/null +++ b/synthDC/crte_000055441.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +55441 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Thu May 12 21:47:47 UTC 2022 (1652392067) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 dest +0x00000000 15204364 harris 644 790528 2 dest +0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000057184.txt b/synthDC/crte_000057184.txt new file mode 100644 index 000000000..77c41bece --- /dev/null +++ b/synthDC/crte_000057184.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +57184 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 22:54:26 UTC 2022 (1652741666) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000057185.txt b/synthDC/crte_000057185.txt new file mode 100644 index 000000000..d99b82eb3 --- /dev/null +++ b/synthDC/crte_000057185.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +57185 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 22:54:26 UTC 2022 (1652741666) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/ppa.py b/synthDC/ppa.py deleted file mode 100755 index 91b21d880..000000000 --- a/synthDC/ppa.py +++ /dev/null @@ -1,61 +0,0 @@ -#!/usr/bin/python3 -# from msilib.schema import File -import subprocess -from multiprocessing import Pool -import csv -import re -import matplotlib.pyplot as plt -import numpy as np - - -def run_command(module, width, freq): - command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq) - subprocess.Popen(command, shell=True) - -widths = ['32'] -modules = ['shifter'] -freqs = ['10', '4000', '5000', '6000'] - -LoT = [] -for module in modules: - for width in widths: - for freq in freqs: - LoT += [[module, width, freq]] - -pool = Pool() -pool.starmap(run_command, LoT) - -bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" -outputCPL = subprocess.check_output(['bash','-c', bashCommand]) -linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] - -bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" -outputDA = subprocess.check_output(['bash','-c', bashCommand]) -linesDA = outputDA.decode("utf-8").split('\n')[:-1] - -cpl = re.compile('\d{1}\.\d{6}') -f = re.compile('_\d*_MHz') -wm = re.compile('ppa_\w*_\d*_qor') -da = re.compile('\d*\.\d{6}') - -allSynths = [] - -for i in range(len(linesCPL)): - line = linesCPL[i] - oneSynth = [] - mwm = wm.findall(line)[0][4:-4].split('_') - oneSynth += [mwm[0]] - oneSynth += [mwm[1]] - oneSynth += [f.findall(line)[0][1:-4]] - oneSynth += cpl.findall(line) - oneSynth += da.findall(linesDA[i]) - allSynths += [oneSynth] - -file = open("ppaData.csv", "w") -writer = csv.writer(file) -writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) - -for one in allSynths: - writer.writerow(one) - -file.close() \ No newline at end of file diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py new file mode 100755 index 000000000..dd3fcf23b --- /dev/null +++ b/synthDC/ppaAnalyze.py @@ -0,0 +1,297 @@ +#!/usr/bin/python3 +# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22 + +from distutils.log import error +from statistics import median +import subprocess +import statistics +import csv +import re +import matplotlib.pyplot as plt +import matplotlib.lines as lines +import numpy as np + + +def getData(mod=None, width=None): + specStr = '' + if mod != None: + specStr = mod + if width != None: + specStr += ('_'+str(width)) + specStr += '*' + + bashCommand = "grep 'Critical Path Length' runs/ppa_{}/reports/*qor*".format(specStr) + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] + + bashCommand = "grep 'Design Area' runs/ppa_{}/reports/*qor*".format(specStr) + outputDA = subprocess.check_output(['bash','-c', bashCommand]) + linesDA = outputDA.decode("utf-8").split('\n')[:-1] + + bashCommand = "grep '100' runs/ppa_{}/reports/*power*".format(specStr) + outputP = subprocess.check_output(['bash','-c', bashCommand]) + linesP = outputP.decode("utf-8").split('\n')[:-1] + + cpl = re.compile('\d{1}\.\d{6}') + f = re.compile('_\d*_MHz') + wm = re.compile('ppa_\w*_\d*_qor') + da = re.compile('\d*\.\d{6}') + p = re.compile('\d+\.\d+[e-]*\d+') + + allSynths = [] + for i in range(len(linesCPL)): + line = linesCPL[i] + mwm = wm.findall(line)[0][4:-4].split('_') + freq = int(f.findall(line)[0][1:-4]) + delay = float(cpl.findall(line)[0]) + area = float(da.findall(linesDA[i])[0]) + mod = mwm[0] + width = int(mwm[1]) + + power = p.findall(linesP[i]) + lpower = float(power[2]) + denergy = float(power[1])*delay + + oneSynth = [mod, width, freq, delay, area, lpower, denergy] + allSynths += [oneSynth] + + return allSynths + +def getVals(module, var, freq=None): + allSynths = getData(mod=module) + + if (var == 'delay'): + ind = 3 + units = " (ns)" + elif (var == 'area'): + ind = 4 + units = " (sq microns)" + elif (var == 'lpower'): + ind = 5 + units = " (nW)" + elif (var == 'denergy'): + ind = 6 + units = " (pJ)" + else: + error + + widths = [] + metric = [] + if (freq != None): + for oneSynth in allSynths: + if (oneSynth[2] == freq): + widths += [oneSynth[1]] + metric += [oneSynth[ind]] + else: + widths = [8, 16, 32, 64, 128] + for w in widths: + m = 10000 # large number to start + for oneSynth in allSynths: + if (oneSynth[1] == w): + if (oneSynth[3] < m): + m = oneSynth[3] + met = oneSynth[ind] + metric += [met] + return widths, metric, units + +def writeCSV(): + allSynths = getData() + file = open("ppaData.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)']) + + for one in allSynths: + writer.writerow(one) + + file.close() + +def genLegend(fits, coefs, module, r2): + + coefsr = [str(round(c, 3)) for c in coefs] + + eq = '' + ind = 0 + if 'c' in fits: + eq += coefsr[ind] + ind += 1 + if 'l' in fits: + eq += " + " + coefsr[ind] + "*N" + ind += 1 + if 's' in fits: + eq += " + " + coefsr[ind] + "*N^2" + ind += 1 + if 'g' in fits: + eq += " + " + coefsr[ind] + "*log2(N)" + ind += 1 + if 'n' in fits: + eq += " + " + coefsr[ind] + "*Nlog2(N)" + ind += 1 + + legend_elements = [lines.Line2D([0], [0], color='orange', label=eq), + lines.Line2D([0], [0], color='steelblue', ls='', marker='o', label=' R^2='+ str(round(r2, 4)))] + return legend_elements + +def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): + ''' + module: string module name + freq: int freq (MHz) + var: string delay, area, lpower, or denergy + fits: constant, linear, square, log2, Nlog2 + plots chosen variable vs width for all matching syntheses with regression + ''' + widths, metric, units = getVals(module, var, freq=freq) + coefs, r2, funcArr = regress(widths, metric, fits) + + xp = np.linspace(8, 140, 200) + pred = [] + for x in xp: + y = [func(x) for func in funcArr] + pred += [sum(np.multiply(coefs, y))] + + if ax is None: + singlePlot = True + ax = plt.gca() + else: + singlePlot = False + + ax.scatter(widths, metric) + ax.plot(xp, pred, color='orange') + + legend_elements = genLegend(fits, coefs, module, r2) + ax.legend(handles=legend_elements) + + ax.set_xticks(widths) + ax.set_xlabel("Width (bits)") + ax.set_ylabel(str.title(var) + units) + + if singlePlot: + ax.set_title(module + " (target " + str(freq) + "MHz)") + plt.show() + +def regress(widths, var, fits='clsgn'): + + funcArr = genFuncs(fits) + + mat = [] + for w in widths: + row = [] + for func in funcArr: + row += [func(w)] + mat += [row] + + y = np.array(var, dtype=np.float) + coefsResid = np.linalg.lstsq(mat, y, rcond=None) + coefs = coefsResid[0] + try: + resid = coefsResid[1][0] + except: + resid = 0 + r2 = 1 - resid / (y.size * y.var()) + return coefs, r2, funcArr + +def makeCoefTable(): + file = open("ppaFitting.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Metric', 'Freq', '1', 'N', 'N^2', 'log2(N)', 'Nlog2(N)', 'R^2']) + + for mod in ['add', 'mult', 'comparator', 'shifter']: + for comb in [['delay', 5000], ['area', 5000], ['area', 10]]: + var = comb[0] + freq = comb[1] + widths, metric, units = getVals(mod, freq, var) + coefs, r2, funcArr = regress(widths, metric) + row = [mod] + comb + np.ndarray.tolist(coefs) + [r2] + writer.writerow(row) + + file.close() + +def genFuncs(fits='clsgn'): + funcArr = [] + if 'c' in fits: + funcArr += [lambda x: 1] + if 'l' in fits: + funcArr += [lambda x: x] + if 's' in fits: + funcArr += [lambda x: x**2] + if 'g' in fits: + funcArr += [lambda x: np.log2(x)] + if 'n' in fits: + funcArr += [lambda x: x*np.log2(x)] + return funcArr + +def noOutliers(freqs, delays, areas): + f=[] + d=[] + a=[] + try: + med = statistics.median(freqs) + for i in range(len(freqs)): + norm = freqs[i]/med + if (norm > 0.25) & (norm<1.75): + f += [freqs[i]] + d += [delays[i]] + a += [areas[i]] + except: pass + + return f, d, a + +def freqPlot(mod, width): + allSynths = getData(mod=mod, width=width) + + freqsV, delaysV, areasV, freqsA, delaysA, areasA = ([] for i in range(6)) + for oneSynth in allSynths: + if (mod == oneSynth[0]) & (width == oneSynth[1]): + if (1000/oneSynth[3] < oneSynth[2]): + freqsV += [oneSynth[2]] + delaysV += [oneSynth[3]] + areasV += [oneSynth[4]] + else: + freqsA += [oneSynth[2]] + delaysA += [oneSynth[3]] + areasA += [oneSynth[4]] + + freqsV, delaysV, areasV = noOutliers(freqsV, delaysV, areasV) + freqsA, delaysA, areasA = noOutliers(freqsA, delaysA, areasA) + + adprodA = np.multiply(areasA, delaysA) + adsqA = np.multiply(adprodA, delaysA) + adprodV = np.multiply(areasV, delaysV) + adsqV = np.multiply(adprodV, delaysV) + + legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), + lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] + + f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True) + ax1.scatter(freqsA, delaysA, color='green') + ax1.scatter(freqsV, delaysV, color='blue') + ax2.scatter(freqsA, areasA, color='green') + ax2.scatter(freqsV, areasV, color='blue') + ax3.scatter(freqsA, adprodA, color='green') + ax3.scatter(freqsV, adprodV, color='blue') + ax4.scatter(freqsA, adsqA, color='green') + ax4.scatter(freqsV, adsqV, color='blue') + ax1.legend(handles=legend_elements) + ax4.set_xlabel("Target Freq (MHz)") + ax1.set_ylabel('Delay (ns)') + ax2.set_ylabel('Area (sq microns)') + ax3.set_ylabel('Area * Delay') + ax4.set_ylabel('Area * Delay^2') + ax1.set_title(mod + '_' + str(width)) + plt.show() + +def plotPPA(mod, freq=None): + fig, axs = plt.subplots(2, 2) + oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='clg', freq=freq) + oneMetricPlot(mod, 'area', ax=axs[0,1], fits='s', freq=freq) + oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='c', freq=freq) + oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits='s', freq=freq) + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " min delay" + plt.suptitle(mod + titleStr) + plt.show() + +# writeCSV() +# makeCoefTable() + +freqPlot('decoder', 8) + +plotPPA('decoder') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 0919db4ce..c7b4d9496 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,45 +1,803 @@ -Module,Width,Target Freq,Delay,Area -add,16,10,2.032906,221.479998 -add,16,4000,0.249839,551.740010 -add,16,5000,0.228259,924.140017 -add,16,6000,0.225754,1120.140018 -add,32,10,4.160501,456.679995 -add,32,4000,0.280842,1730.680031 -add,32,5000,0.250500,1933.540033 -add,32,6000,0.271774,1746.360030 -add,64,10,8.474034,927.079988 -add,64,4000,0.323267,3758.300065 -add,64,5000,0.334061,3798.480071 -add,64,6000,0.328457,3749.480066 -comparator,16,10,0.576329,252.840005 -comparator,16,4000,0.249312,280.280005 -comparator,16,5000,0.199026,313.600006 -comparator,16,6000,0.166568,422.380007 -comparator,32,10,0.765874,495.880010 -comparator,32,4000,0.249950,608.580012 -comparator,32,5000,0.205372,919.240014 -comparator,32,6000,0.201200,1248.520016 -comparator,64,10,0.561562,1008.420020 -comparator,64,4000,0.249905,1437.660027 -comparator,64,5000,0.219296,2738.120023 -comparator,64,6000,0.221138,2341.220025 -mult,16,10,4.730546,3869.040009 -mult,16,4000,0.821111,9132.620147 -mult,16,5000,0.820059,9583.420143 -mult,16,6000,0.831308,8594.600132 -mult,32,10,7.575772,12412.680067 -mult,32,4000,1.091389,31262.980534 -mult,32,5000,1.092153,31497.200524 -mult,32,6000,1.084816,33519.920555 -mult,64,10,4.793300,46798.920227 -mult,64,4000,1.411752,93087.261425 -mult,64,5000,1.404875,94040.801492 -mult,64,6000,1.415466,89931.661403 -shifter,32,10,1.906335,1656.200032 -shifter,32,10,1.906335,1656.200032 -shifter,32,4000,0.260606,3490.760054 -shifter,32,4000,0.260606,3490.760054 -shifter,32,5000,0.238962,4985.260077 -shifter,32,5000,0.238962,4985.260077 -shifter,32,6000,0.241742,4312.000069 -shifter,32,6000,0.241742,4312.000069 +Module,Width,Target Freq,Delay,Area,L Power (nW),D energy (mJ) +add,128,10,7.100851,1867.879976,465.925,0.035575263509999996 +add,128,1538,0.633294,4623.64009,632.254,0.27231642 +add,128,2051,0.486762,4951.940095,885.884,0.35630978399999996 +add,128,2359,0.423881,5520.340104,1.49,0.451433265 +add,128,2410,0.414767,5600.700103,1.57,0.456658467 +add,128,2462,0.406101,5721.240105,1.77,0.477980877 +add,128,2513,0.397913,6085.800112,2.14,0.516093161 +add,128,2564,0.436395,6456.240111,2.27,0.615753345 +add,128,2615,0.390136,6662.040117,2.45,0.6261682799999999 +add,128,2667,0.394304,7494.060127,3.58,0.76692128 +add,128,2718,0.407908,7287.280117,3.35,0.7693144879999999 +add,128,2769,0.431383,6941.340124,2.86,0.742841526 +add,128,3077,0.387515,7712.60013,2.93,0.9029099500000001 +add,128,3590,0.386891,6860.000114,2.62,0.913836542 +add,128,5000,0.389771,7007.980119,2.77,1.289752239 +add,16,10,2.032906,221.479998,55.29,0.00116892095 +add,16,2609,0.375085,405.720008,52.28,0.028731511 +add,16,3478,0.287131,443.940009,126.253,0.041921126 +add,16,4000,0.249839,551.74001,302.479,0.059711521 +add,16,4087,0.243761,503.720009,183.936,0.050946049 +add,16,4174,0.239287,549.780011,304.811,0.060061037 +add,16,4261,0.234402,607.60001,368.742,0.06680457 +add,16,4348,0.22992,610.540011,364.173,0.06575712 +add,16,4435,0.22545,666.400011,419.709,0.0789075 +add,16,4522,0.222724,820.260016,626.379,0.090871392 +add,16,4609,0.221986,815.360013,735.998,0.091680218 +add,16,4696,0.227412,866.320016,645.684,0.10392728400000001 +add,16,5000,0.228259,924.140017,641.631,0.118466421 +add,16,5217,0.22222,824.180016,601.276,0.10177676000000001 +add,16,6000,0.225754,1120.140018,1.01,0.166832206 +add,16,6087,0.226225,857.500013,678.287,0.14161685000000002 +add,32,10,4.160501,456.679995,112.161,0.00490939118 +add,32,2400,0.41509,958.440019,151.083,0.06848985 +add,32,3200,0.312424,1121.120021,296.836,0.105599312 +add,32,3680,0.271527,1465.100024,591.825,0.149882904 +add,32,3760,0.278449,1689.520028,834.387,0.18739617700000002 +add,32,3840,0.291206,1547.420027,784.112,0.177344454 +add,32,3920,0.273454,2044.280039,1.33,0.23653770999999998 +add,32,4000,0.280842,1730.680031,849.828,0.20641886999999998 +add,32,4080,0.256294,1991.360031,1.24,0.223744662 +add,32,4160,0.253175,2031.540036,1.24,0.231655125 +add,32,4240,0.268332,1829.660028,1.09,0.218958912 +add,32,4320,0.254861,1716.960028,866.723,0.199811024 +add,32,4800,0.258491,1955.100033,1.07,0.27865329800000005 +add,32,5000,0.2505,1933.540033,1.03,0.26277449999999997 +add,32,5600,0.254525,1871.800028,877.446,0.28048655 +add,32,6000,0.271774,1746.36003,955.901,0.309278812 +add,64,10,8.474034,927.079988,230.083,0.02084612364 +add,64,1818,0.538894,2114.840041,250.049,0.1347235 +add,64,2424,0.412474,2298.100044,453.413,0.175713924 +add,64,2788,0.358537,2637.180048,758.693,0.235558809 +add,64,2848,0.351091,2625.420049,698.362,0.23523097 +add,64,2909,0.343753,2800.840049,852.781,0.25368971399999996 +add,64,2970,0.337807,3412.360059,1.37,0.33003743900000004 +add,64,3030,0.331556,3202.640054,1.28,0.311331084 +add,64,3091,0.349251,3284.960053,1.35,0.34331373299999995 +add,64,3152,0.328164,3804.360061,1.89,0.39543762000000005 +add,64,3212,0.336436,3593.660062,1.72,0.38387347600000005 +add,64,3273,0.311119,3816.120062,1.96,0.39947679599999997 +add,64,3636,0.330032,3266.340054,1.22,0.407259488 +add,64,4000,0.323267,3758.300065,1.75,0.492335641 +add,64,4242,0.328234,3507.420063,1.57,0.47003108800000004 +add,64,5000,0.334061,3798.480071,2.18,0.640394937 +add,64,6000,0.328457,3749.480066,1.77,0.770560122 +add,8,10,0.940062,103.879999,24.765,0.000226554942 +add,8,5000,0.199689,197.960003,83.576,0.022564857 +comparator,128,10,0.842074,1997.240039,243.506,0.00073260438 +comparator,128,2308,0.406531,2810.640055,437.781,0.156107904 +comparator,128,3077,0.324985,2559.760047,659.43,0.17159208 +comparator,128,3538,0.282712,3158.540057,1.6,0.26490114400000003 +comparator,128,3615,0.276605,3092.880056,1.5,0.26443437999999997 +comparator,128,3692,0.270828,3380.020055,2.0,0.30170239200000004 +comparator,128,3769,0.27069,3741.640049,2.91,0.34404698999999994 +comparator,128,3846,0.273602,4038.58005,3.61,0.41751665200000004 +comparator,128,3923,0.256043,4153.240051,3.84,0.382528242 +comparator,128,4000,0.268954,4027.800041,3.66,0.44538782400000004 +comparator,128,4077,0.262622,4638.340054,5.12,0.5050221060000001 +comparator,128,4154,0.257245,4649.120047,5.1,0.5502470549999999 +comparator,128,4615,0.265848,4047.400041,3.87,0.49421143199999995 +comparator,128,5000,0.260142,5215.56005,6.0,0.964606536 +comparator,128,5385,0.267095,4787.300045,5.3,1.016830665 +comparator,16,10000,0.146177,1065.260009,1.61,0.182282719 +comparator,16,10,0.576329,252.840005,31.402,8.2991376e-05 +comparator,16,4000,0.249312,280.280005,55.248,0.0144850272 +comparator,16,5000,0.199026,313.600006,78.893,0.0170963334 +comparator,16,5333,0.186933,318.500006,100.145,0.021871161 +comparator,16,6000,0.166568,422.380007,301.506,0.04247484 +comparator,16,6133,0.16297,441.000006,363.571,0.04009062 +comparator,16,6267,0.168782,502.740008,498.843,0.053841457999999995 +comparator,16,6400,0.168782,604.660008,744.154,0.05924248199999999 +comparator,16,6533,0.152969,508.620009,432.277,0.056292591999999995 +comparator,16,6667,0.150575,691.880011,816.855,0.06911392499999999 +comparator,16,6800,0.146926,723.240009,925.474,0.08110315200000001 +comparator,16,6933,0.168782,607.600006,799.51,0.065149852 +comparator,16,7067,0.158772,756.56001,1.05,0.079068456 +comparator,16,7200,0.15891,771.260013,1.09,0.08040846 +comparator,16,8000,0.158838,801.640006,1.19,0.09959142600000001 +comparator,16,9333,0.166546,695.800007,927.014,0.11258509600000001 +comparator,32,10000,0.194087,1451.380013,1.85,0.47415454100000004 +comparator,32,10,0.765874,495.88001,66.41,0.000173087524 +comparator,32,3158,0.304333,684.040013,135.532,0.041084955000000006 +comparator,32,4000,0.24995,608.580012,130.613,0.041991600000000004 +comparator,32,4211,0.237004,654.640013,145.103,0.046926792 +comparator,32,4842,0.206449,781.060011,485.75,0.069986211 +comparator,32,4947,0.2021,882.980013,601.459,0.10488990000000001 +comparator,32,5000,0.205372,919.240014,840.47,0.08830995999999999 +comparator,32,5053,0.197891,805.560012,561.888,0.07302177900000001 +comparator,32,5158,0.197393,1203.440015,1.31,0.14725517800000001 +comparator,32,5263,0.195832,1060.360011,1.06,0.10770760000000001 +comparator,32,5368,0.199678,1110.340013,1.12,0.13638007400000002 +comparator,32,5474,0.192304,1188.740012,1.43,0.137881968 +comparator,32,5579,0.192149,1206.380012,1.44,0.172549802 +comparator,32,5684,0.203736,1218.140014,1.42,0.19762392 +comparator,32,6000,0.2012,1248.520016,1.48,0.1867136 +comparator,32,6316,0.2012,1239.700017,1.45,0.1963712 +comparator,32,7368,0.194845,1391.600021,1.66,0.34799316999999996 +comparator,64,10,0.561562,1008.42002,127.626,0.000252141338 +comparator,64,2727,0.333026,1392.580027,202.012,0.077262032 +comparator,64,3636,0.275001,1323.000026,357.28,0.09707535299999999 +comparator,64,4000,0.249905,1437.660027,558.66,0.11545611 +comparator,64,4182,0.239102,1454.320026,590.635,0.10974781800000001 +comparator,64,4273,0.233995,1568.980027,683.786,0.14297094500000002 +comparator,64,4364,0.229142,1709.120026,1.02,0.17552277200000002 +comparator,64,4455,0.224454,1899.240032,1.34,0.20492650199999998 +comparator,64,4545,0.229482,2235.380032,2.24,0.25931466 +comparator,64,4636,0.215691,2072.700029,1.84,0.210298725 +comparator,64,4727,0.225291,2499.000023,2.71,0.311352162 +comparator,64,4818,0.214579,2591.120026,2.62,0.38087772499999994 +comparator,64,4909,0.213022,2891.980026,3.4,0.401972514 +comparator,64,5000,0.219296,2738.120023,2.95,0.436179744 +comparator,64,5455,0.221407,2929.220025,3.36,0.49750152899999994 +comparator,64,6000,0.221138,2341.220025,2.59,0.296988334 +comparator,64,6364,0.223965,2547.020023,2.94,0.557896815 +comparator,8,10000,0.1136,496.86,810.074,0.07338560000000001 +comparator,8,10909,0.11361,387.1,565.114,0.07293762000000001 +comparator,8,10,0.29577,118.580002,16.053,2.0201091e-05 +comparator,8,12727,0.113615,488.039998,768.445,0.09202815 +comparator,8,5000,0.195502,129.360003,21.443,0.0069989716 +comparator,8,5455,0.182936,130.340003,22.567,0.0072442656 +comparator,8,7273,0.13643,147.980003,61.898,0.01459801 +comparator,8,8364,0.119528,210.700003,172.337,0.026535216 +comparator,8,8545,0.116724,205.800003,165.947,0.027897035999999997 +comparator,8,8727,0.124671,264.600002,278.768,0.038648010000000003 +comparator,8,8909,0.11208,261.660004,251.629,0.03564144 +comparator,8,9091,0.10991,297.920001,343.785,0.038798229999999996 +comparator,8,9273,0.107742,309.680003,356.05,0.041588412000000005 +comparator,8,9455,0.106411,345.94,438.668,0.045969552000000004 +comparator,8,9636,0.111488,397.88,589.556,0.06064947200000001 +comparator,8,9818,0.11361,381.219999,573.131,0.05873637 +decoder,128,11997,0.083125,926.100008,787.251,0.0482125 +decoder,128,12763,0.079353,1086.820012,959.985,0.064910754 +decoder,128,13273,0.100672,959.420012,753.194,0.074799296 +decoder,128,13784,0.080668,1300.460014,1.37,0.09180018399999999 +decoder,128,15000,0.101117,1111.320011,1.04,0.098386841 +decoder,128,15315,0.079077,1283.800018,1.26,0.100269636 +decoder,128,17868,0.101057,1072.12001,985.334,0.113588068 +decoder,128,20000,0.078354,1161.30001,1.13,0.11134103399999999 +decoder,128,7500,0.13242,552.72001,163.224,0.01694976 +decoder,128,7658,0.130462,549.78001,153.219,0.015394515999999999 +decoder,16,12005,0.08179,78.400002,12.174,0.0013904300000000002 +decoder,16,18407,0.052159,98.980002,39.072,0.0038128229 +decoder,16,20000,0.049981,94.080001,66.328,0.003348727 +decoder,16,20008,0.049718,95.060001,70.279,0.0034554010000000003 +decoder,16,21208,0.047148,119.560002,121.799,0.005940648000000001 +decoder,16,21608,0.046101,118.580002,119.754,0.005393817 +decoder,16,22809,0.04375,201.880002,199.593,0.013387499999999998 +decoder,32,10000,0.099725,147.980003,44.83,0.0032510349999999993 +decoder,32,12025,0.081513,166.600003,59.7,0.004646241000000001 +decoder,32,14430,0.068522,191.100004,82.08,0.007126288 +decoder,32,15000,0.066529,175.420003,85.153,0.0062005028 +decoder,32,15332,0.06516,314.580003,249.747,0.0172674 +decoder,32,16234,0.061497,250.880004,167.484,0.012053412000000001 +decoder,32,17000,0.06201,655.62001,900.063,0.049235940000000006 +decoder,32,18000,0.06048,825.160012,1.22,0.0671328 +decoder,32,19000,0.059976,951.580016,1.48,0.08120750400000001 +decoder,32,20000,0.060737,1096.620017,1.73,0.104042481 +decoder,32,21000,0.059192,926.100019,1.38,0.08837365600000001 +decoder,32,25000,0.058416,905.52001,1.34,0.104155728 +decoder,32,7500,0.115541,147.000003,15.758,0.0023801446 +decoder,32,9019,0.104922,155.820003,44.605,0.0071871570000000004 +decoder,64,10000,0.098226,291.060005,96.679,0.009744019199999999 +decoder,64,10511,0.094204,302.820005,116.69,0.011869704 +decoder,64,15000,0.066629,643.86001,638.115,0.038778077999999994 +decoder,64,16117,0.061996,696.780014,775.245,0.041351332000000005 +decoder,64,16467,0.060727,780.080013,923.175,0.050160502 +decoder,64,18920,0.069176,905.520014,1.07,0.081835208 +decoder,64,19270,0.055769,1076.040022,1.56,0.074228539 +decoder,64,20000,0.057083,1052.520018,1.55,0.07826079300000001 +decoder,64,7500,0.131244,264.600005,64.81,0.0040816884 +decoder,8,10000,0.085629,37.240001,2.355,0.00054203157 +decoder,8,10744,0.085629,37.240001,2.355,0.0005822771999999999 +decoder,8,11445,0.085629,37.240001,2.355,0.00061995396 +decoder,8,11678,0.085629,37.240001,2.355,0.00063279831 +decoder,8,11912,0.067612,37.240001,2.814,0.0005233168800000001 +decoder,8,12613,0.067612,37.240001,2.814,0.00055374228 +decoder,8,12846,0.067612,37.240001,2.814,0.0005638840800000001 +decoder,8,13313,0.05554,38.220001,2.007,0.00047153459999999995 +decoder,8,16350,0.05554,38.220001,2.007,0.000577616 +decoder,8,7007,0.085629,37.240001,2.355,0.00037933647 +flop,128,10000,0.067611,2132.47998,1.04,2.047734357 +flop,128,11832,0.067611,2132.47998,1.04,2.422840185 +flop,128,13903,0.067611,2132.47998,1.04,2.846963988 +flop,128,14199,0.067611,2132.47998,1.04,2.907543444 +flop,128,14495,0.067611,2132.47998,1.04,2.9681905110000004 +flop,128,14790,0.067611,2132.47998,1.04,3.0285671339999998 +flop,128,15000,0.067611,2132.47998,1.04,3.0715677300000004 +flop,128,15382,0.067611,2132.47998,1.04,3.1497936570000005 +flop,128,15678,0.067611,2132.47998,1.04,3.210440724 +flop,128,15974,0.067611,2132.47998,1.04,3.2710201800000003 +flop,128,16270,0.067611,2132.47998,1.04,3.3316672470000004 +flop,128,16861,0.067611,2132.47998,1.04,3.4526909370000003 +flop,128,17749,0.067611,2132.47998,1.04,3.6344969160000002 +flop,128,20000,0.067611,2132.47998,1.04,4.095468714 +flop,128,20707,0.067611,2132.47998,1.04,4.240223865000001 +flop,128,8874,0.067611,2132.47998,1.04,1.8171808470000002 +flop,16,10000,0.067611,266.559998,129.629,0.25597524600000005 +flop,16,11832,0.067611,266.559998,129.629,0.30289728000000005 +flop,16,13607,0.067611,266.559998,129.629,0.34833187200000004 +flop,16,13903,0.067611,266.559998,129.629,0.35590430400000006 +flop,16,14199,0.067611,266.559998,129.629,0.363476736 +flop,16,14495,0.067611,266.559998,129.629,0.37104916800000004 +flop,16,14790,0.067611,266.559998,129.629,0.3786216 +flop,16,15000,0.067611,266.559998,129.629,0.38403048 +flop,16,15086,0.067611,266.559998,129.629,0.386194032 +flop,16,15382,0.067611,266.559998,129.629,0.39376646400000004 +flop,16,15678,0.067611,266.559998,129.629,0.401338896 +flop,16,15974,0.067611,266.559998,129.629,0.408911328 +flop,16,16270,0.067611,266.559998,129.629,0.416551371 +flop,16,16861,0.067611,266.559998,129.629,0.43162862400000007 +flop,16,20000,0.067611,266.559998,129.629,0.5120181030000001 +flop,16,20707,0.067611,266.559998,129.629,0.530137851 +flop,16,8874,0.067611,266.559998,129.629,0.22717296 +flop,32,10000,0.067611,533.119995,259.258,0.5119504920000001 +flop,32,11832,0.067611,533.119995,259.258,0.6057945600000001 +flop,32,13607,0.067611,533.119995,259.258,0.6966637440000001 +flop,32,13903,0.067611,533.119995,259.258,0.7118086080000001 +flop,32,14199,0.067611,533.119995,259.258,0.726953472 +flop,32,14495,0.067611,533.119995,259.258,0.7420983360000001 +flop,32,14790,0.067611,533.119995,259.258,0.7572432 +flop,32,15000,0.067611,533.119995,259.258,0.767993349 +flop,32,15086,0.067611,533.119995,259.258,0.772388064 +flop,32,15382,0.067611,533.119995,259.258,0.7875329280000001 +flop,32,15678,0.067611,533.119995,259.258,0.802677792 +flop,32,15974,0.067611,533.119995,259.258,0.817822656 +flop,32,16270,0.067611,533.119995,259.258,0.8329675200000001 +flop,32,16861,0.067611,533.119995,259.258,0.8632572480000001 +flop,32,17749,0.067611,533.119995,259.258,0.90869184 +flop,32,20000,0.067611,533.119995,259.258,1.0239685950000001 +flop,32,20707,0.067611,533.119995,259.258,1.06014048 +flop,32,8874,0.067611,533.119995,259.258,0.45434592 +flop,64,10000,0.067611,1066.23999,518.516,1.0239009840000002 +flop,64,11832,0.067611,1066.23999,518.516,1.211453898 +flop,64,13607,0.067611,1066.23999,518.516,1.393259877 +flop,64,13903,0.067611,1066.23999,518.516,1.423549605 +flop,64,14199,0.067611,1066.23999,518.516,1.4538393330000001 +flop,64,14790,0.067611,1066.23999,518.516,1.514351178 +flop,64,15000,0.067611,1066.23999,518.516,1.5358514760000002 +flop,64,15086,0.067611,1066.23999,518.516,1.5446409060000001 +flop,64,15382,0.067611,1066.23999,518.516,1.5749982450000002 +flop,64,15974,0.067611,1066.23999,518.516,1.635577701 +flop,64,16270,0.067611,1066.23999,518.516,1.665867429 +flop,64,16861,0.067611,1066.23999,518.516,1.7263792740000001 +flop,64,17749,0.067611,1066.23999,518.516,1.8173160690000003 +flop,64,20000,0.067611,1066.23999,518.516,2.0478019680000004 +flop,64,20707,0.067611,1066.23999,518.516,2.120213349 +flop,64,8874,0.067611,1066.23999,518.516,0.9086242290000001 +flop,8,10000,0.067611,133.279999,64.814,0.12798762300000002 +flop,8,11832,0.067611,133.279999,64.814,0.15144864000000002 +flop,8,13607,0.067611,133.279999,64.814,0.17416593600000002 +flop,8,13903,0.067611,133.279999,64.814,0.17801976300000003 +flop,8,14199,0.067611,133.279999,64.814,0.181805979 +flop,8,14790,0.067611,133.279999,64.814,0.1893108 +flop,8,15000,0.067611,133.279999,64.814,0.19201524 +flop,8,15382,0.067611,133.279999,64.814,0.196950843 +flop,8,15678,0.067611,133.279999,64.814,0.200737059 +flop,8,16270,0.067611,133.279999,64.814,0.208309491 +flop,8,20000,0.067611,133.279999,64.814,0.256042857 +flopenr,128,10000,0.172806,6543.460042,3.8,10.839429156 +flopenr,128,20000,0.216852,6351.380048,2.97,26.923043208 +flopenr,128,3472,0.243217,4090.519957,839.91,2.155875488 +flopenr,128,4629,0.196289,4950.960049,2.03,3.966215534 +flopenr,128,5324,0.185184,5635.980017,2.56,6.2853301440000005 +flopenr,128,5440,0.212028,5488.000058,2.66,6.8258174039999995 +flopenr,128,5555,0.180307,5170.47998,1.93,4.730173838 +flopenr,128,5671,0.233427,5740.840082,3.05,8.013782337 +flopenr,128,5787,0.158508,5392.939968,2.19,4.578345072 +flopenr,128,5903,0.204863,5312.580023,2.48,6.196900886999999 +flopenr,128,6018,0.229543,5500.74005,2.85,7.564819108000001 +flopenr,128,6134,0.21139,5399.800032,2.6,7.055986809999999 +flopenr,128,6366,0.202213,5357.660028,2.77,6.433406595 +flopenr,128,6944,0.193452,5612.460024,2.98,7.582351140000001 +flopenr,16,10000,0.150576,864.360014,554.564,1.199940144 +flopenr,16,5313,0.173096,761.460013,502.047,0.735138712 +flopenr,16,6243,0.175796,845.740013,528.22,0.8188577680000001 +flopenr,16,6376,0.163753,774.200016,397.636,0.824332602 +flopenr,16,6508,0.156837,849.660017,412.253,0.82182588 +flopenr,16,6641,0.149304,696.780009,370.215,0.644843976 +flopenr,16,6774,0.157317,775.180016,386.651,0.8381849760000001 +flopenr,16,6907,0.157317,767.340013,356.367,0.808137429 +flopenr,16,7040,0.165641,829.080008,388.122,0.938356265 +flopenr,16,7172,0.149628,879.060014,543.145,0.9070449360000001 +flopenr,16,7305,0.137358,868.28001,441.429,0.8523063900000001 +flopenr,16,7571,0.137358,869.26001,464.962,0.88664589 +flopenr,16,7969,0.147944,824.180012,499.633,0.8990556879999999 +flopenr,16,9298,0.149759,843.780013,503.168,1.0830570880000001 +flopenr,32,10000,0.148623,1697.360016,1.0,2.1431436600000002 +flopenr,32,5383,0.173867,1422.959997,496.365,1.1993345659999999 +flopenr,32,6325,0.165025,1591.520024,806.227,1.567902525 +flopenr,32,6594,0.203857,1608.180028,964.264,2.170057765 +flopenr,32,6728,0.203857,1609.160028,966.958,2.2140908770000003 +flopenr,32,6998,0.171867,1531.740022,763.22,1.88538099 +flopenr,32,7132,0.171867,1533.700022,803.1,1.9216449269999998 +flopenr,32,7267,0.171867,1533.700022,803.1,1.9580807310000001 +flopenr,32,7401,0.168712,1666.000019,919.998,2.046645272 +flopenr,32,7670,0.171392,1666.980017,917.151,2.1948459519999997 +flopenr,32,8074,0.162642,1698.340021,976.973,2.1127195800000003 +flopenr,32,9420,0.175267,1604.260011,885.804,2.4467273200000004 +flopenr,64,15000,0.190554,3254.580017,1.91,8.815409148 +flopenr,64,3149,0.259481,2073.679978,429.405,1.066985872 +flopenr,64,4198,0.190505,2245.179982,539.505,1.02796498 +flopenr,64,4828,0.20165,2733.220049,1.49,3.0547958499999996 +flopenr,64,4933,0.20165,2736.160049,1.49,3.1320278 +flopenr,64,5038,0.198159,2751.840019,1.52,2.6361091770000002 +flopenr,64,5143,0.144251,2331.41998,584.543,1.032404407 +flopenr,64,5248,0.188016,2361.799992,765.172,1.5415431839999998 +flopenr,64,5353,0.193779,2490.180011,929.113,2.116648017 +flopenr,64,5668,0.171704,2479.399988,843.955,2.061649928 +flopenr,64,5983,0.165637,2718.520023,1.43,2.4832299040000003 +flopenr,8,10000,0.145352,404.740009,283.162,0.628938104 +flopenr,8,15000,0.145352,404.740009,283.162,0.9433344800000001 +flopenr,8,20000,0.145352,406.700009,283.303,1.2583122640000002 +flopenr,8,6467,0.145352,399.840009,278.471,0.39303180800000004 +flopenr,8,6742,0.13948,396.900007,259.546,0.40616576 +flopenr,8,7017,0.13948,396.900007,259.546,0.42262439999999996 +flopenr,8,7293,0.13948,396.900007,259.546,0.439362 +flopr,128,10000,0.062982,2642.07999,1.11,1.926808326 +flopr,128,14607,0.142393,2813.579995,1.29,6.316411087 +flopr,128,14925,0.167564,2782.219993,1.13,7.517256168 +flopr,128,15000,0.167143,2783.199993,1.13,7.535475012000001 +flopr,128,15242,0.165883,2788.099993,1.14,7.601090826000001 +flopr,128,15878,0.099791,3011.539997,1.64,5.126962207 +flopr,128,16195,0.094802,3945.479988,1.94,6.82716603 +flopr,128,16513,0.115912,2856.699992,1.43,5.983029704 +flopr,128,16830,0.114707,3323.180002,1.82,6.260593353 +flopr,128,17148,0.124671,3343.760002,1.85,7.328909406 +flopr,128,17465,0.124671,2887.079993,1.28,6.774622140000001 +flopr,128,20000,0.127021,3218.319991,1.56,9.278884049999998 +flopr,128,22229,0.123156,3161.479996,1.9,8.881641252000001 +flopr,128,9527,0.062982,2638.15999,1.12,1.8303199019999998 +flopr,16,10000,0.062982,333.199999,139.534,0.23983545599999997 +flopr,16,12702,0.115814,358.679998,148.002,0.574669068 +flopr,16,14607,0.113143,375.339998,175.379,0.6860991519999999 +flopr,16,15000,0.113143,375.339998,174.193,0.704541461 +flopr,16,15242,0.113143,375.339998,174.193,0.7158557609999999 +flopr,16,15560,0.113143,375.339998,175.379,0.73090378 +flopr,16,15878,0.099791,416.5,246.045,0.7232851680000001 +flopr,16,16195,0.099791,382.199999,188.76,0.691651421 +flopr,16,16513,0.099791,416.5,246.045,0.7522245580000001 +flopr,16,16830,0.108065,395.919998,188.407,0.82259078 +flopr,16,17465,0.108065,395.919998,188.407,0.853605435 +flopr,16,18100,0.108065,395.919998,188.407,0.8847281549999999 +flopr,16,19053,0.108065,395.919998,188.407,0.93130417 +flopr,16,20000,0.108255,379.259998,180.305,0.92817837 +flopr,32,10000,0.062982,662.479998,278.385,0.479985822 +flopr,32,14607,0.115814,758.519997,356.88,1.42798662 +flopr,32,14925,0.119136,752.639997,345.5,1.474784544 +flopr,32,15000,0.118028,734.019997,342.052,1.427312604 +flopr,32,15242,0.118028,734.019997,342.052,1.450328064 +flopr,32,15560,0.118028,733.039997,339.995,1.4795990079999999 +flopr,32,15878,0.112493,734.999998,361.292,1.425511296 +flopr,32,16513,0.10078,870.240001,483.787,1.38441486 +flopr,32,17148,0.10078,882.000001,496.236,1.44407662 +flopr,32,17465,0.10078,882.000001,496.236,1.47058176 +flopr,32,18100,0.10078,882.000001,496.236,1.5240959399999998 +flopr,32,19053,0.116921,746.759997,361.146,1.8577577689999998 +flopr,32,20000,0.108065,785.959998,399.268,1.8580696099999998 +flopr,32,22229,0.111852,1144.640004,1.28,2.2861430279999997 +flopr,32,9527,0.062982,662.479998,281.256,0.45756422999999996 +flopr,64,10000,0.062982,1322.999995,556.428,0.960664446 +flopr,64,12702,0.132352,1459.219998,678.198,2.6371136 +flopr,64,14607,0.138259,1454.319996,669.613,3.206917505 +flopr,64,14925,0.138259,1444.519997,668.83,3.258073335 +flopr,64,15000,0.138849,1420.999997,658.22,3.23795868 +flopr,64,15242,0.138849,1420.999997,654.663,3.290165904 +flopr,64,15560,0.138849,1417.079997,651.791,3.327932832 +flopr,64,16195,0.099791,1619.939998,931.738,2.7440529180000004 +flopr,64,16830,0.116921,1449.419994,603.364,3.104486392 +flopr,64,17148,0.099791,1623.859998,924.887,2.881864289 +flopr,64,17465,0.099791,1631.699998,936.964,2.9331568630000002 +flopr,64,18100,0.099791,1523.899996,774.939,3.014386737 +flopr,64,19053,0.116921,1538.599995,761.87,3.823199779 +flopr,64,20000,0.116921,1538.599995,761.897,4.013313325 +flopr,64,22229,0.116921,1772.819999,1.35,4.520516623 +flopr,64,9527,0.062982,1321.039995,556.087,0.9183405419999999 +flopr,8,10000,0.062982,168.559999,70.109,0.11991772799999999 +flopr,8,15000,0.103061,189.139999,87.938,0.33103193200000003 +flopr,8,15242,0.103061,189.139999,89.124,0.336494165 +flopr,8,15560,0.103061,189.139999,89.124,0.343502313 +flopr,8,15878,0.099791,205.799999,97.226,0.376910607 +flopr,8,16513,0.099791,205.799999,97.226,0.391979048 +flopr,8,18100,0.099791,205.799999,97.226,0.429700046 +flopr,8,19053,0.099791,205.799999,97.226,0.452252812 +flopr,8,20000,0.099791,205.799999,97.226,0.474805578 +flopr,8,9527,0.062982,168.559999,70.109,0.114249348 +floprasync,128,10000,0.067064,2892.960056,1.29,2.020772448 +floprasync,128,11929,0.067064,2892.960056,1.29,2.4104813519999997 +floprasync,128,13718,0.011172,2897.860056,1.29,0.462230328 +floprasync,128,14016,0.009129,2898.840056,1.29,0.385919346 +floprasync,128,14315,0.009129,2898.840056,1.29,0.394153704 +floprasync,128,14613,0.008449,2899.820056,1.29,0.37238967500000003 +floprasync,128,14911,0.067064,2906.680056,1.31,3.01687404 +floprasync,128,15209,0.067064,2981.160052,1.48,3.0848098719999997 +floprasync,128,15508,0.067064,2981.160052,1.48,3.145502792 +floprasync,128,15806,0.067064,2981.160052,1.48,3.205927456 +floprasync,128,16104,0.067064,2981.160052,1.48,3.2663521199999996 +floprasync,128,16999,0.067064,2981.160052,1.48,3.447894368 +floprasync,128,17893,0.067064,2981.160052,1.48,3.629235424 +floprasync,128,20876,0.067064,2981.160052,1.48,4.234286832 +floprasync,128,8947,0.067064,2892.960056,1.29,1.8079783759999999 +floprasync,16,10000,0.067064,362.600007,161.167,0.250618168 +floprasync,16,11929,0.067064,362.600007,161.167,0.298971312 +floprasync,16,13718,0.011172,367.500007,163.187,0.057491112 +floprasync,16,14315,0.009129,368.480007,165.173,0.049031859000000004 +floprasync,16,14613,0.008449,369.460007,167.159,0.046334316 +floprasync,16,14911,0.067064,376.320006,185.036,0.375960784 +floprasync,16,15508,0.067064,421.400004,288.357,0.396214112 +floprasync,16,16104,0.067064,421.400004,288.357,0.41143764 +floprasync,16,16402,0.067064,421.400004,288.357,0.419015872 +floprasync,16,16999,0.067064,421.400004,288.357,0.434306464 +floprasync,16,17893,0.067064,421.400004,288.357,0.45710822399999995 +floprasync,16,20876,0.067064,421.400004,288.357,0.5333599920000001 +floprasync,16,8947,0.067064,362.600007,161.167,0.22426201599999998 +floprasync,32,14607,0.008449,730.100014,327.985,0.09319247 +floprasync,32,14925,0.067064,750.680013,369.73,0.758896224 +floprasync,32,15242,0.067064,782.040011,449.182,0.778210656 +floprasync,32,15560,0.067064,782.040011,449.182,0.794440144 +floprasync,32,15878,0.067064,782.040011,449.182,0.810669632 +floprasync,32,16195,0.067064,782.040011,449.182,0.826832056 +floprasync,32,16513,0.067064,782.040011,449.182,0.843061544 +floprasync,32,16830,0.067064,782.040011,449.182,0.8592239679999999 +floprasync,32,17148,0.067064,782.040011,449.182,0.8755205199999999 +floprasync,32,17465,0.067064,782.040011,449.182,0.8916829439999999 +floprasync,32,18100,0.067064,782.040011,449.182,0.924074856 +floprasync,32,9527,0.067064,723.240014,321.992,0.48118419999999995 +floprasync,64,12702,0.067064,1446.480028,643.984,1.283202576 +floprasync,64,14607,0.008449,1453.340028,649.976,0.186342695 +floprasync,64,14925,0.067064,1473.920027,691.722,1.5131650319999999 +floprasync,64,15242,0.067064,1505.280025,771.174,1.548440696 +floprasync,64,15560,0.067064,1505.280025,771.174,1.5807655440000001 +floprasync,64,15878,0.067064,1505.280025,771.174,1.613090392 +floprasync,64,16513,0.067064,1505.280025,771.174,1.67760596 +floprasync,64,16830,0.067064,1505.280025,771.174,1.70979668 +floprasync,64,17148,0.067064,1505.280025,771.174,1.742054464 +floprasync,64,17465,0.067064,1505.280025,771.174,1.774312248 +floprasync,64,18100,0.067064,1505.280025,771.174,1.838827816 +floprasync,64,19053,0.067064,1505.280025,771.174,1.9356011679999998 +floprasync,64,22229,0.067064,1505.280025,771.174,2.258246072 +floprasync,64,9527,0.067064,1446.480028,643.984,0.962100144 +floprasync,8,10000,0.067064,182.280004,80.754,0.125208488 +floprasync,8,13718,0.067064,182.280004,80.754,0.17175090399999998 +floprasync,8,14315,0.067064,182.280004,80.754,0.17919500800000002 +floprasync,8,14613,0.067064,182.280004,80.754,0.18295059200000002 +floprasync,8,15000,0.067064,211.680002,144.349,0.190931208 +floprasync,8,15209,0.067064,211.680002,144.349,0.193613768 +floprasync,8,15806,0.067064,211.680002,144.349,0.20119199999999998 +floprasync,8,16104,0.067064,211.680002,144.349,0.205014648 +floprasync,8,17893,0.067064,211.680002,144.349,0.22781640799999997 +floprasync,8,20000,0.067064,211.680002,144.349,0.25464200800000003 +floprasync,8,8947,0.067064,182.280004,80.754,0.11199688 +mult,128,10,9.334627,180734.540854,1.8,3.9952203559999995 +mult,128,337,2.963253,201889.800086,2.67,45.050335358999995 +mult,128,449,2.227145,212055.340673,3.27,49.890275145000004 +mult,128,5000,1.78322,314617.244472,1.63,1778.4766348 +mult,128,517,1.934229,243417.302347,5.67,87.74436435599999 +mult,128,528,1.893939,255011.682875,6.65,103.378766376 +mult,128,539,1.855281,259737.242949,7.18,109.125773139 +mult,128,551,1.814879,274624.423573,8.73,127.507953903 +mult,128,562,1.779353,284850.723775,1.03,150.1773932 +mult,128,573,1.745187,296812.604204,1.08,142.41074957400002 +mult,128,584,1.712328,298800.044147,1.15,149.236234512 +mult,128,596,1.71139,312992.404301,1.44,170.14468241 +mult,128,607,1.707473,305974.624156,1.38,168.524170154 +mult,128,674,1.727276,311582.184447,1.52,220.7890547 +mult,128,787,1.735561,317542.544465,1.66,268.93559031599995 +mult,16,10,4.730546,3869.040009,641.517,0.0506168422 +mult,16,1122,0.891172,6478.780105,3.54,2.76708906 +mult,16,1146,0.87258,7193.200125,4.57,3.2241831 +mult,16,1171,0.853963,7258.860127,4.57,3.119526839 +mult,16,1195,0.836814,7685.16012,5.33,3.2225707139999997 +mult,16,1220,0.81966,8829.800131,6.95,3.5007678600000003 +mult,16,1244,0.822616,8780.800145,7.15,3.46321336 +mult,16,1268,0.802449,9789.220166,8.8,3.968110305 +mult,16,1293,0.813903,9702.000166,8.74,3.7960435919999997 +mult,16,1317,0.805748,10366.440177,1.01,4.222925268 +mult,16,1463,0.83466,8521.100128,6.71,4.39281558 +mult,16,1707,0.829615,8563.24013,6.78,5.20334528 +mult,16,4000,0.821111,9132.620147,8.03,11.829746177 +mult,16,5000,0.820059,9583.420143,8.5,16.544690325 +mult,16,6000,0.831308,8594.600132,7.15,17.545586648000004 +mult,16,732,1.36399,4043.480026,624.48,0.66017116 +mult,16,976,1.024406,4960.760064,1.32,1.185237742 +mult,32,1000,1.099618,29507.800463,2.24,16.776871826 +mult,32,10,7.575772,12412.680067,1.18,0.1734851788 +mult,32,1111,1.092041,31649.100517,2.53,19.255958953 +mult,32,1296,1.097292,30544.640517,2.37,22.420967435999998 +mult,32,4000,1.091389,31262.980534,2.49,71.454329219 +mult,32,5000,1.092153,31497.200524,2.58,86.885139762 +mult,32,556,1.796075,14371.700056,2.21,2.710277175 +mult,32,6000,1.084816,33519.920555,2.91,112.601731168 +mult,32,741,1.349466,17389.120212,4.65,5.9956774379999995 +mult,32,852,1.173643,23514.120391,1.27,12.269263922 +mult,32,870,1.149401,25198.740416,1.5,13.454888105999999 +mult,32,889,1.124838,26822.600434,1.8,14.631892703999998 +mult,32,907,1.102529,29124.620481,2.08,14.771683542000002 +mult,32,926,1.101021,31000.340484,2.46,15.033340734000001 +mult,32,944,1.085045,32407.620517,2.68,16.47315319 +mult,32,963,1.089271,32490.92054,2.7,16.995895413000003 +mult,32,981,1.091413,33127.920535,2.84,18.800680338 +mult,64,1000,1.350119,103523.281624,7.3,80.49409478 +mult,64,10,4.7933,46798.920227,5.46,0.49370990000000003 +mult,64,4000,1.411752,93087.261425,6.05,321.704398752 +mult,64,429,2.326205,53642.260108,7.4,11.089019235 +mult,64,5000,1.404875,94040.801492,6.16,419.589801625 +mult,64,571,1.751186,58587.340388,1.1,15.692377746 +mult,64,6000,1.415466,89931.661403,5.63,477.43951273199997 +mult,64,657,1.52205,69763.260863,2.39,33.567290699999994 +mult,64,671,1.490298,74604.461058,2.89,39.279784385999996 +mult,64,686,1.457722,78293.181181,3.18,41.225835882 +mult,64,700,1.428547,82949.161302,3.92,47.333476298 +mult,64,714,1.400528,87215.101373,4.39,49.643115488 +mult,64,729,1.371734,93726.221523,5.35,53.37005473799999 +mult,64,743,1.345895,95943.961579,5.62,54.919245475000004 +mult,64,757,1.341232,106627.921626,7.73,59.02762032 +mult,64,771,1.341474,98844.761554,6.33,57.983872176 +mult,64,857,1.336163,107976.401664,7.95,68.108236599 +mult,8,1091,0.915221,1167.180013,211.892,0.170231106 +mult,8,10,2.076433,1009.399998,211.637,0.004277451980000001 +mult,8,1455,0.687251,1615.04003,680.207,0.42334661599999995 +mult,8,1673,0.611485,2094.260033,1.39,0.65428895 +mult,8,1709,0.599356,2453.920037,2.01,0.8540823000000001 +mult,8,1745,0.589521,2771.440043,2.58,0.864827307 +mult,8,1782,0.582418,2549.960043,2.14,0.9091544979999999 +mult,8,1818,0.581954,2672.460046,2.2,0.91657755 +mult,8,1855,0.605444,2332.40004,1.74,0.8476216 +mult,8,1891,0.605341,2405.90004,1.93,0.869875017 +mult,8,1927,0.574177,3273.200051,3.43,1.0622274500000002 +mult,8,1964,0.585681,2746.940044,2.48,1.009714044 +mult,8,2182,0.550085,4360.02008,5.2,1.393365305 +mult,8,2545,0.564127,4034.66007,4.58,1.690124492 +mult,8,5000,0.552339,4261.040075,5.05,3.0616150770000004 +mux2,1,10,0.060639,6.86,1.19,3.1229084999999996e-07 +mux2,1,10,0.060639,6.86,1.19,3.1229084999999996e-07 +priorityencoder,128,10000,0.113763,1058.400021,117.974,0.029692143 +priorityencoder,128,12306,0.113763,1058.400021,117.974,0.036631686000000004 +priorityencoder,128,20000,0.113763,1058.400021,117.974,0.059498049000000004 +priorityencoder,128,7032,0.113763,1058.400021,117.974,0.020932392 +priorityencoder,128,7500,0.113763,1058.400021,117.974,0.022297548 +priorityencoder,128,9493,0.113763,1058.400021,117.974,0.028213224000000002 +priorityencoder,128,9669,0.113763,1058.400021,117.974,0.028782039000000002 +priorityencoder,16,10153,0.104403,159.740003,39.177,0.007715381699999999 +priorityencoder,16,10345,0.104403,159.740003,39.177,0.007861545900000001 +priorityencoder,16,10536,0.104403,159.740003,39.177,0.0080077101 +priorityencoder,16,10919,0.104403,159.740003,39.177,0.0082895982 +priorityencoder,16,11494,0.104403,159.740003,39.177,0.0087280908 +priorityencoder,16,15000,0.104403,159.740003,39.177,0.011379927 +priorityencoder,16,7500,0.104403,159.740003,39.177,0.0057004038 +priorityencoder,16,7663,0.104403,159.740003,39.177,0.0058256874 +priorityencoder,16,8812,0.104403,159.740003,39.177,0.0066922323 +priorityencoder,16,9004,0.104403,159.740003,39.177,0.0068383965 +priorityencoder,16,9195,0.104403,159.740003,39.177,0.0069845607 +priorityencoder,32,10000,0.111067,293.020006,53.82,0.011217767 +priorityencoder,32,10264,0.111067,293.020006,53.82,0.011439900999999999 +priorityencoder,32,10804,0.111067,293.020006,53.82,0.012106303 +priorityencoder,32,12605,0.111067,293.020006,53.82,0.014105509 +priorityencoder,32,15000,0.111067,293.020006,53.82,0.016771117 +priorityencoder,32,5402,0.111067,293.020006,53.82,0.0060309381 +priorityencoder,32,7203,0.111067,293.020006,53.82,0.0080412508 +priorityencoder,32,8283,0.111067,293.020006,53.82,0.0092518811 +priorityencoder,32,8463,0.111067,293.020006,53.82,0.0094518017 +priorityencoder,32,8643,0.111067,293.020006,53.82,0.0096517223 +priorityencoder,32,8824,0.111067,293.020006,53.82,0.0098516429 +priorityencoder,32,9004,0.111067,293.020006,53.82,0.0100515635 +priorityencoder,32,9184,0.111067,293.020006,53.82,0.0102514841 +priorityencoder,32,9364,0.111067,293.020006,53.82,0.0104514047 +priorityencoder,32,9544,0.111067,293.020006,53.82,0.010662432 +priorityencoder,32,9724,0.111067,293.020006,53.82,0.0108623526 +priorityencoder,32,9904,0.111067,293.020006,53.82,0.011062273199999998 +priorityencoder,64,5336,0.112447,546.840011,77.149,0.0092094093 +priorityencoder,64,7114,0.112447,546.840011,77.149,0.012256723 +priorityencoder,64,7500,0.112447,546.840011,77.149,0.012931405000000002 +priorityencoder,64,8182,0.112447,546.840011,77.149,0.014168322 +priorityencoder,64,8359,0.112447,546.840011,77.149,0.014393216 +priorityencoder,64,9071,0.112447,546.840011,77.149,0.015630133 +priorityencoder,64,9249,0.112447,546.840011,77.149,0.015967474 +priorityencoder,64,9605,0.112447,546.840011,77.149,0.016529709 +priorityencoder,64,9782,0.112447,546.840011,77.149,0.01686705 +priorityencoder,8,10000,0.104625,85.260002,26.481,0.006183337499999999 +priorityencoder,8,10131,0.104625,85.260002,26.481,0.0062670375 +priorityencoder,8,10323,0.104625,85.260002,26.481,0.0063925875 +priorityencoder,8,10896,0.104625,85.260002,26.481,0.006737849999999999 +priorityencoder,8,11470,0.104625,85.260002,26.481,0.0070935749999999995 +priorityencoder,8,13381,0.104625,85.260002,26.481,0.008275837500000001 +priorityencoder,8,7646,0.104625,85.260002,26.481,0.004729049999999999 +priorityencoder,8,8984,0.104625,85.260002,26.481,0.0055555875 +priorityencoder,8,9176,0.104625,85.260002,26.481,0.0056811375 +priorityencoder,8,9558,0.104625,85.260002,26.481,0.0059113125 +priorityencoder,8,9749,0.104625,85.260002,26.481,0.0060368625 +priorityencoder,8,9940,0.104625,85.260002,26.481,0.00615195 +priorityonehot,128,10000,0.273337,2507.820036,1.19,0.285090491 +priorityonehot,128,2222,0.449659,1317.120025,366.819,0.0218084615 +priorityonehot,128,2963,0.337291,1562.120028,493.695,0.0313006048 +priorityonehot,128,3407,0.293484,1910.02003,670.082,0.053707572 +priorityonehot,128,3481,0.287273,2149.14003,1.01,0.069232793 +priorityonehot,128,3556,0.281206,2041.340031,721.584,0.060740496000000005 +priorityonehot,128,3630,0.27774,2218.720036,971.079,0.07443432 +priorityonehot,128,3704,0.276108,2448.040034,1.37,0.09001120800000001 +priorityonehot,128,3778,0.264659,2299.080036,975.931,0.07516315599999998 +priorityonehot,128,3852,0.271881,2556.820035,1.37,0.10059596999999999 +priorityonehot,128,3926,0.258274,2524.480033,1.28,0.09349518799999999 +priorityonehot,128,4000,0.253946,2661.680036,1.33,0.10157840000000001 +priorityonehot,128,4074,0.262056,2578.380038,1.58,0.11268408 +priorityonehot,128,4222,0.263015,2585.240036,1.32,0.10257585 +priorityonehot,128,4444,0.270608,2401.980038,1.12,0.10716076800000002 +priorityonehot,128,5000,0.276002,2397.080033,1.14,0.12337289400000001 +priorityonehot,128,5185,0.274609,2437.260036,1.21,0.131537711 +priorityonehot,128,7500,0.265066,2435.300034,1.21,0.183690738 +priorityonehot,16,10000,0.099923,281.260004,117.94,0.012790144 +priorityonehot,16,10222,0.097791,313.600004,134.808,0.014864232 +priorityonehot,16,10444,0.098367,271.460003,84.711,0.014558315999999998 +priorityonehot,16,10667,0.09706,282.240005,85.616,0.01717962 +priorityonehot,16,10889,0.091727,365.540004,454.516,0.019446124 +priorityonehot,16,11111,0.089821,300.860005,305.978,0.014640823 +priorityonehot,16,11333,0.088202,338.100002,367.782,0.017111188 +priorityonehot,16,11556,0.090809,382.200008,391.295,0.023791958000000002 +priorityonehot,16,11778,0.094501,290.080006,108.636,0.017766188 +priorityonehot,16,12000,0.093589,291.060006,116.96,0.018062677000000003 +priorityonehot,16,12222,0.095549,368.480004,319.793,0.026467073 +priorityonehot,16,12667,0.085601,696.78001,1.08,0.050675792 +priorityonehot,16,13333,0.077249,976.080015,1.55,0.079720968 +priorityonehot,16,15000,0.086192,739.900005,1.11,0.067143568 +priorityonehot,16,15556,0.088601,610.540002,811.656,0.058742463 +priorityonehot,16,20000,0.088596,668.36001,947.549,0.08363462399999999 +priorityonehot,16,25000,0.086374,701.680009,963.103,0.11124971200000001 +priorityonehot,16,5000,0.196212,130.340003,29.8,0.0023937864000000003 +priorityonehot,16,6667,0.147215,152.880003,35.496,0.0039600835 +priorityonehot,16,7500,0.131703,194.040003,81.795,0.0086133762 +priorityonehot,16,8889,0.11233,198.940003,56.451,0.007571042 +priorityonehot,32,10000,0.133112,964.320008,797.215,0.07241292800000002 +priorityonehot,32,15000,0.140665,681.100009,546.147,0.07609976500000001 +priorityonehot,32,20000,0.136421,673.260008,406.575,0.10599911699999999 +priorityonehot,32,25000,0.140143,613.480007,367.99,0.11407640199999998 +priorityonehot,32,4000,0.248804,332.220006,108.841,0.008334934 +priorityonehot,32,5000,0.199515,362.600007,102.444,0.008818563 +priorityonehot,32,5333,0.186576,407.680007,135.997,0.0138625968 +priorityonehot,32,6133,0.162922,442.960006,148.282,0.015493882200000001 +priorityonehot,32,6267,0.161707,596.82001,462.029,0.026681655 +priorityonehot,32,6400,0.156239,552.720007,285.787,0.020936026 +priorityonehot,32,6533,0.153004,593.88001,232.761,0.025551668000000003 +priorityonehot,32,6667,0.149833,623.280007,316.846,0.025771275999999996 +priorityonehot,32,6800,0.152882,730.100008,561.099,0.040360848 +priorityonehot,32,6933,0.148938,630.14001,363.804,0.027702467999999997 +priorityonehot,32,7067,0.141491,1078.980015,1.58,0.065510333 +priorityonehot,32,7200,0.143094,1101.520018,1.47,0.07297794 +priorityonehot,32,7333,0.153523,663.46001,318.025,0.037920181 +priorityonehot,32,7500,0.15352,670.320007,335.87,0.04160392 +priorityonehot,32,7600,0.145454,656.600009,371.544,0.035781684 +priorityonehot,32,8000,0.145441,1137.780016,1.52,0.07650196599999999 +priorityonehot,32,9333,0.144083,845.740013,862.939,0.067430844 +priorityonehot,64,10000,0.209855,1194.620015,760.611,0.10597677500000001 +priorityonehot,64,2857,0.34852,702.660012,180.97,0.015056064000000001 +priorityonehot,64,3810,0.262388,851.620013,233.218,0.024795666 +priorityonehot,64,4381,0.22809,942.760013,344.503,0.03033597 +priorityonehot,64,4476,0.223289,1068.200015,670.986,0.038182419 +priorityonehot,64,4571,0.220784,1016.260015,474.392,0.03753328 +priorityonehot,64,4667,0.220552,1039.780015,503.937,0.041243224 +priorityonehot,64,4762,0.212289,1107.400013,650.606,0.043519245 +priorityonehot,64,4857,0.20832,1169.140015,786.702,0.048121920000000006 +priorityonehot,64,4952,0.215228,1318.100022,1.11,0.069518644 +priorityonehot,64,5000,0.207597,1187.760016,764.739,0.053352429 +priorityonehot,64,5048,0.220929,1048.600015,648.313,0.046616018999999995 +priorityonehot,64,5143,0.220683,1064.280016,459.708,0.04590206399999999 +priorityonehot,64,5238,0.210273,1174.040018,697.959,0.05467098 +priorityonehot,64,5429,0.233158,1061.340017,622.371,0.05432581400000001 +priorityonehot,64,5714,0.218253,1192.660017,537.877,0.05936481600000001 +priorityonehot,64,6667,0.226349,1288.700018,1.12,0.082391036 +priorityonehot,64,7500,0.224494,1243.620017,948.965,0.085756708 +priorityonehot,8,10000,0.099885,59.780001,9.529,0.001478298 +priorityonehot,8,12000,0.076956,63.700001,16.155,0.0018700307999999998 +priorityonehot,8,15000,0.065937,73.500001,15.316,0.0030792578999999996 +priorityonehot,8,16000,0.061645,82.320002,24.568,0.0042226825 +priorityonehot,8,18400,0.054629,109.760001,31.371,0.007702688999999999 +priorityonehot,8,18800,0.054102,127.400002,42.783,0.009089136 +priorityonehot,8,19200,0.05415,142.100001,48.939,0.01083 +priorityonehot,8,19600,0.054151,189.14,207.102,0.015053978 +priorityonehot,8,20000,0.054151,141.120002,52.37,0.011480012 +priorityonehot,8,20400,0.054151,145.040002,58.857,0.011967371 +priorityonehot,8,20800,0.054084,154.840002,56.302,0.013412832 +priorityonehot,8,21200,0.054084,157.780003,56.585,0.01406184 +priorityonehot,8,21600,0.054084,157.780003,56.585,0.014332260000000001 +priorityonehot,8,22000,0.054084,157.780003,56.585,0.014602680000000002 +priorityonehot,8,22800,0.054084,157.780003,56.585,0.015143520000000002 +priorityonehot,8,24000,0.054084,159.740003,61.953,0.016008863999999998 +priorityonehot,8,25000,0.054084,158.760003,59.967,0.016549704 +priorityonehot,8,28000,0.054102,177.380002,118.676,0.021045677999999998 +priorityonehot,8,5000,0.196969,53.900001,8.712,0.0012566622200000002 +priorityonehot,8,7500,0.132247,56.840001,8.114,0.0015076158000000002 +shifter,128,10,2.758726,9722.580189,720.698,0.021766348139999996 +shifter,128,5000,0.401118,19106.080347,1.23,2.78375892 +shifter,16,10,1.237745,681.100013,52.029,0.000545845545 +shifter,16,5000,0.209586,2120.720031,2.15,0.21482564999999998 +shifter,32,10,1.906335,1656.200032,118.773,0.00219228525 +shifter,32,4000,0.260606,3490.760054,2.57,0.33409689200000003 +shifter,32,4000,0.260606,3490.760054,2.57,0.33409689200000003 +shifter,32,4000,0.260606,3490.760054,2.57,0.33409689200000003 +shifter,32,5000,0.238962,4985.260077,4.9,0.594776418 +shifter,32,6000,0.241742,4312.000069,3.71,0.582839962 +shifter,32,6000,0.241742,4312.000069,3.71,0.582839962 +shifter,32,6000,0.241742,4312.000069,3.71,0.582839962 +shifter,64,10,2.919486,4346.300085,210.734,0.008670873420000001 +shifter,64,5000,0.358993,9471.700156,6.94,1.621930374 +shifter,8,10,0.622998,244.020005,26.943,0.00011836962000000002 +shifter,8,5000,0.198885,495.88001,300.128,0.056682224999999996 +shiftleft,128,10000,0.313996,12023.620188,9.23,3.370119068 +shiftleft,128,1935,0.516184,5594.820107,768.953,0.30712947999999995 +shiftleft,128,2581,0.387267,7361.76014,2.47,0.42405736499999996 +shiftleft,128,2968,0.33687,9142.420162,5.66,0.76772673 +shiftleft,128,3032,0.329767,9579.500162,6.25,0.817492393 +shiftleft,128,3097,0.322855,8849.400141,5.95,0.731266575 +shiftleft,128,3161,0.321225,10330.180176,7.53,0.9106728749999999 +shiftleft,128,3226,0.320064,10597.720193,7.05,0.893618688 +shiftleft,128,3290,0.314992,10979.920188,8.05,0.985609968 +shiftleft,128,3355,0.309977,11750.200195,9.57,1.06012134 +shiftleft,128,3419,0.302549,10925.040179,7.55,0.99236072 +shiftleft,128,3484,0.313597,11188.660188,8.59,1.077519292 +shiftleft,128,3871,0.303026,12747.840208,1.16,1.410889056 +shiftleft,128,4516,0.309266,12621.420203,1.12,1.610038796 +shiftleft,128,5000,0.319285,11347.420196,8.66,1.5265015849999999 +shiftleft,128,7500,0.32019,11850.160206,9.18,2.42896134 +shiftleft,16,10000,0.128994,1192.660017,1.42,0.132734826 +shiftleft,16,10769,0.131174,1153.460019,1.35,0.133666306 +shiftleft,16,4615,0.215535,446.880008,113.608,0.023493315 +shiftleft,16,5000,0.198416,468.440009,148.45,0.025397248 +shiftleft,16,6154,0.162492,802.620013,641.83,0.057847152 +shiftleft,16,7077,0.141279,1079.960019,1.18,0.08321333099999999 +shiftleft,16,7231,0.138234,1233.820018,1.4,0.09773143799999999 +shiftleft,16,7385,0.135404,937.860017,965.452,0.068514424 +shiftleft,16,7500,0.133331,1031.940019,1.06,0.088265122 +shiftleft,16,7538,0.132481,971.180015,992.057,0.07418936 +shiftleft,16,7692,0.130257,1033.900012,1.06,0.08049882600000001 +shiftleft,16,7846,0.127358,935.900016,874.844,0.079344034 +shiftleft,16,8000,0.124837,968.240013,940.706,0.073029645 +shiftleft,16,8154,0.128748,1062.320016,1.07,0.086518656 +shiftleft,16,8308,0.12432,1199.520016,1.3,0.10057488 +shiftleft,16,9231,0.113513,1695.400019,2.27,0.149950673 +shiftleft,32,10000,0.15971,3675.98006,4.09,0.5206546 +shiftleft,32,3750,0.266551,1173.060021,319.774,0.059174321999999994 +shiftleft,32,5000,0.199946,2419.620024,2.11,0.21554178800000004 +shiftleft,32,5750,0.173824,2582.30004,2.29,0.204764672 +shiftleft,32,5875,0.169973,2781.240046,2.63,0.22385444100000002 +shiftleft,32,6000,0.169263,2872.380041,2.88,0.24272314199999998 +shiftleft,32,6125,0.163188,2892.960045,2.74,0.235317096 +shiftleft,32,6250,0.159977,2964.500038,3.13,0.268121452 +shiftleft,32,6375,0.159792,3330.040049,3.53,0.296573952 +shiftleft,32,6500,0.158323,3294.760046,3.49,0.29020605899999996 +shiftleft,32,6625,0.155982,3619.14005,4.14,0.331617732 +shiftleft,32,6750,0.156124,3323.180043,3.58,0.30288056 +shiftleft,32,7500,0.166296,3306.520048,3.7,0.35171604 +shiftleft,32,8750,0.164673,3752.420048,4.46,0.47178814500000005 +shiftleft,64,10000,0.23373,6486.620108,6.06,1.38251295 +shiftleft,64,2609,0.382901,2559.760048,666.022,0.14205627099999998 +shiftleft,64,3478,0.287377,3864.140062,2.25,0.304044866 +shiftleft,64,4000,0.249988,4733.400082,3.49,0.366982384 +shiftleft,64,4087,0.244635,4460.960079,2.81,0.336373125 +shiftleft,64,4174,0.239544,5090.120088,4.17,0.440281872 +shiftleft,64,4261,0.234657,5289.060089,3.95,0.45171472500000004 +shiftleft,64,4348,0.23035,5490.940094,4.5,0.49456144999999996 +shiftleft,64,4435,0.24668,5129.320094,4.03,0.4834928 +shiftleft,64,4522,0.23827,5915.280105,5.1,0.5599345 +shiftleft,64,4609,0.229176,6732.600115,6.6,0.6073164 +shiftleft,64,4696,0.2291,6340.600105,5.97,0.6313996 +shiftleft,64,5000,0.239464,5848.640098,4.78,0.610154272 +shiftleft,64,5217,0.234181,6430.760098,6.17,0.7226825659999999 +shiftleft,64,6087,0.227478,6715.940117,5.94,0.82915731 +shiftleft,64,7500,0.229635,7015.820112,6.8,1.08755136 +shiftleft,8,10000,0.100846,390.040004,479.939,0.031867336 +shiftleft,8,10222,0.097799,394.940007,435.049,0.040195389 +shiftleft,8,10444,0.095384,335.160004,328.601,0.032716712 +shiftleft,8,10667,0.093734,359.660006,404.389,0.042461502 +shiftleft,8,10889,0.098154,548.800008,801.248,0.05319946800000001 +shiftleft,8,11111,0.091007,491.960005,678.321,0.042591276000000004 +shiftleft,8,11333,0.092595,545.860006,815.115,0.06018675 +shiftleft,8,11556,0.093322,577.220004,841.762,0.056739776 +shiftleft,8,11778,0.091769,674.240011,1.04,0.064513607 +shiftleft,8,12000,0.088725,724.220008,1.1,0.06760845 +shiftleft,8,13333,0.085966,939.82001,1.56,0.106683806 +shiftleft,8,15000,0.087055,827.120012,1.35,0.09924269999999999 +shiftleft,8,15556,0.084214,738.920012,1.13,0.08665620599999999 +shiftleft,8,20000,0.100914,757.540012,1.26,0.136435728 +shiftleft,8,5000,0.198975,154.840003,31.052,0.007421767500000001 +shiftleft,8,6667,0.149837,177.380003,48.381,0.0092299592 +shiftleft,8,7500,0.132768,218.540002,147.871,0.020844576 +shiftleft,8,8889,0.112426,236.180002,193.721,0.024059163999999997 diff --git a/synthDC/ppaFitting.csv b/synthDC/ppaFitting.csv new file mode 100644 index 000000000..6b88ead61 --- /dev/null +++ b/synthDC/ppaFitting.csv @@ -0,0 +1,13 @@ +Module,Metric,Freq,1,N,N^2,log2(N),Nlog2(N),R^2 +add,delay,5000,-0.038978555556527635,-0.08911531250030817,-0.00012953428819478948,0.2083593333340971,0.013950093750045424,1.0 +add,area,5000,-1913.1778463362505,-268.21377075092175,-0.4100347526051751,1046.9667200022955,47.59125331263557,1.0 +add,area,10,-13.720001333167332,14.700000312552621,1.3021426840869221e-09,-1.3062278840780171e-10,-9.375775472819561e-08,1.0 +mult,delay,5000,-0.2915958888891911,-0.02828693750009581,-3.445876736121953e-05,0.32169033333357117,0.0044735312500140964,1.0 +mult,area,5000,27780.605184113756,10418.196477973508,26.857274703166343,-24448.387256089416,-1468.2850310678027,1.0 +mult,area,10,-6472.791005245042,-2075.5787013197305,8.20962684330778,5345.246556351299,313.5693677823146,1.0 +comparator,delay,5000,0.1903951111111219,0.000987500000002994,3.427951388890516e-06,3.333333324460974e-06,-0.00012593750000039925,1.0 +comparator,area,5000,-508.51109056188875,-579.7924890645068,-1.0888888741341944,969.5466443383111,101.5524983752957,1.0 +comparator,area,10,-155.6022268893253,-40.3637507501383,-0.07230902908001494,132.9533363336765,8.452500156270371,1.0 +shifter,delay,5000,0.06953233333235516,-0.08957893750031035,-0.00015877864583368578,0.16727300000076853,0.014763625000045773,1.0 +shifter,area,5000,-237.48663487568587,1208.7075255666841,1.5708073263938906,-1678.7400476770383,-166.69187856311666,1.0 +shifter,area,10,-1079.4155736731122,-591.3687615645423,-0.877491337241916,1211.9333560050677,103.11437703155087,1.0 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py new file mode 100755 index 000000000..f939a8e3a --- /dev/null +++ b/synthDC/ppaSynth.py @@ -0,0 +1,75 @@ +#!/usr/bin/python3 +# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22 + +import subprocess +import re +from multiprocessing import Pool + + +def runCommand(module, width, tech, freq): + command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq) + subprocess.Popen(command, shell=True) + +def deleteRedundant(LoT): + '''removes any previous runs for the current synthesis specifications''' + synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}nm_{}_*" + for synth in LoT: + bashCommand = synthStr.format(*synth) + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + +def getData(): + bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] + + cpl = re.compile('\d{1}\.\d{6}') + f = re.compile('_\d*_MHz') + wm = re.compile('ppa_\w*_\d*_qor') + + allSynths = [] + + for i in range(len(linesCPL)): + line = linesCPL[i] + mwm = wm.findall(line)[0][4:-4].split('_') + freq = int(f.findall(line)[0][1:-4]) + delay = float(cpl.findall(line)[0]) + mod = mwm[0] + width = int(mwm[1]) + + oneSynth = [mod, width, freq, delay] + allSynths += [oneSynth] + + return allSynths + +allSynths = getData() +arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 10, 14, 20, 40] + +widths = [8] +modules = ['decoder'] +tech = 'sky90' +LoT = [] + +## initial sweep to get estimate of min delay +# freqs = ['17200'] +# for module in modules: +# for width in widths: +# for freq in freqs: +# LoT += [[module, width, tech, freq]] + +# thorough sweep based on estimate of min delay +for m in modules: + for w in widths: + delays = [] + for oneSynth in allSynths: + if (oneSynth[0] == m) & (oneSynth[1] == w): + delays += [oneSynth[3]] + try: f = 1000/min(delays) + except: print(m) + for freq in [str(round(f+f*x/100)) for x in arr]: + LoT += [[m, w, tech, freq]] + +deleteRedundant(LoT) + +pool = Pool() +pool.starmap(runCommand, LoT) +pool.close() \ No newline at end of file diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 9d6aac68a..368e45f3a 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -137,6 +137,10 @@ if {$tech == "sky130"} { # Set the wire load model set_wire_load_mode "top" +# Set switching activities +# default activity factors are 1 for clocks, 0.1 for others +# static probability of 0.5 is used for leakage + # Attempt Area Recovery - if looking for minimal area # set_max_area 2000 @@ -359,4 +363,4 @@ redirect $filename { report_constraint } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] # redirect $filename { report_hierarchy } -quit +#quit