More updates to fpga IP module names.

fpga/constraints/marked_debug_rvvi.txt

@@ -0,0 +1,10 @@
+wally/wallypipelinedcore.sv: logic             PCM
+wally/wallypipelinedcore.sv: logic    TrapM
+wally/wallypipelinedcore.sv: logic                InstrValidM
+wally/wallypipelinedcore.sv: logic                 InstrM
+lsu/lsu.sv: logic        IEUAdrM
+lsu/lsu.sv: logic        PAdrM
+lsu/lsu.sv: logic        ReadDataM
+lsu/lsu.sv: logic        WriteDataM
+lsu/lsu.sv: logic       MemRWM
+privileged/csrc.sv: logic      HPMCOUNTER_REGW

fpga/generator/Makefile

@@ -44,9 +44,9 @@ IP_Arty: $(dst)/sysrst.log \
 # Generate Memory IP Blocks
 .PHONY: MEM_VCU MEM_Arty
 MEM_VCU:
-	$(MAKE) $(dst)/xlnx_ddr4-$(board).log
+	$(MAKE) $(dst)/ddr4-$(board).log
 MEM_Arty:
-	$(MAKE) $(dst)/xlnx_ddr3-$(board).log
+	$(MAKE) $(dst)/ddr3-$(board).log
 
 # Copy files and make necessary modifications
 .PHONY: PreProcessFiles

fpga/generator/ahbaxibridge.tcl

@@ -0,0 +1,20 @@
+
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+
+set ipName ahbaxibridge
+
+create_project $ipName . -force -part $partNumber
+if {$boardName!="ArtyA7"} {
+    set_property board_part $boardName [current_project]
+}
+
+# really just these two lines which change
+create_ip -name ahblite_axi_bridge -vendor xilinx.com -library ip -module_name $ipName
+set_property -dict [list CONFIG.C_M_AXI_DATA_WIDTH {64} CONFIG.C_S_AHB_DATA_WIDTH {64} CONFIG.C_M_AXI_THREAD_ID_WIDTH {4}] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1

fpga/generator/clkconverter.tcl

@@ -0,0 +1,28 @@
+
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+#set partNumber xcvu9p-flga2104-2L-e
+#set boardName  xilinx.com:vcu118:part0:2.4
+
+set ipName clkconverter
+
+create_project $ipName . -force -part $partNumber
+if {$boardName!="ArtyA7"} {
+    set_property board_part $boardName [current_project]
+}
+
+create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
+
+set_property -dict [list CONFIG.ACLK_ASYNC {1} \
+			CONFIG.PROTOCOL {AXI4} \
+			CONFIG.ADDR_WIDTH {32} \
+			CONFIG.DATA_WIDTH {64} \
+			CONFIG.ID_WIDTH {4} \
+		        CONFIG.MI_CLK.FREQ_HZ {208333333} \
+			CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1

fpga/generator/ddr3-ArtyA7.tcl

@@ -2,7 +2,7 @@
 set partNumber $::env(XILINX_PART)
 set boardName $::env(XILINX_BOARD)
 
-set ipName xlnx_ddr3
+set ipName ddr3
 
 create_project $ipName . -force -part $partNumber
 set_property board_part $boardName [current_project]

fpga/generator/ddr4-vcu108.tcl

@@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
 #set partNumber xcvu9p-flga2104-2L-e
 #set boardName  xilinx.com:vcu118:part0:2.4
 
-set ipName xlnx_ddr4
+set ipName ddr4
 
 create_project $ipName . -force -part $partNumber
 set_property board_part $boardName [current_project]

fpga/generator/ddr4-vcu118.tcl

@@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
 #set partNumber xcvu9p-flga2104-2L-e
 #set boardName  xilinx.com:vcu118:part0:2.4
 
-set ipName xlnx_ddr4
+set ipName ddr4
 
 create_project $ipName . -force -part $partNumber
 set_property board_part $boardName [current_project]

fpga/generator/mmcm.tcl

@@ -0,0 +1,27 @@
+set partNumber $::env(XILINX_PART)
+set boardName  $::env(XILINX_BOARD)
+
+set ipName mmcm
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $boardName [current_project]
+
+create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
+
+set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
+                        CONFIG.NUM_OUT_CLKS {3} \
+                        CONFIG.CLKOUT2_USED {true} \
+                        CONFIG.CLKOUT3_USED {true} \
+                        CONFIG.CLKOUT4_USED {true} \
+                        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
+                        CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
+                        CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
+                        CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
+                        CONFIG.CLKIN1_JITTER_PS {10.0} \
+                       ] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1

fpga/generator/sysrst.tcl

@@ -0,0 +1,26 @@
+
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+#set partNumber xcvu9p-flga2104-2L-e
+#set boardName  xilinx.com:vcu118:part0:2.4
+
+set ipName sysrst
+
+create_project $ipName . -force -part $partNumber
+if {$boardName!="ArtyA7"} {
+    set_property board_part $boardName [current_project]
+}
+
+# really just these two lines which change
+create_ip -name proc_sys_reset -vendor xilinx.com -library ip -module_name $ipName
+set_property -dict [list CONFIG.C_AUX_RESET_HIGH {1} \
+			CONFIG.C_AUX_RST_WIDTH {1} \
+			CONFIG.C_EXT_RESET_HIGH {1} \
+			CONFIG.C_EXT_RST_WIDTH {1} \
+			CONFIG.C_NUM_BUS_RST {1}] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1

fpga/generator/wally.tcl

@@ -23,20 +23,15 @@ if {$board=="ArtyA7"} {
 }
 
 # read in ip
-read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
+read_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci
-read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
+read_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci
-read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
+read_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci
-# Added crossbar - Jacob Pease <2023-01-12 Thu>
-#read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci
-#read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci
-#read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci
-#read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci
 
 if {$board=="ArtyA7"} {
-    read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci
+    read_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
-    read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci
+    read_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
 } else {
-    read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
+    read_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci
 }
 
 # read in all other rtl

fpga/generator/xlnx_ddr4.tcl

@@ -5,7 +5,7 @@ set partNumber xcvu095-ffva2104-2-e
 set boardName  xilinx.com:vcu108:part0:1.2
 
 
-set ipName xlnx_ddr4
+set ipName ddr4
 
 create_project $ipName . -force -part $partNumber
 set_property board_part $boardName [current_project]

fpga/src/fpgaTopArtyA7.sv

@@ -400,7 +400,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
      .m_axi_rready(BUS_axi_rready));
 
   // DDR3 Controller
-  xlnx_ddr3 xlnx_ddr3_c0
+  ddr3 ddr3
     (
      // ddr3 I/O
      .ddr3_dq(ddr3_dq),