From fc80bf1251c76ed719bcc1e7a8d7ddb9dcee3a31 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 22 Aug 2024 14:31:39 -0700 Subject: [PATCH] More updates to fpga IP module names. --- fpga/constraints/marked_debug_rvvi.txt | 10 +++++++ fpga/generator/Makefile | 4 +-- fpga/generator/ahbaxibridge.tcl | 20 +++++++++++++ fpga/generator/clkconverter.tcl | 28 +++++++++++++++++++ .../{xlnx_ddr3-ArtyA7.tcl => ddr3-ArtyA7.tcl} | 2 +- .../{xlnx_ddr4-vcu108.tcl => ddr4-vcu108.tcl} | 2 +- .../{xlnx_ddr4-vcu118.tcl => ddr4-vcu118.tcl} | 2 +- fpga/generator/mmcm.tcl | 27 ++++++++++++++++++ fpga/generator/sysrst.tcl | 26 +++++++++++++++++ fpga/generator/wally.tcl | 17 ++++------- fpga/generator/xlnx_ddr4.tcl | 2 +- fpga/src/fpgaTopArtyA7.sv | 2 +- 12 files changed, 124 insertions(+), 18 deletions(-) create mode 100644 fpga/constraints/marked_debug_rvvi.txt create mode 100644 fpga/generator/ahbaxibridge.tcl create mode 100644 fpga/generator/clkconverter.tcl rename fpga/generator/{xlnx_ddr3-ArtyA7.tcl => ddr3-ArtyA7.tcl} (97%) rename fpga/generator/{xlnx_ddr4-vcu108.tcl => ddr4-vcu108.tcl} (99%) rename fpga/generator/{xlnx_ddr4-vcu118.tcl => ddr4-vcu118.tcl} (99%) create mode 100644 fpga/generator/mmcm.tcl create mode 100644 fpga/generator/sysrst.tcl diff --git a/fpga/constraints/marked_debug_rvvi.txt b/fpga/constraints/marked_debug_rvvi.txt new file mode 100644 index 000000000..afed3dd23 --- /dev/null +++ b/fpga/constraints/marked_debug_rvvi.txt @@ -0,0 +1,10 @@ +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic PAdrM +lsu/lsu.sv: logic ReadDataM +lsu/lsu.sv: logic WriteDataM +lsu/lsu.sv: logic MemRWM +privileged/csrc.sv: logic HPMCOUNTER_REGW diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 9c97843d6..1922db0f8 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -44,9 +44,9 @@ IP_Arty: $(dst)/sysrst.log \ # Generate Memory IP Blocks .PHONY: MEM_VCU MEM_Arty MEM_VCU: - $(MAKE) $(dst)/xlnx_ddr4-$(board).log + $(MAKE) $(dst)/ddr4-$(board).log MEM_Arty: - $(MAKE) $(dst)/xlnx_ddr3-$(board).log + $(MAKE) $(dst)/ddr3-$(board).log # Copy files and make necessary modifications .PHONY: PreProcessFiles diff --git a/fpga/generator/ahbaxibridge.tcl b/fpga/generator/ahbaxibridge.tcl new file mode 100644 index 000000000..e41eed6ce --- /dev/null +++ b/fpga/generator/ahbaxibridge.tcl @@ -0,0 +1,20 @@ + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName ahbaxibridge + +create_project $ipName . -force -part $partNumber +if {$boardName!="ArtyA7"} { + set_property board_part $boardName [current_project] +} + +# really just these two lines which change +create_ip -name ahblite_axi_bridge -vendor xilinx.com -library ip -module_name $ipName +set_property -dict [list CONFIG.C_M_AXI_DATA_WIDTH {64} CONFIG.C_S_AHB_DATA_WIDTH {64} CONFIG.C_M_AXI_THREAD_ID_WIDTH {4}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/clkconverter.tcl b/fpga/generator/clkconverter.tcl new file mode 100644 index 000000000..6a9746504 --- /dev/null +++ b/fpga/generator/clkconverter.tcl @@ -0,0 +1,28 @@ + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +set ipName clkconverter + +create_project $ipName . -force -part $partNumber +if {$boardName!="ArtyA7"} { + set_property board_part $boardName [current_project] +} + +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [list CONFIG.ACLK_ASYNC {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.ID_WIDTH {4} \ + CONFIG.MI_CLK.FREQ_HZ {208333333} \ + CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_ddr3-ArtyA7.tcl b/fpga/generator/ddr3-ArtyA7.tcl similarity index 97% rename from fpga/generator/xlnx_ddr3-ArtyA7.tcl rename to fpga/generator/ddr3-ArtyA7.tcl index 2213e7da9..20aed4e9f 100644 --- a/fpga/generator/xlnx_ddr3-ArtyA7.tcl +++ b/fpga/generator/ddr3-ArtyA7.tcl @@ -2,7 +2,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) -set ipName xlnx_ddr3 +set ipName ddr3 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/generator/xlnx_ddr4-vcu108.tcl b/fpga/generator/ddr4-vcu108.tcl similarity index 99% rename from fpga/generator/xlnx_ddr4-vcu108.tcl rename to fpga/generator/ddr4-vcu108.tcl index 71f8f06a4..e9610cfff 100644 --- a/fpga/generator/xlnx_ddr4-vcu108.tcl +++ b/fpga/generator/ddr4-vcu108.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/generator/xlnx_ddr4-vcu118.tcl b/fpga/generator/ddr4-vcu118.tcl similarity index 99% rename from fpga/generator/xlnx_ddr4-vcu118.tcl rename to fpga/generator/ddr4-vcu118.tcl index 8041726ff..5a98c07de 100644 --- a/fpga/generator/xlnx_ddr4-vcu118.tcl +++ b/fpga/generator/ddr4-vcu118.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/generator/mmcm.tcl b/fpga/generator/mmcm.tcl new file mode 100644 index 000000000..de4a1a1d0 --- /dev/null +++ b/fpga/generator/mmcm.tcl @@ -0,0 +1,27 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName mmcm + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ + CONFIG.NUM_OUT_CLKS {3} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ + CONFIG.CLKIN1_JITTER_PS {10.0} \ + ] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/sysrst.tcl b/fpga/generator/sysrst.tcl new file mode 100644 index 000000000..8225c02d5 --- /dev/null +++ b/fpga/generator/sysrst.tcl @@ -0,0 +1,26 @@ + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +set ipName sysrst + +create_project $ipName . -force -part $partNumber +if {$boardName!="ArtyA7"} { + set_property board_part $boardName [current_project] +} + +# really just these two lines which change +create_ip -name proc_sys_reset -vendor xilinx.com -library ip -module_name $ipName +set_property -dict [list CONFIG.C_AUX_RESET_HIGH {1} \ + CONFIG.C_AUX_RST_WIDTH {1} \ + CONFIG.C_EXT_RESET_HIGH {1} \ + CONFIG.C_EXT_RST_WIDTH {1} \ + CONFIG.C_NUM_BUS_RST {1}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index c0ac9f4a4..cfaa2bf1b 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -23,20 +23,15 @@ if {$board=="ArtyA7"} { } # read in ip -read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci -read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci -read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci -# Added crossbar - Jacob Pease <2023-01-12 Thu> -#read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci -#read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci -#read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci -#read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci +read_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci +read_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci +read_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci if {$board=="ArtyA7"} { - read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci - read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci + read_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci + read_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci } else { - read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci + read_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci } # read in all other rtl diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl index c3aac1f71..2b9d24e70 100644 --- a/fpga/generator/xlnx_ddr4.tcl +++ b/fpga/generator/xlnx_ddr4.tcl @@ -5,7 +5,7 @@ set partNumber xcvu095-ffva2104-2-e set boardName xilinx.com:vcu108:part0:1.2 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 0da6adddf..f5fc64996 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -400,7 +400,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .m_axi_rready(BUS_axi_rready)); // DDR3 Controller - xlnx_ddr3 xlnx_ddr3_c0 + ddr3 ddr3 ( // ddr3 I/O .ddr3_dq(ddr3_dq),