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Revert "Beginning subword cleanup."

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This reverts commit 7e1ea1e6d9.
This commit is contained in:
Rose Thompson 2024-03-06 15:16:24 -06:00
parent a8024eee26
commit f752b5dd37
2 changed files with 16 additions and 7 deletions
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2
src/lsu/lsu.sv
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@ -423,7 +423,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if(MISALIGN_SUPPORT) begin if(MISALIGN_SUPPORT) begin
subwordreadmisaligned #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM); subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM);
end else begin end else begin

21
src/lsu/subworddreadmisaligned.sv
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@ -40,11 +40,10 @@ module subwordreadmisaligned #(parameter LLEN)
logic [7:0] ByteM; logic [7:0] ByteM;
logic [15:0] HalfwordM; logic [15:0] HalfwordM;
logic [31:0] WordM;
logic [4:0] PAdrSwap; logic [4:0] PAdrSwap;
logic [4:0] BigEndianPAdr; logic [4:0] BigEndianPAdr;
logic [4:0] LengthM; logic [4:0] LengthM;
// Funct3M[2] is the unsigned bit. mask upper bits. // Funct3M[2] is the unsigned bit. mask upper bits.
// Funct3M[1:0] is the size of the memory access. // Funct3M[1:0] is the size of the memory access.
assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM}; assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
@ -67,14 +66,14 @@ module subwordreadmisaligned #(parameter LLEN)
logic [LLEN*2-1:0] ReadDataAlignedM; logic [LLEN*2-1:0] ReadDataAlignedM;
assign ReadDataAlignedM = ReadDataWordMuxM >> (PAdrSwap[$clog2(LLEN/4)-1:0] * 8); assign ReadDataAlignedM = ReadDataWordMuxM >> (PAdrSwap[$clog2(LLEN/4)-1:0] * 8);
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
if (LLEN == 128) begin:swrmux if (LLEN == 128) begin:swrmux
logic [31:0] WordM;
logic [63:0] DblWordM; logic [63:0] DblWordM;
logic [127:0] QdWordM; logic [127:0] QdWordM;
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
assign DblWordM = ReadDataAlignedM[63:0]; assign DblWordM = ReadDataAlignedM[63:0];
assign QdWordM =ReadDataAlignedM[127:0]; assign QdWordM =ReadDataAlignedM[127:0];
@ -93,8 +92,12 @@ module subwordreadmisaligned #(parameter LLEN)
endcase endcase
end else if (LLEN == 64) begin:swrmux end else if (LLEN == 64) begin:swrmux
logic [31:0] WordM;
logic [63:0] DblWordM; logic [63:0] DblWordM;
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
assign DblWordM = ReadDataAlignedM[63:0]; assign DblWordM = ReadDataAlignedM[63:0];
// sign extension/ NaN boxing // sign extension/ NaN boxing
@ -113,6 +116,12 @@ module subwordreadmisaligned #(parameter LLEN)
end else begin:swrmux // 32-bit end else begin:swrmux // 32-bit
logic [31:0] WordM;
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
// sign extension // sign extension
always_comb always_comb
case(Funct3M) case(Funct3M)