From f752b5dd37d94fb359584f31efbac6d810c548bd Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 6 Mar 2024 15:16:24 -0600 Subject: [PATCH] Revert "Beginning subword cleanup." This reverts commit 7e1ea1e6d9472fdfd188823fc81ee455abbab460. --- src/lsu/lsu.sv | 2 +- src/lsu/subworddreadmisaligned.sv | 21 +++++++++++++++------ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 8e827292f..0150be599 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -423,7 +423,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( ///////////////////////////////////////////////////////////////////////////////////////////// if(MISALIGN_SUPPORT) begin - subwordreadmisaligned #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, + subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM); end else begin diff --git a/src/lsu/subworddreadmisaligned.sv b/src/lsu/subworddreadmisaligned.sv index fe96844f3..cc1c13787 100644 --- a/src/lsu/subworddreadmisaligned.sv +++ b/src/lsu/subworddreadmisaligned.sv @@ -40,11 +40,10 @@ module subwordreadmisaligned #(parameter LLEN) logic [7:0] ByteM; logic [15:0] HalfwordM; - logic [31:0] WordM; logic [4:0] PAdrSwap; logic [4:0] BigEndianPAdr; logic [4:0] LengthM; - + // Funct3M[2] is the unsigned bit. mask upper bits. // Funct3M[1:0] is the size of the memory access. assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM}; @@ -67,14 +66,14 @@ module subwordreadmisaligned #(parameter LLEN) logic [LLEN*2-1:0] ReadDataAlignedM; assign ReadDataAlignedM = ReadDataWordMuxM >> (PAdrSwap[$clog2(LLEN/4)-1:0] * 8); - assign ByteM = ReadDataAlignedM[7:0]; - assign HalfwordM = ReadDataAlignedM[15:0]; - assign WordM = ReadDataAlignedM[31:0]; - if (LLEN == 128) begin:swrmux + logic [31:0] WordM; logic [63:0] DblWordM; logic [127:0] QdWordM; + assign ByteM = ReadDataAlignedM[7:0]; + assign HalfwordM = ReadDataAlignedM[15:0]; + assign WordM = ReadDataAlignedM[31:0]; assign DblWordM = ReadDataAlignedM[63:0]; assign QdWordM =ReadDataAlignedM[127:0]; @@ -93,8 +92,12 @@ module subwordreadmisaligned #(parameter LLEN) endcase end else if (LLEN == 64) begin:swrmux + logic [31:0] WordM; logic [63:0] DblWordM; + assign ByteM = ReadDataAlignedM[7:0]; + assign HalfwordM = ReadDataAlignedM[15:0]; + assign WordM = ReadDataAlignedM[31:0]; assign DblWordM = ReadDataAlignedM[63:0]; // sign extension/ NaN boxing @@ -113,6 +116,12 @@ module subwordreadmisaligned #(parameter LLEN) end else begin:swrmux // 32-bit + logic [31:0] WordM; + + assign ByteM = ReadDataAlignedM[7:0]; + assign HalfwordM = ReadDataAlignedM[15:0]; + assign WordM = ReadDataAlignedM[31:0]; + // sign extension always_comb case(Funct3M)