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Added option to use rvvi ila

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Rose Thompson 2024-07-22 12:19:37 -05:00
parent 02f108345a
commit efa99940c5
1 changed files with 1 additions and 0 deletions
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fpga/generator/wally.tcl
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@ -90,6 +90,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} {
source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc
} else {
# source ../constraints/vcu-small-debug.xdc