diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index eff0a6cb9..9df775646 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -90,6 +90,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
 
 if {$board=="ArtyA7"} {
     source ../constraints/small-debug.xdc
+    #source ../constraints/small-debug-rvvi.xdc
 
 } else {
     # source ../constraints/vcu-small-debug.xdc