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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Rose Thompson 2024-02-01 12:12:05 -06:00
commit e900bb09db
21 changed files with 883 additions and 529 deletions
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85
bin/nightly_build/nightly_build_v13_beta.sh Executable file
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#!/bin/bash
# set WALLY path
WALLY=$(dirname ${BASH_SOURCE[0]:-$0})
export WALLY=$(cd "$WALLY/../../" && pwd)
echo "WALLY is set to: $WALLY"
# Going to nightly runs
cd $WALLY/../
# check if directories exist
if [ ! -d "build-results" ]; then
echo "Directory does not exist, creating it..."
mkdir -p "build-results"
if [ $? -eq 0 ]; then
echo "Directory created successfully."
else
echo "Failed to create directory."
exit 1
fi
else
echo "Directory already exists."
fi
if [ ! -d "logs" ]; then
echo "Directory does not exist, creating it..."
mkdir -p "logs"
if [ $? -eq 0 ]; then
echo "Directory created successfully."
else
echo "Failed to create directory."
exit 1
fi
else
echo "Directory already exists."
fi
# setup source okstate file
echo "Sourcing setup files"
source $WALLY/setup_host.sh
source $WALLY/../setup-files/setup_tools.sh
# Navigate to the gir repo
cd $WALLY
# pull the repository
echo "Pulling submodules"
#git pull --recurse-submodules origin main
# build the regression tests
echo "Building the regression tests"
cd sim
#if make wally-riscv-arch-test; then
#if make all; then
# echo "Make successfull"
#else
# echo "Make failed"
# cd $WALLY/..
# add the the regression result and the coverage result that there was an error in making the tests
# python $WALLY/bin/nightly_build/src/error_detector.py --tag make -o $WALLY/../build-results/regression_results.md
# python $WALLY/bin/nightly_build/src/error_detector.py --tag make -o $WALLY/../build-results/coverage_results.md
# exit the program
#exit 1
#fi
# execute the simulation / regression tests and save output to a file
echo "running the regression test"
#./regression-wally > $WALLY/../logs/regression_output.log 2>&1
echo "running coverage tests"
#./coverage > $WALLY/../logs/coverage_output.log 2>&1
# run the Python script to parse the output and generate the log file
echo "Parsing output data from the regression test"
cd $WALLY/../
python $WALLY/bin/nightly_build/src/parse_regression.py -i $WALLY/../logs/regression_output.log -o $WALLY/../build-results/regression_results.md
python $WALLY/bin/nightly_build/src/parse_coverage.py -i $WALLY/../logs/coverage_output.log -o $WALLY/../build-results/coverage_results.md
# email update
cd $WALLY/bin/nightly_build/src/
./send_mail_html.sh

37
bin/nightly_build/src/error_detector.py Normal file
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import argparse
import datetime
def add_failure_to_markdown(tag, output_file, input_file = None):
# Get the current date and time
current_datetime = datetime.datetime.now()
formatted_datetime = current_datetime.strftime("%Y-%m-%d %H:%M:%S")
# Create the failure message based on the provided tag and input content
if tag == "make":
failure_message = f"# {tag.capitalize()} riscof comilation failure - {formatted_datetime}\n\n"
failure_message += f"The error was due to a problem in compiling the the riscof tests:\n\n"
if input_file != None:
failure_message += f"The particular error: {input_file}\n\n"
else:
failure_message = f"# {tag.capitalize()} Failure - {formatted_datetime}\n\n"
failure_message += f":\n\n"
# Append the failure message to the specified output file
with open(output_file, "a") as file:
file.write(failure_message)
print(f"Failure information added to {output_file}.")
if __name__ == "__main__":
# Set up argparse
parser = argparse.ArgumentParser(description="Add failure information to Markdown file.")
parser.add_argument("--tag", required=True, help="Specify the tag for the failure type (e.g., 'make', 'custom').")
parser.add_argument("-i", required=False, help="Specify the input file containing failure details.")
parser.add_argument("-o", required=True, help="Specify the output file to write the failure information.")
# Parse command-line arguments
args = parser.parse_args()
# Call the function with the specified tag, input file, and output file
add_failure_to_markdown(args.tag, args.o)

95
bin/nightly_build/src/parse_coverage.py Normal file
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import os
import argparse
from datetime import datetime
import re
from colorama import init, Fore, Style
def parse_regression_output(output):
passed_configs = []
failed_configs = []
lines = output.split('\n')
index = 0
while index < len(lines):
# Remove ANSI escape codes
line = re.sub(r'\x1b\[[0-9;]*[mGK]', '', lines[index])
if "Success" in line:
passed_configs.append(line.split(':')[0].strip())
elif "Failures detected in output" in line:
try:
config_name = line.split(':')[0].strip()
log_file = os.path.abspath(config_name+".log")
failed_configs.append((config_name, log_file))
except:
failed_configs.append((config_name, "Log file not found"))
index += 1
# alphabetically sort the configurations
passed_configs.sort()
failed_configs.sort()
return passed_configs, failed_configs
def write_to_markdown(passed_configs, failed_configs, output_file):
timestamp = datetime.now().strftime("%Y-%m-%d %H:%M:%S")
with open(output_file, 'a') as md_file:
md_file.write(f"\n\n# Coverage Test Results - {timestamp}\n\n")
md_file.write("\n## Failed Configurations\n")
for config, log_file in failed_configs:
md_file.write(f"- <span class=\"failure\" style=\"color: red;\">{config}</span> ({log_file})\n")
if len(failed_configs) == 0:
md_file.write(" - no failures\n")
md_file.write("\n## Passed Configurations\n")
for config in passed_configs:
md_file.write(f"- <span class=\"success\" style=\"color: green;\">{config}</span>\n")
def write_new_markdown(passed_configs, failed_configs):
timestamp = datetime.now().strftime("%Y-%m-%d")
output_file = f"/home/thkidd/nightly_runs/build-results/builds/coverage/wally_coverage_{timestamp}.md"
with open(output_file, 'w') as md_file:
# Title
md_file.write(f"\n\n# Coverage Test Results - {timestamp}\n\n")
## File path
md_file.write(f"\n**File:** {output_file}\n")
md_file.write("\n## Failed Configurations\n")
# add in if there were no failures
if len(failed_configs) == 0:
md_file.write(f"No Failures\n")
for config, log_file in failed_configs:
md_file.write(f"- <span class=\"failure regression\" style=\"color: red;\">{config}</span> ({log_file})\n")
md_file.write("\n## Passed Configurations\n")
for config in passed_configs:
md_file.write(f"- <span class=\"success regression\" style=\"color: green;\">{config}</span>\n")
if __name__ == "__main__":
init(autoreset=True) # Initialize colorama
parser = argparse.ArgumentParser(description='Parse regression test output and append to a markdown file.')
parser.add_argument('-i', '--input', help='Input file containing regression test output', required=True)
parser.add_argument('-o', '--output', help='Output markdown file', default='regression_results.md')
args = parser.parse_args()
with open(args.input, 'r') as input_file:
regression_output = input_file.read()
passed_configs, failed_configs = parse_regression_output(regression_output)
write_to_markdown(passed_configs, failed_configs, args.output)
print(f"Markdown file updated: {args.output}")
write_new_markdown(passed_configs, failed_configs)
print("New markdown file created")

102
bin/nightly_build/src/parse_regression.py Normal file
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import argparse
import os
from datetime import datetime
import re
from colorama import init, Fore, Style
def parse_regression_output(output):
passed_configs = []
failed_configs = []
lines = output.split('\n')
index = 0
while index < len(lines):
# Remove ANSI escape codes
line = re.sub(r'\x1b\[[0-9;]*[mGK]', '', lines[index])
#print("The cleaned line: ", line)
if "Success" in line:
passed_configs.append(line.split(':')[0].strip())
elif "Failures detected in output" in line:
try:
config_name = line.split(':')[0].strip()
log_file = os.path.abspath(config_name+".log")
failed_configs.append((config_name, log_file))
except:
failed_configs.append((config_name, "Log file not found"))
elif "Timeout" in line:
try:
config_name = line.split(':')[0].strip()
log_file = os.path.abspath(config_name+".log")
failed_configs.append((config_name, log_file))
except:
failed_configs.append((config_name, "Log file not found"))
index += 1
# alphabetically sort the configurations
passed_configs.sort()
failed_configs.sort()
return passed_configs, failed_configs
def write_to_markdown(passed_configs, failed_configs, output_file):
timestamp = datetime.now().strftime("%Y-%m-%d %H:%M:%S")
with open(output_file, 'a') as md_file:
md_file.write(f"\n\n<div class=\"regression\">\n# Regression Test Results - {timestamp}\n</div>\n\n")
#md_file.write(f"\n\n# Regression Test Results - {timestamp}\n\n")
if failed_configs:
md_file.write("## Failed Configurations\n")
for config, log_file in failed_configs:
md_file.write(f"- <span class=\"failure regression\" style=\"color: red;\">{config}</span> ({log_file})\n")
md_file.write("\n")
else:
md_file.write("## No Failed Configurations\n")
md_file.write("\n## Passed Configurations\n")
for config in passed_configs:
md_file.write(f"- <span class=\"success regression\" style=\"color: green;\">{config}</span>\n")
def write_new_markdown(passed_configs, failed_configs):
timestamp = datetime.now().strftime("%Y-%m-%d")
output_file = f"/home/thkidd/nightly_runs/build-results/builds/regression/wally_regression_{timestamp}.md"
with open(output_file, 'w') as md_file:
# Title
md_file.write(f"\n\n# Regression Test Results - {timestamp}\n\n")
#md_file.write(f"\n\n<div class=\"regression\">\n# Regression Test Results - {timestamp}\n</div>\n\n")
# File Path
md_file.write(f"\n**File:** {output_file}\n\n")
if failed_configs:
md_file.write("## Failed Configurations\n\n")
for config, log_file in failed_configs:
md_file.write(f"- <span class=\"failure regression\" style=\"color: red;\">{config}</span> ({log_file})\n")
md_file.write("\n")
else:
md_file.write("## Failed Configurations\n")
md_file.write(f"No Failures\n")
md_file.write("\n## Passed Configurations\n")
for config in passed_configs:
md_file.write(f"- <span class=\"success regression\" style=\"color: green;\">{config}</span>\n")
if __name__ == "__main__":
init(autoreset=True) # Initialize colorama
parser = argparse.ArgumentParser(description='Parse regression test output and append to a markdown file.')
parser.add_argument('-i', '--input', help='Input file containing regression test output', required=True)
parser.add_argument('-o', '--output', help='Output markdown file containing formatted file', default='regression_results.md')
args = parser.parse_args()
with open(args.input, 'r') as input_file:
regression_output = input_file.read()
passed_configs, failed_configs = parse_regression_output(regression_output)
write_to_markdown(passed_configs, failed_configs, args.output)
print(f"Markdown file updated: {args.output}")
write_new_markdown(passed_configs, failed_configs)
print("New markdown file created")

79
bin/nightly_build/src/send_mail_html.sh Executable file
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current_date=$(date "+%Y-%m-%d")
email_address="thomas.kidd@okstate.edu"
#email_address="WALLY-REGRESSION@LISTSERV.OKSTATE.EDU"
subject="WALLY regression and coverage test report"
attachments=""
html_body=""
host_name=$(hostname)
os_info=$(lsb_release -a 2>/dev/null)
script_location=$WALLY/bin/nightly_build/
html_body="<div id='system-info'>
<h3>System Information</h3>
<p><strong>Server Name:</strong> $host_name@okstate.edu</p>
<p><strong>Operating System:</strong> $os_info</p>
<p><strong>Script Origin:</strong> $script_location</p>
</div>
<p>Testing sending HTML content through mutt</p>"
# Iterate through the files and concatenate their content to the body
for file in $WALLY/../build-results/builds/*/wally_*_"$current_date"*.md; do
attachments+=" -a $file"
# Convert Markdown to HTML using pandoc
html_content=$(pandoc "$file")
# add the file full path
# html_body+="<p>File: $file</p>"
# Append the HTML content to the body
html_body+="$html_content"
done
echo "Sending email"
# Get server hostname and OS information
host_name=$(hostname)
os_info=$(uname -a)
# Define HTML body content
# Use mutt to send the email with HTML body
#mutt -e "my_hdr From:James Stine <james.stine@okstate.edu>" -s "$subject" $attachments \
mutt -e "my_hdr From:Thomas Kidd <thomas.kidd@okstate.edu>" -s "$subject" \
-e "set content_type=text/html" -- $email_address <<EOF
<html>
<head>
<meta charset="UTF-8">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<title>Nightly Build Results - $current_date</title>
<style>
body {
font-family: 'Helvetica Neue', Arial, sans-serif;
margin: 20px;
padding: 20px;
background-color: #f4f4f4;
}
h1, h3, p {
color: #333;
}
#system-info {
border: 1px solid #ddd;
padding: 15px;
margin-bottom: 20px;
background-color: #fff;
border-radius: 5px;
box-shadow: 0 0 10px rgba(0, 0, 0, 0.1);
}
<!-- .success { color: green; } -->
<!-- .failure { color: red; } -->
</style>
</head>
<body>
<h1 id="test-results---$current_date">Test Results - $current_date</h1>
$html_body
</body>
</html>
EOF

184
config/buildroot/config.vh
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@ -1,184 +0,0 @@
//////////////////////////////////////////
// config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// include shared configuration
`include "BranchPredictorType.vh"
// RV32 or RV64: XLEN = 32 or 64
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam MISA = (32'h0014112D);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZFH_SUPPORTED = 1;
localparam ZFA_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1;
localparam ZICBOM_SUPPORTED = 1;
localparam ZICBOZ_SUPPORTED = 1;
localparam ZICBOP_SUPPORTED = 1;
localparam ZICCLSM_SUPPORTED = 1;
localparam ZICOND_SUPPORTED = 1;
localparam SVPBMT_SUPPORTED = 1;
localparam SVNAPOT_SUPPORTED = 1;
localparam SVINVAL_SUPPORTED = 1;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;
localparam DCACHE_SUPPORTED = 1;
localparam ICACHE_SUPPORTED = 1;
localparam VIRTMEM_SUPPORTED = 1;
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
localparam BIGENDIAN_SUPPORTED = 1;
// TLB configuration. Entries should be a power of 2
localparam ITLB_ENTRIES = 32'd32;
localparam DTLB_ENTRIES = 32'd32;
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
localparam DCACHE_NUMWAYS = 32'd4;
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
localparam DCACHE_LINELENINBITS = 32'd512;
localparam ICACHE_NUMWAYS = 32'd4;
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
localparam ICACHE_LINELENINBITS = 32'd512;
localparam CACHE_SRAMLEN = 32'd128;
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
localparam IDIV_BITSPERCYCLE = 32'd4;
localparam IDIV_ON_FPU = 1;
// Legal number of PMP entries are 0, 16, or 64
localparam PMP_ENTRIES = 32'd16;
// Address space
localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000;
// WFI Timeout Wait
localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
localparam DTIM_SUPPORTED = 1'b0;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h00001FFF;
localparam IROM_SUPPORTED = 1'b0;
localparam logic [63:0] IROM_BASE = 64'h80000000;
localparam logic [63:0] IROM_RANGE = 64'h00001FFF;
localparam BOOTROM_SUPPORTED = 1'b1;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000 ;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b1;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h0FFFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b1;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
localparam CLINT_SUPPORTED = 1'b1;
localparam logic [63:0] CLINT_BASE = 64'h02000000;
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
localparam GPIO_SUPPORTED = 1'b1;
localparam logic [63:0] GPIO_BASE = 64'h10060000;
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
localparam UART_SUPPORTED = 1'b1;
localparam logic [63:0] UART_BASE = 64'h10000000;
localparam logic [63:0] UART_RANGE = 64'h00000007;
localparam PLIC_SUPPORTED = 1'b1;
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam logic [63:0] SDC_BASE = 64'h00013000;
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
localparam SPI_SUPPORTED = 1'b1;
localparam logic [63:0] SPI_BASE = 64'h10040000;
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
// Bus Interface width
localparam AHBW = 32'd64;
// AHB
localparam RAM_LATENCY = 32'b0;
localparam BURST_EN = 1;
// Test modes
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 0;
localparam SPI_LOOPBACK_TEST = 0;
// Hardware configuration
localparam UART_PRESCALE = 32'd0;
// Interrupt configuration
localparam PLIC_NUM_SRC = 32'd53;
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
localparam PLIC_UART_ID = 32'd10;
localparam PLIC_GPIO_ID = 32'd3;
localparam PLIC_SPI_ID = 32'd6;
localparam PLIC_SDC_ID = 32'd20;
localparam BPRED_SUPPORTED = 1;
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
localparam INSTR_CLASS_PRED = 1;
localparam SVADU_SUPPORTED = 1;
localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture
localparam RADIX = 32'h4;
localparam DIVCOPIES = 32'h4;
// bit manipulation
localparam ZBA_SUPPORTED = 1;
localparam ZBB_SUPPORTED = 1;
localparam ZBC_SUPPORTED = 1;
localparam ZBS_SUPPORTED = 1;
// New compressed instructions
localparam ZCB_SUPPORTED = 1;
localparam ZCA_SUPPORTED = 0;
localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;
`include "config-shared.vh"

217
config/derivlist.txt
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@ -41,8 +41,8 @@ RESET_VECTOR 64'h1000
UNCORE_RAM_RANGE 64'h0FFFFFFF UNCORE_RAM_RANGE 64'h0FFFFFFF
UNCORE_RAM_PRELOAD 1 UNCORE_RAM_PRELOAD 1
GPIO_LOOPBACK_TEST 0 GPIO_LOOPBACK_TEST 0
SPI_LOOPBACK_TEST 0 SPI_LOOPBACK_TEST 0
UART_PRESCALE 0 UART_PRESCALE 32'd0
PLIC_NUM_SRC 32'd53 PLIC_NUM_SRC 32'd53
# fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM) # fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM)
@ -59,10 +59,10 @@ BPRED_SIZE 32'd12
# The syn configurations are trimmed down for faster synthesis. # The syn configurations are trimmed down for faster synthesis.
deriv syn_rv32e rv32e deriv syn_rv32e rv32e
DTIM_RANGE 32'h1FF DTIM_RANGE 64'h1FF
IROM_RANGE 32'h1FF IROM_RANGE 64'h1FF
BOOTROM_RANGE 32'h1FF BOOTROM_RANGE 64'h1FF
UNCORE_RAM_RANGE 32'h1FF UNCORE_RAM_RANGE 64'h1FF
WAYSIZEINBYTES 32'd512 WAYSIZEINBYTES 32'd512
NUMWAYS 32'd1 NUMWAYS 32'd1
BPRED_SIZE 32'd5 BPRED_SIZE 32'd5
@ -77,8 +77,8 @@ deriv syn_rv64gc rv64gc syn_rv32e
# The syn_sram configurations use SRAM macros # The syn_sram configurations use SRAM macros
deriv syn_sram_rv32e rv32e deriv syn_sram_rv32e rv32e
DTIM_RANGE 32'h1FF DTIM_RANGE 64'h1FF
IROM_RANGE 32'h1FF IROM_RANGE 64'h1FF
USE_SRAM 1 USE_SRAM 1
# The other syn configurations have the same trimming # The other syn configurations have the same trimming
@ -90,9 +90,9 @@ deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
# The following syn configurations gradually turn off features # The following syn configurations gradually turn off features
deriv syn_pmp0_rv64gc rv64gc syn_rv64gc deriv syn_pmp0_rv64gc rv64gc syn_rv64gc
PMP_ENTRIES 0 PMP_ENTRIES 32'd0
deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc
PMP_ENTRIES 0 PMP_ENTRIES 32'd0
deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc
ZICSR_SUPPORTED 0 ZICSR_SUPPORTED 0
@ -119,26 +119,33 @@ MISA (32'h00000104 | 1 << 18 | 1 << 20)
deriv div_2_1_rv32gc rv32gc deriv div_2_1_rv32gc rv32gc
RADIX 32'd2 RADIX 32'd2
DIVCOPIES 32'd1 DIVCOPIES 32'd1
IDIV_ON_FPU 0
deriv div_2_2_rv32gc rv32gc deriv div_2_2_rv32gc rv32gc
RADIX 32'd2 RADIX 32'd2
DIVCOPIES 32'd2 DIVCOPIES 32'd2
IDIV_ON_FPU 0
deriv div_2_4_rv32gc rv32gc deriv div_2_4_rv32gc rv32gc
RADIX 32'd2 RADIX 32'd2
DIVCOPIES 32'd4 DIVCOPIES 32'd4
IDIV_ON_FPU 0
deriv div_4_1_rv32gc rv32gc deriv div_4_1_rv32gc rv32gc
RADIX 32'd4 RADIX 32'd4
DIVCOPIES 32'd1 DIVCOPIES 32'd1
IDIV_ON_FPU 0
deriv div_4_2_rv32gc rv32gc deriv div_4_2_rv32gc rv32gc
RADIX 32'd4 RADIX 32'd4
IDIV_ON_FPU 0
DIVCOPIES 32'd2 DIVCOPIES 32'd2
IDIV_ON_FPU 0
deriv div_4_4_rv32gc rv32gc deriv div_4_4_rv32gc rv32gc
RADIX 32'd4 RADIX 32'd4
DIVCOPIES 32'd4 DIVCOPIES 32'd4
IDIV_ON_FPU 0
deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc
IDIV_ON_FPU 1 IDIV_ON_FPU 1
@ -161,26 +168,32 @@ IDIV_ON_FPU 1
deriv div_2_1_rv64gc rv64gc deriv div_2_1_rv64gc rv64gc
RADIX 32'd2 RADIX 32'd2
DIVCOPIES 32'd1 DIVCOPIES 32'd1
IDIV_ON_FPU 0
deriv div_2_2_rv64gc rv64gc deriv div_2_2_rv64gc rv64gc
RADIX 32'd2 RADIX 32'd2
DIVCOPIES 32'd2 DIVCOPIES 32'd2
IDIV_ON_FPU 0
deriv div_2_4_rv64gc rv64gc deriv div_2_4_rv64gc rv64gc
RADIX 32'd2 RADIX 32'd2
DIVCOPIES 32'd4 DIVCOPIES 32'd4
IDIV_ON_FPU 0
deriv div_4_1_rv64gc rv64gc deriv div_4_1_rv64gc rv64gc
RADIX 32'd4 RADIX 32'd4
DIVCOPIES 32'd1 DIVCOPIES 32'd1
IDIV_ON_FPU 0
deriv div_4_2_rv64gc rv64gc deriv div_4_2_rv64gc rv64gc
RADIX 32'd4 RADIX 32'd4
DIVCOPIES 32'd2 DIVCOPIES 32'd2
IDIV_ON_FPU 0
deriv div_4_4_rv64gc rv64gc deriv div_4_4_rv64gc rv64gc
RADIX 32'd4 RADIX 32'd4
DIVCOPIES 32'd4 DIVCOPIES 32'd4
IDIV_ON_FPU 0
deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc
IDIV_ON_FPU 1 IDIV_ON_FPU 1
@ -203,95 +216,95 @@ IDIV_ON_FPU 1
# RAM latency and Burst mode for bus stress testing # RAM latency and Burst mode for bus stress testing
deriv ram_0_0_rv64gc rv64gc deriv ram_0_0_rv64gc rv64gc
RAM_LATENCY 0 RAM_LATENCY 32'd0
BURST_EN 0 BURST_EN 0
deriv ram_1_0_rv64gc rv64gc deriv ram_1_0_rv64gc rv64gc
RAM_LATENCY 1 RAM_LATENCY 32'd1
BURST_EN 0 BURST_EN 0
deriv ram_2_0_rv64gc rv64gc deriv ram_2_0_rv64gc rv64gc
RAM_LATENCY 2 RAM_LATENCY 32'd2
BURST_EN 0 BURST_EN 0
deriv ram_1_1_rv64gc rv64gc deriv ram_1_1_rv64gc rv64gc
RAM_LATENCY 1 RAM_LATENCY 32'd1
BURST_EN 1 BURST_EN 1
deriv ram_2_1_rv64gc rv64gc deriv ram_2_1_rv64gc rv64gc
RAM_LATENCY 2 RAM_LATENCY 32'd2
BURST_EN 1 BURST_EN 1
# Branch predictor simulations # Branch predictor simulations
deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc
BPRED_SIZE 6 BPRED_SIZE 32'd6
deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc
BPRED_SIZE 8 BPRED_SIZE 32'd8
deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
BPRED_SIZE 10 BPRED_SIZE 32'd10
deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc
BPRED_SIZE 12 BPRED_SIZE 32'd12
deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc
BPRED_SIZE 14 BPRED_SIZE 32'd14
deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc
BPRED_SIZE 16 BPRED_SIZE 32'd16
deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT BPRED_TYPE `BP_TWOBIT
deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
RAS_SIZE 2 RAS_SIZE 32'd2
deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc
RAS_SIZE 3 RAS_SIZE 32'd3
deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc
RAS_SIZE 4 RAS_SIZE 32'd4
deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc
RAS_SIZE 6 RAS_SIZE 32'd6
deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
RAS_SIZE 10 RAS_SIZE 32'd10
deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
RAS_SIZE 16 RAS_SIZE 32'd16
deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc
BTB_SIZE 6 BTB_SIZE 32'd6
deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc
BTB_SIZE 8 BTB_SIZE 32'd8
deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc
BTB_SIZE 12 BTB_SIZE 32'd12
deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc
BTB_SIZE 14 BTB_SIZE 32'd14
deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc
BTB_SIZE 16 BTB_SIZE 32'd16
deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
INSTR_CLASS_PRED 0 INSTR_CLASS_PRED 0
@ -366,6 +379,7 @@ INSTR_CLASS_PRED 0
deriv noicache_rv32gc rv32gc deriv noicache_rv32gc rv32gc
ICACHE_SUPPORTED 0 ICACHE_SUPPORTED 0
VIRTMEM_SUPPORTED 0
deriv nodcache_rv32gc rv32gc deriv nodcache_rv32gc rv32gc
DCACHE_SUPPORTED 0 DCACHE_SUPPORTED 0
@ -374,93 +388,108 @@ deriv nocache_rv32gc rv32gc
ICACHE_SUPPORTED 0 ICACHE_SUPPORTED 0
DCACHE_SUPPORTED 0 DCACHE_SUPPORTED 0
deriv way_1_4096_512_rv32gc rv32gc
DCACHE_NUMWAYS 1
DCACHE_WAYSIZEINBYTES 4096
DCACHE_LINELENINBITS 512
ICACHE_NUMWAYS 1
ICACHE_WAYSIZEINBYTES 4096
ICACHE_LINELENINBITS 512
deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 1
ICACHE_NUMWAYS 1
deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 4
ICACHE_NUMWAYS 4
deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 8
ICACHE_NUMWAYS 8
deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc
DCACHE_WAYSIZEINBYTES 2048
ICACHE_WAYSIZEINBYTES 2048
deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc
DCACHE_LINELENINBITS 256
ICACHE_LINELENINBITS 256
deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc
DCACHE_LINELENINBITS 1024
ICACHE_LINELENINBITS 1024
deriv noicache_rv64gc rv64gc deriv noicache_rv64gc rv64gc
ICACHE_SUPPORTED 0 ICACHE_SUPPORTED 0
VIRTMEM_SUPPORTED 0
SVPBMT_SUPPORTED 0
SVNAPOT_SUPPORTED 0
deriv nodcache_rv64gc rv64gc deriv nodcache_rv64gc rv64gc
DCACHE_SUPPORTED 0 DCACHE_SUPPORTED 0
VIRTMEM_SUPPORTED 0
ZICBOM_SUPPORTED 0
ZICBOZ_SUPPORTED 0
SVPBMT_SUPPORTED 0
SVNAPOT_SUPPORTED 0
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
deriv nocache_rv64gc rv64gc deriv nocache_rv64gc rv64gc
ICACHE_SUPPORTED 0 ICACHE_SUPPORTED 0
DCACHE_SUPPORTED 0 DCACHE_SUPPORTED 0
VIRTMEM_SUPPORTED 0
ZICBOM_SUPPORTED 0
ZICBOZ_SUPPORTED 0
SVPBMT_SUPPORTED 0
SVNAPOT_SUPPORTED 0
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
deriv way_1_4096_512_rv32gc rv32gc
DCACHE_NUMWAYS 32'd1
DCACHE_WAYSIZEINBYTES 32'd4096
DCACHE_LINELENINBITS 32'd512
ICACHE_NUMWAYS 32'd1
ICACHE_WAYSIZEINBYTES 32'd4096
ICACHE_LINELENINBITS 32'd512
deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 32'd1
ICACHE_NUMWAYS 32'd1
deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 32'd4
ICACHE_NUMWAYS 32'd4
deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 32'd8
ICACHE_NUMWAYS 32'd8
deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc
DCACHE_WAYSIZEINBYTES 32'd2048
ICACHE_WAYSIZEINBYTES 32'd2048
deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc
DCACHE_LINELENINBITS 32'd256
ICACHE_LINELENINBITS 32'd256
deriv way_1_4096_512_rv64gc rv64gc deriv way_1_4096_512_rv64gc rv64gc
DCACHE_NUMWAYS 1 DCACHE_NUMWAYS 32'd1
DCACHE_WAYSIZEINBYTES 4096 DCACHE_WAYSIZEINBYTES 32'd4096
DCACHE_LINELENINBITS 512 DCACHE_LINELENINBITS 32'd512
ICACHE_NUMWAYS 1 ICACHE_NUMWAYS 32'd1
ICACHE_WAYSIZEINBYTES 4096 ICACHE_WAYSIZEINBYTES 32'd4096
ICACHE_LINELENINBITS 512 ICACHE_LINELENINBITS 32'd512
deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS 1 DCACHE_NUMWAYS 32'd1
ICACHE_NUMWAYS 1 ICACHE_NUMWAYS 32'd1
deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS 4 DCACHE_NUMWAYS 32'd4
ICACHE_NUMWAYS 4 ICACHE_NUMWAYS 32'd4
deriv way_8_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS 32'd8
ICACHE_NUMWAYS 32'd8
deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc
DCACHE_WAYSIZEINBYTES 2048 DCACHE_WAYSIZEINBYTES 32'd2048
ICACHE_WAYSIZEINBYTES 2048 ICACHE_WAYSIZEINBYTES 32'd2048
deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc
DCACHE_LINELENINBITS 256 DCACHE_LINELENINBITS 32'd256
ICACHE_LINELENINBITS 256 ICACHE_LINELENINBITS 32'd256
deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc
DCACHE_LINELENINBITS 1024 DCACHE_LINELENINBITS 32'd1024
ICACHE_LINELENINBITS 1024 ICACHE_LINELENINBITS 32'd1024
# TLB Size variants # TLB Size variants
deriv tlb2_rv32gc rv32gc deriv tlb2_rv32gc rv32gc
ITLB_ENTRIES 2 ITLB_ENTRIES 32'd2
DTLB_ENTRIES 2 DTLB_ENTRIES 32'd2
deriv tlb16_rv32gc rv32gc deriv tlb16_rv32gc rv32gc
ITLB_ENTRIES 16 ITLB_ENTRIES 32'd16
DTLB_ENTRIES 16 DTLB_ENTRIES 32'd16
deriv tlb2_rv64gc rv64gc deriv tlb2_rv64gc rv64gc
ITLB_ENTRIES 2 ITLB_ENTRIES 32'd2
DTLB_ENTRIES 2 DTLB_ENTRIES 32'd2
deriv tlb16_rv64gc rv64gc deriv tlb16_rv64gc rv64gc
ITLB_ENTRIES 16 ITLB_ENTRIES 32'd16
DTLB_ENTRIES 16 DTLB_ENTRIES 32'd16
# Feature variants # Feature variants

2
config/shared/config-shared.vh
View File

@ -103,7 +103,7 @@ localparam RESBITS = DIVMINb + LOGR; // number of bits in a result: r intege
localparam FPDUR = (RESBITS-1)/RK + 1 ; // ceiling((r+b)/rk) localparam FPDUR = (RESBITS-1)/RK + 1 ; // ceiling((r+b)/rk)
localparam DIVb = FPDUR*RK - LOGR; // divsqrt fractional bits, so total number of bits is a multiple of rk after r integer bits localparam DIVb = FPDUR*RK - LOGR; // divsqrt fractional bits, so total number of bits is a multiple of rk after r integer bits
localparam DURLEN = $clog2(FPDUR); // enough bits to count the duration localparam DURLEN = $clog2(FPDUR); // enough bits to count the duration
localparam DIVBLEN = $clog2(DIVb); // enough bits to count number of fractional bits localparam DIVBLEN = $clog2(DIVb+1); // enough bits to count number of fractional bits + 1 integer bit
// largest length in IEU/FPU // largest length in IEU/FPU
localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF)); // max(XLEN, NF) localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF)); // max(XLEN, NF)

1
config/shared/parameter-defs.vh
View File

@ -102,6 +102,7 @@ localparam cvw_t P = '{
BPRED_NUM_LHR : BPRED_NUM_LHR, BPRED_NUM_LHR : BPRED_NUM_LHR,
BTB_SIZE : BTB_SIZE, BTB_SIZE : BTB_SIZE,
RAS_SIZE : RAS_SIZE, RAS_SIZE : RAS_SIZE,
INSTR_CLASS_PRED : INSTR_CLASS_PRED,
RADIX : RADIX, RADIX : RADIX,
DIVCOPIES : DIVCOPIES, DIVCOPIES : DIVCOPIES,
ZBA_SUPPORTED : ZBA_SUPPORTED, ZBA_SUPPORTED : ZBA_SUPPORTED,

43
sim/lint-wally
View File

@ -1,19 +1,48 @@
#!/bin/bash #!/bin/bash
# check for warnings in Verilog code # check for warnings in Verilog code
# The verilator lint tool is faster and better than Questa so it is best to run this first. # The verilator lint tool is faster and better than Questa so it is best to run this first.
export PATH=$PATH:/usr/local/bin/ export PATH=$PATH:/usr/local/bin/
verilator=`which verilator` verilator=`which verilator`
basepath=$(dirname $0)/.. basepath=$(dirname $0)/..
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do RED='\033[0;31m'
#for config in rv64gc; do GREEN='\033[0;32m'
echo "$config linting..." NC='\033[0m' # No Color
if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then fails=0
echo "Exiting after $config lint due to errors or warnings"
exit 1 if [ "$1" == "-nightly" ]; then
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
derivconfigs=`ls $WALLY/config/deriv`
for entry in $derivconfigs
do
if [[ $entry != *"syn_sram"* ]]; then # ignore syn_sram* configs that contain undefined module
configs[${#configs[@]}]=$entry
fi
done
else
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i div_2_1i_rv64gc ) # add fdqh_rv64gc when working
fi
for config in ${configs[@]}; do
# echo "$config linting..."
if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
if [ "$1" == "-nightly" ]; then
echo -e "${RED}$config failed lint${NC}"
fails=$((fails+1))
else
echo -e "${RED}$config fails with lint errors or warnings"
exit 1
fi
else
echo -e "${GREEN}$config passed lint${NC}"
fi fi
done done
echo "All lints run with no errors or warnings" if [ $fails > 0 ]; then
echo -e "${RED}Linting failed for $fails of ${#configs[@]} configurations"
exit 1
fi
echo -e "${GREEN}All ${#configs[@]} lints run with no errors or warnings"
# --lint-only just runs lint rather than trying to compile and simulate # --lint-only just runs lint rather than trying to compile and simulate
# -I points to the include directory where files such as `include config.vh are found # -I points to the include directory where files such as `include config.vh are found

148
sim/regression-wally
View File

@ -29,6 +29,7 @@ os.chdir(regressionDir)
coverage = '-coverage' in sys.argv coverage = '-coverage' in sys.argv
fp = '-fp' in sys.argv fp = '-fp' in sys.argv
nightly = '-nightly' in sys.argv
TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
# name: the name of this test configuration (used in printing human-readable # name: the name of this test configuration (used in printing human-readable
@ -40,14 +41,20 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
# be any pattern grep accepts, see `man 1 grep` for more info). # be any pattern grep accepts, see `man 1 grep` for more info).
# edit this list to add more test cases # edit this list to add more test cases
configs = [ if (nightly):
TestCase( nightMode = "-nightly";
name="lints", configs = []
variant="all", else:
cmd="./lint-wally | tee {}", nightMode = "";
grepstr="All lints run with no errors or warnings" configs = [
) TestCase(
] name="lints",
variant="all",
cmd="./lint-wally " + nightMode + " | tee {}",
grepstr="All lints run with no errors or warnings"
)
]
def getBuildrootTC(boot): def getBuildrootTC(boot):
INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
@ -78,7 +85,7 @@ for test in tests64i:
configs.append(tc) configs.append(tc)
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zbc", "arch32zfad",
#tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"]
for test in tests32gc: for test in tests32gc:
tc = TestCase( tc = TestCase(
@ -117,29 +124,26 @@ for test in tests32e:
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
ahbTests = [("0", "0"), ("0", "1"), ("1", "0"), ("1", "1"), ("2", "0"), ("2", "1")] tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad",
for test in ahbTests: "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working
tc = TestCase(
name="ram_latency_" + test[0] + "_burst_en_" + test[1],
variant="ahb",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"]
#tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
# "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] # "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"]
if (coverage): # delete all but 64gc tests when running coverage if (coverage): # delete all but 64gc tests when running coverage
configs = [] configs = []
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
"arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv",
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zicboz", "arch64zcb", "arch64zba", "arch64zbb", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz"
if (fp): if (fp):
tests64gc.append("arch64f") tests64gc.append("arch64f")
tests64gc.append("arch64d") tests64gc.append("arch64d")
tests64gc.append("arch64zfh")
tests64gc.append("arch64f_fma") tests64gc.append("arch64f_fma")
tests64gc.append("arch64d_fma") tests64gc.append("arch64d_fma") # *** add arch64zfh_fma when available(see riscv-arch-test pr 367)
tests64gc.append("arch64f_divsqrt")
tests64gc.append("arch64d_divsqrt")
tests64gc.append("arch64zfh_divsqrt")
tests64gc.append("arch64zfaf")
tests64gc.append("arch64zfad")
coverStr = '-coverage' coverStr = '-coverage'
else: else:
coverStr = '' coverStr = ''
@ -150,7 +154,103 @@ for test in tests64gc:
cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+" " + coverStr + "\n!", cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+" " + coverStr + "\n!",
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
# run derivative configurations if requested
if (nightly):
derivconfigtests = [
["tlb2_rv32gc", ["wally32priv"]],
["tlb16_rv32gc", ["wally32priv"]],
["tlb2_rv64gc", ["wally64priv"]],
["tlb16_rv64gc", ["wally64priv"]],
["way_1_4096_512_rv32gc", ["arch32i"]],
["way_2_4096_512_rv32gc", ["arch32i"]],
["way_8_4096_512_rv32gc", ["arch32i"]],
["way_4_2048_512_rv32gc", ["arch32i"]],
["way_4_4096_256_rv32gc", ["arch32i"]],
["way_1_4096_512_rv64gc", ["arch64i"]],
["way_2_4096_512_rv64gc", ["arch64i"]],
["way_8_4096_512_rv64gc", ["arch64i"]],
["way_4_2048_512_rv64gc", ["arch64i"]],
["way_4_4096_256_rv64gc", ["arch64i"]],
["way_4_4096_1024_rv64gc", ["arch64i"]],
["ram_0_0_rv64gc", ["ahb64"]],
["ram_1_0_rv64gc", ["ahb64"]],
["ram_1_1_rv64gc", ["ahb64"]],
["ram_2_0_rv64gc", ["ahb64"]],
["ram_2_1_rv64gc", ["ahb64"]],
["noicache_rv32gc", ["ahb32"]],
# cacheless designs will not work until DTIM supports FLEN > XLEN
# ["nodcache_rv32gc", ["ahb32"]],
# ["nocache_rv32gc", ["ahb32"]],
["noicache_rv64gc", ["ahb64"]],
["nodcache_rv64gc", ["ahb64"]],
["nocache_rv64gc", ["ahb64"]],
### add misaligned tests
["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
# enable floating-point tests when lint is fixed
# ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
# ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
# ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
# ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
# ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
# ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
# ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
# ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
# ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
# ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
]
for test in derivconfigtests:
config = test[0];
tests = test[1];
for t in tests:
tc = TestCase(
name=t,
variant=config,
cmd="vsim > {} -c <<!\ndo wally-batch.do "+config+" "+t+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
tests32e = ["arch32e"]
for test in tests32e:
tc = TestCase(
name=test,
variant="rv32e",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32e "+test+"\n!",
grepstr="All tests ran without failures")
configs.append(tc)
import os import os
from multiprocessing import Pool, TimeoutError from multiprocessing import Pool, TimeoutError

33
sim/wally-batch.do
View File

@ -21,14 +21,7 @@
onbreak {resume} onbreak {resume}
# create library # create library
if {$2 eq "ahb"} { if {$2 eq "configOptions"} {
if [file exists wkdir/work_${1}_${2}_${3}_${4}] {
vdel -lib wkdir/work_${1}_${2}_${3}_${4} -all
}
vlib wkdir/work_${1}_${2}_${3}_${4}
} elseif {$2 eq "configOptions"} {
if [file exists wkdir/work_${1}_${3}_${4}] { if [file exists wkdir/work_${1}_${3}_${4}] {
vdel -lib wkdir/work_${1}_${3}_${4} -all vdel -lib wkdir/work_${1}_${3}_${4} -all
} }
@ -59,7 +52,7 @@ if {$argc >= 3} {
# default to config/rv64ic, but allow this to be overridden at the command line. For example: # default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined-batch.do ../config/rv32imc rv32imc # do wally-pipelined-batch.do ../config/rv32imc rv32imc
if {$2 eq "buildroot"} { if {$2 eq "buildroot"} {
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation # start and run simulation
if { $coverage } { if { $coverage } {
echo "wally-batch buildroot coverage" echo "wally-batch buildroot coverage"
@ -74,7 +67,7 @@ if {$2 eq "buildroot"} {
run -all run -all
exec ./slack-notifier/slack-notifier.py exec ./slack-notifier/slack-notifier.py
} elseif {$2 eq "buildroot-no-trace"} { } elseif {$2 eq "buildroot-no-trace"} {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation # start and run simulation
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
@ -86,22 +79,6 @@ if {$2 eq "buildroot"} {
run -all run -all
run -all run -all
exec ./slack-notifier/slack-notifier.py exec ./slack-notifier/slack-notifier.py
} elseif {$2 eq "ahb"} {
vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
vsim -lib wkdir/work_${1}_${2}_${3}_${4} testbenchopt -fatal 7
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
#vsim -coverage -lib work_$2 workopt_$2
# power add generates the logging necessary for said generation.
# power add -r /dut/core/*
run -all
# power off -r /dut/core/*
} elseif {$2 eq "configOptions"} { } elseif {$2 eq "configOptions"} {
# set arguments " " # set arguments " "
# for {set i 5} {$i <= $argc} {incr i} { # for {set i 5} {$i <= $argc} {incr i} {
@ -112,7 +89,7 @@ if {$2 eq "buildroot"} {
# **** fix this so we can pass any number of +defines. # **** fix this so we can pass any number of +defines.
# only allows 3 right now # only allows 3 right now
vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7 vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt
@ -126,7 +103,7 @@ if {$2 eq "buildroot"} {
# power off -r /dut/core/* # power off -r /dut/core/*
} else { } else {
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
if {$coverage} { if {$coverage} {

7
sim/wally.do
View File

@ -77,12 +77,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
run 20 ms run 20 ms
} else { } else {
if {$2 eq "ahb"} { vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
} else {
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
}
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
vsim workopt +nowarn3829 -fatal 7 vsim workopt +nowarn3829 -fatal 7

2
src/cache/cacheLRU.sv vendored
View File

@ -143,7 +143,7 @@ module cacheLRU
// This is a two port memory. // This is a two port memory.
// Every cycle must read from CacheSetData and each load/store must write the new LRU. // Every cycle must read from CacheSetData and each load/store must write the new LRU.
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0;
if(CacheEn) begin if(CacheEn) begin
if(ClearValid & ~FlushStage) if(ClearValid & ~FlushStage)
LRUMemory[PAdr] <= '0; LRUMemory[PAdr] <= '0;

1
src/cvw.sv
View File

@ -162,6 +162,7 @@ typedef struct packed {
int BPRED_SIZE; int BPRED_SIZE;
int BTB_SIZE; int BTB_SIZE;
int RAS_SIZE; int RAS_SIZE;
logic INSTR_CLASS_PRED; // is class predictor enabled
// FPU division architecture // FPU division architecture
int RADIX; int RADIX;

23
src/fpu/fpu.sv
View File

@ -270,15 +270,22 @@ module fpu import cvw::*; #(parameter cvw_t P) (
// floating-point load immediate: fli // floating-point load immediate: fli
if (P.ZFA_SUPPORTED) begin if (P.ZFA_SUPPORTED) begin
logic [4:0] Rs1E; logic [4:0] Rs1E;
logic [1:0] Fmt2E; // Two-bit format field from instruction
flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E); flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E);
fli #(P) fli(.Rs1(Rs1E), .Fmt(FmtE), .Imm(FliResE)); flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E);
fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE));
end else assign FliResE = '0; end else assign FliResE = '0;
// fmv.*.x: NaN Box SrcA to extend integer to requested FP size // fmv.*.x: NaN Box SrcA to extend integer to requested FP size
if(P.FPSIZES == 1) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}; if(P.FPSIZES == 1)
if (P.FLEN >= P.XLEN) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
else assign PreIntSrcE = ForwardedSrcAE[P.FLEN-1:0];
else if(P.FPSIZES == 2) else if(P.FPSIZES == 2)
mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE); if (P.FLEN >= P.XLEN)
mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE);
else
mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, ForwardedSrcAE[P.FLEN-1:0], FmtE, PreIntSrcE);
else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN
mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]},
@ -287,7 +294,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
FmtE, PreIntSrcE); // NaN boxing zeroes FmtE, PreIntSrcE); // NaN boxing zeroes
end end
// fmvp.*.x: Select pair of registers // fmvp.*.x: Select pair of registers
if (P.ZFA_SUPPORTED & (P.XLEN==32 & P.D_SUPPORTED) | (P.XLEN==64 & P.Q_SUPPORTED)) if (P.ZFA_SUPPORTED & (P.FLEN == 2*P.XLEN))
assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x
else assign IntSrcE = PreIntSrcE; else assign IntSrcE = PreIntSrcE;
@ -311,11 +318,11 @@ module fpu import cvw::*; #(parameter cvw_t P) (
end end
// sign extend to XLEN if necessary // sign extend to XLEN if necessary
if (P.FLEN>P.XLEN) if (P.FLEN >= 2*P.XLEN)
if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* if (P.ZFA_SUPPORTED & P.FLEN == 2*P.XLEN) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; else assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
else else
assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE};
mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE); mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
// E/M pipe registers // E/M pipe registers

6
src/lsu/lsu.sv
View File

@ -406,7 +406,11 @@ module lsu import cvw::*; #(parameter cvw_t P) (
end end
if (P.F_SUPPORTED) if (P.F_SUPPORTED)
mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM); if (P.FLEN >= P.XLEN)
mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
else
mux2 #(P.LLEN) datamux(IMAWriteDataM, {{{P.XLEN-P.FLEN}{1'b0}}, FWriteDataM}, FpLoadStoreM, IMAFWriteDataM);
else assign IMAFWriteDataM = IMAWriteDataM; else assign IMAFWriteDataM = IMAWriteDataM;
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////

2
src/uncore/ram_ahb.sv
View File

@ -99,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
endcase endcase
end end
assign CycleFlag = Cycle == P.RAM_LATENCY; assign CycleFlag = Cycle == P.RAM_LATENCY[7:0];
assign CntEn = NextState == DELAY; assign CntEn = NextState == DELAY;
assign DelayReady = NextState == DELAY; assign DelayReady = NextState == DELAY;
assign CntRst = NextState == READY; assign CntRst = NextState == READY;

89
testbench/common/riscvassertions.sv
View File

@ -21,53 +21,52 @@
module riscvassertions import cvw::*; #(parameter cvw_t P); module riscvassertions import cvw::*; #(parameter cvw_t P);
initial begin initial begin
assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support");
assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");
assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)");
assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported"); assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported");
assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $fatal(1, "Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size");
assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2");
assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF"); assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF");
assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported");
assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache");
assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache");
assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED.");
assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16");
assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally."); assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally.");
assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED");
assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED");
assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $fatal(1, "At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM requires DCACHE_SUPPORTED"); assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED");
assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ requires DCACHE_SUPPORTED"); assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED");
assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP requires DCACHE_SUPPORTED"); assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVPBMT requires VIRTMEM_SUPPORTED and RV64"); assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVNAPOT requires VIRTMEM_SUPPORTED and RV64"); assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $fatal(1, "ZCB requires M and ZBB (and also ZBA for RV64)");
assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $error("ZCB requires M and ZBB (and also ZBA for RV64)"); assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $fatal(1, "C and ZCA/ZCD/ZCF cannot simultaneously be supported");
assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $error("C and ZCA/ZCD/ZCF cannot simultaneously be supported"); assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA");
assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $error("ZCF or ZCD requires ZCA"); assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $error("ZCF requires F"); assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $error("ZCD requires D");
end end
endmodule endmodule

11
testbench/testbench.sv
View File

@ -104,6 +104,8 @@ module testbench;
"arch64d": if (P.D_SUPPORTED) tests = arch64d; "arch64d": if (P.D_SUPPORTED) tests = arch64d;
"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma; "arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
"arch64f_divsqrt": if (P.F_SUPPORTED) tests = arch64f_divsqrt;
"arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt;
"arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei; "arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei;
"arch64zicond": if (P.ZICOND_SUPPORTED) tests = arch64zicond; "arch64zicond": if (P.ZICOND_SUPPORTED) tests = arch64zicond;
"imperas64i": tests = imperas64i; "imperas64i": tests = imperas64i;
@ -119,7 +121,7 @@ module testbench;
"wally64periph": tests = wally64periph; "wally64periph": tests = wally64periph;
"coremark": tests = coremark; "coremark": tests = coremark;
"fpga": tests = fpga; "fpga": tests = fpga;
"ahb" : tests = ahb; "ahb64" : tests = ahb64;
"coverage64gc" : tests = coverage64gc; "coverage64gc" : tests = coverage64gc;
"arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba; "arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba;
"arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb; "arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb;
@ -128,6 +130,8 @@ module testbench;
"arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz; "arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz;
"arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb; "arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb;
"arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh; "arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh;
// "arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma; *** not yet in riscv-arch-tst PR367
"arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt;
"arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf;
"arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad;
endcase endcase
@ -145,6 +149,8 @@ module testbench;
"arch32d": if (P.D_SUPPORTED) tests = arch32d; "arch32d": if (P.D_SUPPORTED) tests = arch32d;
"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
"arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma; "arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma;
"arch32f_divsqrt": if (P.F_SUPPORTED) tests = arch32f_divsqrt;
"arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt;
"arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei; "arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei;
"arch32zicond": if (P.ZICOND_SUPPORTED) tests = arch32zicond; "arch32zicond": if (P.ZICOND_SUPPORTED) tests = arch32zicond;
"imperas32i": tests = imperas32i; "imperas32i": tests = imperas32i;
@ -156,6 +162,7 @@ module testbench;
"wally32i": tests = wally32i; "wally32i": tests = wally32i;
"wally32priv": tests = wally32priv; "wally32priv": tests = wally32priv;
"wally32periph": tests = wally32periph; "wally32periph": tests = wally32periph;
"ahb32" : tests = ahb32;
"embench": tests = embench; "embench": tests = embench;
"coremark": tests = coremark; "coremark": tests = coremark;
"arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba; "arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba;
@ -165,6 +172,8 @@ module testbench;
"arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz; "arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz;
"arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb; "arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb;
"arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh; "arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh;
// "arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma; *** not yet in riscv-arch-tst PR367
"arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt;
"arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf;
"arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad; "arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad;
endcase endcase

245
testbench/tests.vh
View File

@ -1126,10 +1126,10 @@ string imperas32f[] = '{
// "rv64i_m/F/src/fnmsub_b15-01.S" // "rv64i_m/F/src/fnmsub_b15-01.S"
}; };
string arch64f[] = '{ string arch64f_divsqrt[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv64i_m/F/src/fdiv_b1-01.S",
"rv64i_m/F/src/fdiv_b20-01.S", "rv64i_m/F/src/fdiv_b20-01.S",
"rv64i_m/F/src/fdiv_b1-01.S",
"rv64i_m/F/src/fdiv_b2-01.S", "rv64i_m/F/src/fdiv_b2-01.S",
"rv64i_m/F/src/fdiv_b21-01.S", "rv64i_m/F/src/fdiv_b21-01.S",
"rv64i_m/F/src/fdiv_b3-01.S", "rv64i_m/F/src/fdiv_b3-01.S",
@ -1147,7 +1147,11 @@ string imperas32f[] = '{
"rv64i_m/F/src/fsqrt_b5-01.S", "rv64i_m/F/src/fsqrt_b5-01.S",
"rv64i_m/F/src/fsqrt_b7-01.S", "rv64i_m/F/src/fsqrt_b7-01.S",
"rv64i_m/F/src/fsqrt_b8-01.S", "rv64i_m/F/src/fsqrt_b8-01.S",
"rv64i_m/F/src/fsqrt_b9-01.S", "rv64i_m/F/src/fsqrt_b9-01.S"
};
string arch64f[] = '{
`RISCVARCHTEST,
"rv64i_m/F/src/fadd_b10-01.S", "rv64i_m/F/src/fadd_b10-01.S",
"rv64i_m/F/src/fadd_b1-01.S", "rv64i_m/F/src/fadd_b1-01.S",
"rv64i_m/F/src/fadd_b11-01.S", "rv64i_m/F/src/fadd_b11-01.S",
@ -1178,17 +1182,6 @@ string imperas32f[] = '{
"rv64i_m/F/src/fcvt.wu.s_b27-01.S", "rv64i_m/F/src/fcvt.wu.s_b27-01.S",
"rv64i_m/F/src/fcvt.wu.s_b28-01.S", "rv64i_m/F/src/fcvt.wu.s_b28-01.S",
"rv64i_m/F/src/fcvt.wu.s_b29-01.S", "rv64i_m/F/src/fcvt.wu.s_b29-01.S",
"rv64i_m/F/src/fdiv_b1-01.S",
"rv64i_m/F/src/fdiv_b20-01.S",
"rv64i_m/F/src/fdiv_b2-01.S",
"rv64i_m/F/src/fdiv_b21-01.S",
"rv64i_m/F/src/fdiv_b3-01.S",
"rv64i_m/F/src/fdiv_b4-01.S",
"rv64i_m/F/src/fdiv_b5-01.S",
"rv64i_m/F/src/fdiv_b6-01.S",
"rv64i_m/F/src/fdiv_b7-01.S",
"rv64i_m/F/src/fdiv_b8-01.S",
"rv64i_m/F/src/fdiv_b9-01.S",
"rv64i_m/F/src/feq_b1-01.S", "rv64i_m/F/src/feq_b1-01.S",
"rv64i_m/F/src/feq_b19-01.S", "rv64i_m/F/src/feq_b19-01.S",
"rv64i_m/F/src/fle_b1-01.S", "rv64i_m/F/src/fle_b1-01.S",
@ -1269,15 +1262,6 @@ string imperas32f[] = '{
"rv64i_m/F/src/fsgnj_b1-01.S", "rv64i_m/F/src/fsgnj_b1-01.S",
"rv64i_m/F/src/fsgnjn_b1-01.S", "rv64i_m/F/src/fsgnjn_b1-01.S",
"rv64i_m/F/src/fsgnjx_b1-01.S", "rv64i_m/F/src/fsgnjx_b1-01.S",
"rv64i_m/F/src/fsqrt_b1-01.S",
"rv64i_m/F/src/fsqrt_b20-01.S",
"rv64i_m/F/src/fsqrt_b2-01.S",
"rv64i_m/F/src/fsqrt_b3-01.S",
"rv64i_m/F/src/fsqrt_b4-01.S",
"rv64i_m/F/src/fsqrt_b5-01.S",
"rv64i_m/F/src/fsqrt_b7-01.S",
"rv64i_m/F/src/fsqrt_b8-01.S",
"rv64i_m/F/src/fsqrt_b9-01.S",
"rv64i_m/F/src/fsub_b10-01.S", "rv64i_m/F/src/fsub_b10-01.S",
"rv64i_m/F/src/fsub_b1-01.S", "rv64i_m/F/src/fsub_b1-01.S",
"rv64i_m/F/src/fsub_b11-01.S", "rv64i_m/F/src/fsub_b11-01.S",
@ -1292,6 +1276,30 @@ string imperas32f[] = '{
"rv64i_m/F/src/fsw-align-01.S" "rv64i_m/F/src/fsw-align-01.S"
}; };
string arch64zfh_divsqrt[] = '{
`RISCVARCHTEST,
"rv64i_m/Zfh/src/fdiv_b20-01.S",
"rv64i_m/Zfh/src/fdiv_b1-01.S",
"rv64i_m/Zfh/src/fdiv_b2-01.S",
"rv64i_m/Zfh/src/fdiv_b21-01.S",
"rv64i_m/Zfh/src/fdiv_b3-01.S",
"rv64i_m/Zfh/src/fdiv_b4-01.S",
"rv64i_m/Zfh/src/fdiv_b5-01.S",
"rv64i_m/Zfh/src/fdiv_b6-01.S",
"rv64i_m/Zfh/src/fdiv_b7-01.S",
"rv64i_m/Zfh/src/fdiv_b8-01.S",
"rv64i_m/Zfh/src/fdiv_b9-01.S",
"rv64i_m/Zfh/src/fsqrt_b1-01.S",
"rv64i_m/Zfh/src/fsqrt_b20-01.S",
"rv64i_m/Zfh/src/fsqrt_b2-01.S",
"rv64i_m/Zfh/src/fsqrt_b3-01.S",
"rv64i_m/Zfh/src/fsqrt_b4-01.S",
"rv64i_m/Zfh/src/fsqrt_b5-01.S",
"rv64i_m/Zfh/src/fsqrt_b7-01.S",
"rv64i_m/Zfh/src/fsqrt_b8-01.S",
"rv64i_m/Zfh/src/fsqrt_b9-01.S"
};
string arch64zfh[] = '{ string arch64zfh[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv64i_m/Zfh/src/fadd_b10-01.S", "rv64i_m/Zfh/src/fadd_b10-01.S",
@ -1342,17 +1350,6 @@ string imperas32f[] = '{
"rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S",
"rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S",
"rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S",
"rv64i_m/Zfh/src/fdiv_b20-01.S",
"rv64i_m/Zfh/src/fdiv_b1-01.S",
"rv64i_m/Zfh/src/fdiv_b2-01.S",
"rv64i_m/Zfh/src/fdiv_b21-01.S",
"rv64i_m/Zfh/src/fdiv_b3-01.S",
"rv64i_m/Zfh/src/fdiv_b4-01.S",
"rv64i_m/Zfh/src/fdiv_b5-01.S",
"rv64i_m/Zfh/src/fdiv_b6-01.S",
"rv64i_m/Zfh/src/fdiv_b7-01.S",
"rv64i_m/Zfh/src/fdiv_b8-01.S",
"rv64i_m/Zfh/src/fdiv_b9-01.S",
"rv64i_m/Zfh/src/feq_b1-01.S", "rv64i_m/Zfh/src/feq_b1-01.S",
"rv64i_m/Zfh/src/feq_b19-01.S", "rv64i_m/Zfh/src/feq_b19-01.S",
"rv64i_m/Zfh/src/fle_b1-01.S", "rv64i_m/Zfh/src/fle_b1-01.S",
@ -1385,15 +1382,6 @@ string imperas32f[] = '{
"rv64i_m/Zfh/src/fsgnj_b1-01.S", "rv64i_m/Zfh/src/fsgnj_b1-01.S",
"rv64i_m/Zfh/src/fsgnjn_b1-01.S", "rv64i_m/Zfh/src/fsgnjn_b1-01.S",
"rv64i_m/Zfh/src/fsgnjx_b1-01.S", "rv64i_m/Zfh/src/fsgnjx_b1-01.S",
"rv64i_m/Zfh/src/fsqrt_b1-01.S",
"rv64i_m/Zfh/src/fsqrt_b20-01.S",
"rv64i_m/Zfh/src/fsqrt_b2-01.S",
"rv64i_m/Zfh/src/fsqrt_b3-01.S",
"rv64i_m/Zfh/src/fsqrt_b4-01.S",
"rv64i_m/Zfh/src/fsqrt_b5-01.S",
"rv64i_m/Zfh/src/fsqrt_b7-01.S",
"rv64i_m/Zfh/src/fsqrt_b8-01.S",
"rv64i_m/Zfh/src/fsqrt_b9-01.S",
"rv64i_m/Zfh/src/fsub_b10-01.S", "rv64i_m/Zfh/src/fsub_b10-01.S",
"rv64i_m/Zfh/src/fsub_b1-01.S", "rv64i_m/Zfh/src/fsub_b1-01.S",
"rv64i_m/Zfh/src/fsub_b11-01.S", "rv64i_m/Zfh/src/fsub_b11-01.S",
@ -1417,9 +1405,8 @@ string imperas32f[] = '{
// "rv64i_m/D/src/fnmsub.d_b15-01.S" // "rv64i_m/D/src/fnmsub.d_b15-01.S"
}; };
string arch64d[] = '{ string arch64d_divsqrt[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
// for speed
"rv64i_m/D/src/fdiv.d_b1-01.S", "rv64i_m/D/src/fdiv.d_b1-01.S",
"rv64i_m/D/src/fdiv.d_b20-01.S", "rv64i_m/D/src/fdiv.d_b20-01.S",
"rv64i_m/D/src/fdiv.d_b2-01.S", "rv64i_m/D/src/fdiv.d_b2-01.S",
@ -1439,8 +1426,13 @@ string imperas32f[] = '{
"rv64i_m/D/src/fsqrt.d_b5-01.S", "rv64i_m/D/src/fsqrt.d_b5-01.S",
"rv64i_m/D/src/fsqrt.d_b7-01.S", "rv64i_m/D/src/fsqrt.d_b7-01.S",
"rv64i_m/D/src/fsqrt.d_b8-01.S", "rv64i_m/D/src/fsqrt.d_b8-01.S",
"rv64i_m/D/src/fsqrt.d_b9-01.S", "rv64i_m/D/src/fsqrt.d_b9-01.S"
"rv64i_m/D/src/fadd.d_b10-01.S", };
string arch64d[] = '{
`RISCVARCHTEST,
// for speed
"rv64i_m/D/src/fadd.d_b10-01.S",
"rv64i_m/D/src/fadd.d_b1-01.S", "rv64i_m/D/src/fadd.d_b1-01.S",
"rv64i_m/D/src/fadd.d_b11-01.S", "rv64i_m/D/src/fadd.d_b11-01.S",
"rv64i_m/D/src/fadd.d_b12-01.S", "rv64i_m/D/src/fadd.d_b12-01.S",
@ -1502,17 +1494,6 @@ string imperas32f[] = '{
"rv64i_m/D/src/fcvt.wu.d_b27-01.S", "rv64i_m/D/src/fcvt.wu.d_b27-01.S",
"rv64i_m/D/src/fcvt.wu.d_b28-01.S", "rv64i_m/D/src/fcvt.wu.d_b28-01.S",
"rv64i_m/D/src/fcvt.wu.d_b29-01.S", "rv64i_m/D/src/fcvt.wu.d_b29-01.S",
"rv64i_m/D/src/fdiv.d_b1-01.S",
"rv64i_m/D/src/fdiv.d_b20-01.S",
"rv64i_m/D/src/fdiv.d_b2-01.S",
"rv64i_m/D/src/fdiv.d_b21-01.S",
"rv64i_m/D/src/fdiv.d_b3-01.S",
"rv64i_m/D/src/fdiv.d_b4-01.S",
"rv64i_m/D/src/fdiv.d_b5-01.S",
"rv64i_m/D/src/fdiv.d_b6-01.S",
"rv64i_m/D/src/fdiv.d_b7-01.S",
"rv64i_m/D/src/fdiv.d_b8-01.S",
"rv64i_m/D/src/fdiv.d_b9-01.S",
"rv64i_m/D/src/feq.d_b1-01.S", "rv64i_m/D/src/feq.d_b1-01.S",
"rv64i_m/D/src/feq.d_b19-01.S", "rv64i_m/D/src/feq.d_b19-01.S",
"rv64i_m/D/src/fle.d_b1-01.S", "rv64i_m/D/src/fle.d_b1-01.S",
@ -1590,15 +1571,6 @@ string imperas32f[] = '{
"rv64i_m/D/src/fsgnj.d_b1-01.S", "rv64i_m/D/src/fsgnj.d_b1-01.S",
"rv64i_m/D/src/fsgnjn.d_b1-01.S", "rv64i_m/D/src/fsgnjn.d_b1-01.S",
"rv64i_m/D/src/fsgnjx.d_b1-01.S", "rv64i_m/D/src/fsgnjx.d_b1-01.S",
"rv64i_m/D/src/fsqrt.d_b1-01.S",
"rv64i_m/D/src/fsqrt.d_b20-01.S",
"rv64i_m/D/src/fsqrt.d_b2-01.S",
"rv64i_m/D/src/fsqrt.d_b3-01.S",
"rv64i_m/D/src/fsqrt.d_b4-01.S",
"rv64i_m/D/src/fsqrt.d_b5-01.S",
"rv64i_m/D/src/fsqrt.d_b7-01.S",
"rv64i_m/D/src/fsqrt.d_b8-01.S",
"rv64i_m/D/src/fsqrt.d_b9-01.S",
"rv64i_m/D/src/fssub.d_b10-01.S", "rv64i_m/D/src/fssub.d_b10-01.S",
"rv64i_m/D/src/fssub.d_b1-01.S", "rv64i_m/D/src/fssub.d_b1-01.S",
"rv64i_m/D/src/fssub.d_b11-01.S", "rv64i_m/D/src/fssub.d_b11-01.S",
@ -1754,6 +1726,30 @@ string arch64zbs[] = '{
// "rv32i_m/F/src/fnmsub_b15-01.S" // "rv32i_m/F/src/fnmsub_b15-01.S"
}; };
string arch32f_divsqrt[] = '{
`RISCVARCHTEST,
"rv32i_m/F/src/fdiv_b20-01.S",
"rv32i_m/F/src/fdiv_b1-01.S",
"rv32i_m/F/src/fdiv_b2-01.S",
"rv32i_m/F/src/fdiv_b21-01.S",
"rv32i_m/F/src/fdiv_b3-01.S",
"rv32i_m/F/src/fdiv_b4-01.S",
"rv32i_m/F/src/fdiv_b5-01.S",
"rv32i_m/F/src/fdiv_b6-01.S",
"rv32i_m/F/src/fdiv_b7-01.S",
"rv32i_m/F/src/fdiv_b8-01.S",
"rv32i_m/F/src/fdiv_b9-01.S",
"rv32i_m/F/src/fsqrt_b1-01.S",
"rv32i_m/F/src/fsqrt_b20-01.S",
"rv32i_m/F/src/fsqrt_b2-01.S",
"rv32i_m/F/src/fsqrt_b3-01.S",
"rv32i_m/F/src/fsqrt_b4-01.S",
"rv32i_m/F/src/fsqrt_b5-01.S",
"rv32i_m/F/src/fsqrt_b7-01.S",
"rv32i_m/F/src/fsqrt_b8-01.S",
"rv32i_m/F/src/fsqrt_b9-01.S"
};
string arch32f[] = '{ string arch32f[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/F/src/fadd_b10-01.S", "rv32i_m/F/src/fadd_b10-01.S",
@ -1786,17 +1782,6 @@ string arch64zbs[] = '{
"rv32i_m/F/src/fcvt.wu.s_b27-01.S", "rv32i_m/F/src/fcvt.wu.s_b27-01.S",
"rv32i_m/F/src/fcvt.wu.s_b28-01.S", "rv32i_m/F/src/fcvt.wu.s_b28-01.S",
"rv32i_m/F/src/fcvt.wu.s_b29-01.S", "rv32i_m/F/src/fcvt.wu.s_b29-01.S",
"rv32i_m/F/src/fdiv_b20-01.S",
"rv32i_m/F/src/fdiv_b1-01.S",
"rv32i_m/F/src/fdiv_b2-01.S",
"rv32i_m/F/src/fdiv_b21-01.S",
"rv32i_m/F/src/fdiv_b3-01.S",
"rv32i_m/F/src/fdiv_b4-01.S",
"rv32i_m/F/src/fdiv_b5-01.S",
"rv32i_m/F/src/fdiv_b6-01.S",
"rv32i_m/F/src/fdiv_b7-01.S",
"rv32i_m/F/src/fdiv_b8-01.S",
"rv32i_m/F/src/fdiv_b9-01.S",
"rv32i_m/F/src/feq_b1-01.S", "rv32i_m/F/src/feq_b1-01.S",
"rv32i_m/F/src/feq_b19-01.S", "rv32i_m/F/src/feq_b19-01.S",
"rv32i_m/F/src/fle_b1-01.S", "rv32i_m/F/src/fle_b1-01.S",
@ -1877,15 +1862,6 @@ string arch64zbs[] = '{
"rv32i_m/F/src/fsgnj_b1-01.S", "rv32i_m/F/src/fsgnj_b1-01.S",
"rv32i_m/F/src/fsgnjn_b1-01.S", "rv32i_m/F/src/fsgnjn_b1-01.S",
"rv32i_m/F/src/fsgnjx_b1-01.S", "rv32i_m/F/src/fsgnjx_b1-01.S",
"rv32i_m/F/src/fsqrt_b1-01.S",
"rv32i_m/F/src/fsqrt_b20-01.S",
"rv32i_m/F/src/fsqrt_b2-01.S",
"rv32i_m/F/src/fsqrt_b3-01.S",
"rv32i_m/F/src/fsqrt_b4-01.S",
"rv32i_m/F/src/fsqrt_b5-01.S",
"rv32i_m/F/src/fsqrt_b7-01.S",
"rv32i_m/F/src/fsqrt_b8-01.S",
"rv32i_m/F/src/fsqrt_b9-01.S",
"rv32i_m/F/src/fsub_b10-01.S", "rv32i_m/F/src/fsub_b10-01.S",
"rv32i_m/F/src/fsub_b1-01.S", "rv32i_m/F/src/fsub_b1-01.S",
"rv32i_m/F/src/fsub_b11-01.S", "rv32i_m/F/src/fsub_b11-01.S",
@ -1900,6 +1876,30 @@ string arch64zbs[] = '{
"rv32i_m/F/src/fsw-align-01.S" "rv32i_m/F/src/fsw-align-01.S"
}; };
string arch32zfh_divsqrt[] = '{
`RISCVARCHTEST,
"rv32i_m/Zfh/src/fdiv_b20-01.S",
"rv32i_m/Zfh/src/fdiv_b1-01.S",
"rv32i_m/Zfh/src/fdiv_b2-01.S",
"rv32i_m/Zfh/src/fdiv_b21-01.S",
"rv32i_m/Zfh/src/fdiv_b3-01.S",
"rv32i_m/Zfh/src/fdiv_b4-01.S",
"rv32i_m/Zfh/src/fdiv_b5-01.S",
"rv32i_m/Zfh/src/fdiv_b6-01.S",
"rv32i_m/Zfh/src/fdiv_b7-01.S",
"rv32i_m/Zfh/src/fdiv_b8-01.S",
"rv32i_m/Zfh/src/fdiv_b9-01.S",
"rv32i_m/Zfh/src/fsqrt_b1-01.S",
"rv32i_m/Zfh/src/fsqrt_b20-01.S",
"rv32i_m/Zfh/src/fsqrt_b2-01.S",
"rv32i_m/Zfh/src/fsqrt_b3-01.S",
"rv32i_m/Zfh/src/fsqrt_b4-01.S",
"rv32i_m/Zfh/src/fsqrt_b5-01.S",
"rv32i_m/Zfh/src/fsqrt_b7-01.S",
"rv32i_m/Zfh/src/fsqrt_b8-01.S",
"rv32i_m/Zfh/src/fsqrt_b9-01.S"
};
string arch32zfh[] = '{ string arch32zfh[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/Zfh/src/fadd_b10-01.S", "rv32i_m/Zfh/src/fadd_b10-01.S",
@ -1932,17 +1932,6 @@ string arch64zbs[] = '{
"rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S",
"rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S",
"rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S",
"rv32i_m/Zfh/src/fdiv_b20-01.S",
"rv32i_m/Zfh/src/fdiv_b1-01.S",
"rv32i_m/Zfh/src/fdiv_b2-01.S",
"rv32i_m/Zfh/src/fdiv_b21-01.S",
"rv32i_m/Zfh/src/fdiv_b3-01.S",
"rv32i_m/Zfh/src/fdiv_b4-01.S",
"rv32i_m/Zfh/src/fdiv_b5-01.S",
"rv32i_m/Zfh/src/fdiv_b6-01.S",
"rv32i_m/Zfh/src/fdiv_b7-01.S",
"rv32i_m/Zfh/src/fdiv_b8-01.S",
"rv32i_m/Zfh/src/fdiv_b9-01.S",
"rv32i_m/Zfh/src/feq_b1-01.S", "rv32i_m/Zfh/src/feq_b1-01.S",
"rv32i_m/Zfh/src/feq_b19-01.S", "rv32i_m/Zfh/src/feq_b19-01.S",
"rv32i_m/Zfh/src/fle_b1-01.S", "rv32i_m/Zfh/src/fle_b1-01.S",
@ -1975,15 +1964,6 @@ string arch64zbs[] = '{
"rv32i_m/Zfh/src/fsgnj_b1-01.S", "rv32i_m/Zfh/src/fsgnj_b1-01.S",
"rv32i_m/Zfh/src/fsgnjn_b1-01.S", "rv32i_m/Zfh/src/fsgnjn_b1-01.S",
"rv32i_m/Zfh/src/fsgnjx_b1-01.S", "rv32i_m/Zfh/src/fsgnjx_b1-01.S",
"rv32i_m/Zfh/src/fsqrt_b1-01.S",
"rv32i_m/Zfh/src/fsqrt_b20-01.S",
"rv32i_m/Zfh/src/fsqrt_b2-01.S",
"rv32i_m/Zfh/src/fsqrt_b3-01.S",
"rv32i_m/Zfh/src/fsqrt_b4-01.S",
"rv32i_m/Zfh/src/fsqrt_b5-01.S",
"rv32i_m/Zfh/src/fsqrt_b7-01.S",
"rv32i_m/Zfh/src/fsqrt_b8-01.S",
"rv32i_m/Zfh/src/fsqrt_b9-01.S",
"rv32i_m/Zfh/src/fsub_b10-01.S", "rv32i_m/Zfh/src/fsub_b10-01.S",
"rv32i_m/Zfh/src/fsub_b1-01.S", "rv32i_m/Zfh/src/fsub_b1-01.S",
"rv32i_m/Zfh/src/fsub_b11-01.S", "rv32i_m/Zfh/src/fsub_b11-01.S",
@ -2086,6 +2066,30 @@ string arch64zbs[] = '{
"rv32i_m/D/src/fnmsub.d_b15-01.S" "rv32i_m/D/src/fnmsub.d_b15-01.S"
}; };
string arch32d_divsqrt[] = '{
`RISCVARCHTEST,
"rv32i_m/D/src/fdiv.d_b1-01.S",
"rv32i_m/D/src/fdiv.d_b20-01.S",
"rv32i_m/D/src/fdiv.d_b2-01.S",
"rv32i_m/D/src/fdiv.d_b21-01.S",
"rv32i_m/D/src/fdiv.d_b3-01.S",
"rv32i_m/D/src/fdiv.d_b4-01.S",
"rv32i_m/D/src/fdiv.d_b5-01.S",
"rv32i_m/D/src/fdiv.d_b6-01.S",
"rv32i_m/D/src/fdiv.d_b7-01.S",
"rv32i_m/D/src/fdiv.d_b8-01.S",
"rv32i_m/D/src/fdiv.d_b9-01.S",
"rv32i_m/D/src/fsqrt.d_b1-01.S",
"rv32i_m/D/src/fsqrt.d_b20-01.S",
"rv32i_m/D/src/fsqrt.d_b2-01.S",
"rv32i_m/D/src/fsqrt.d_b3-01.S",
"rv32i_m/D/src/fsqrt.d_b4-01.S",
"rv32i_m/D/src/fsqrt.d_b5-01.S",
"rv32i_m/D/src/fsqrt.d_b7-01.S",
"rv32i_m/D/src/fsqrt.d_b8-01.S",
"rv32i_m/D/src/fsqrt.d_b9-01.S"
};
string arch32d[] = '{ string arch32d[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/D/src/fadd.d_b10-01.S", "rv32i_m/D/src/fadd.d_b10-01.S",
@ -2132,17 +2136,6 @@ string arch64zbs[] = '{
"rv32i_m/D/src/fcvt.wu.d_b27-01.S", "rv32i_m/D/src/fcvt.wu.d_b27-01.S",
"rv32i_m/D/src/fcvt.wu.d_b28-01.S", "rv32i_m/D/src/fcvt.wu.d_b28-01.S",
"rv32i_m/D/src/fcvt.wu.d_b29-01.S", "rv32i_m/D/src/fcvt.wu.d_b29-01.S",
"rv32i_m/D/src/fdiv.d_b1-01.S",
"rv32i_m/D/src/fdiv.d_b20-01.S",
"rv32i_m/D/src/fdiv.d_b2-01.S",
"rv32i_m/D/src/fdiv.d_b21-01.S",
"rv32i_m/D/src/fdiv.d_b3-01.S",
"rv32i_m/D/src/fdiv.d_b4-01.S",
"rv32i_m/D/src/fdiv.d_b5-01.S",
"rv32i_m/D/src/fdiv.d_b6-01.S",
"rv32i_m/D/src/fdiv.d_b7-01.S",
"rv32i_m/D/src/fdiv.d_b8-01.S",
"rv32i_m/D/src/fdiv.d_b9-01.S",
"rv32i_m/D/src/feq.d_b1-01.S", "rv32i_m/D/src/feq.d_b1-01.S",
"rv32i_m/D/src/feq.d_b19-01.S", "rv32i_m/D/src/feq.d_b19-01.S",
"rv32i_m/D/src/fle.d_b1-01.S", "rv32i_m/D/src/fle.d_b1-01.S",
@ -2211,15 +2204,6 @@ string arch64zbs[] = '{
"rv32i_m/D/src/fsgnj.d_b1-01.S", "rv32i_m/D/src/fsgnj.d_b1-01.S",
"rv32i_m/D/src/fsgnjn.d_b1-01.S", "rv32i_m/D/src/fsgnjn.d_b1-01.S",
"rv32i_m/D/src/fsgnjx.d_b1-01.S", "rv32i_m/D/src/fsgnjx.d_b1-01.S",
"rv32i_m/D/src/fsqrt.d_b1-01.S",
"rv32i_m/D/src/fsqrt.d_b20-01.S",
"rv32i_m/D/src/fsqrt.d_b2-01.S",
"rv32i_m/D/src/fsqrt.d_b3-01.S",
"rv32i_m/D/src/fsqrt.d_b4-01.S",
"rv32i_m/D/src/fsqrt.d_b5-01.S",
"rv32i_m/D/src/fsqrt.d_b7-01.S",
"rv32i_m/D/src/fsqrt.d_b8-01.S",
"rv32i_m/D/src/fsqrt.d_b9-01.S",
"rv32i_m/D/src/fssub.d_b10-01.S", "rv32i_m/D/src/fssub.d_b10-01.S",
"rv32i_m/D/src/fssub.d_b1-01.S", "rv32i_m/D/src/fssub.d_b1-01.S",
"rv32i_m/D/src/fssub.d_b11-01.S", "rv32i_m/D/src/fssub.d_b11-01.S",
@ -2488,7 +2472,12 @@ string arch64zbs[] = '{
}; };
string ahb[] = '{ string ahb64[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv64i_m/F/src/fadd_b11-01.S" "rv64i_m/F/src/fadd_b11-01.S"
}; };
string ahb32[] = '{
`RISCVARCHTEST,
"rv32i_m/F/src/fadd_b11-01.S"
};