mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #608 from davidharrishmc/dev
Nightly regression and lint improvements
This commit is contained in:
Rose Thompson
GitHub
commit
532cdad6f3
@ -1,184 +0,0 @@
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//////////////////////////////////////////
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// config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// include shared configuration
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`include "BranchPredictorType.vh"
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// RV32 or RV64: XLEN = 32 or 64
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localparam XLEN = 32'd64;
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// IEEE 754 compliance
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localparam IEEE754 = 0;
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localparam MISA = (32'h0014112D);
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localparam ZICSR_SUPPORTED = 1;
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localparam ZIFENCEI_SUPPORTED = 1;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam COUNTERS = 12'd32;
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localparam ZFH_SUPPORTED = 1;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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localparam ZICBOP_SUPPORTED = 1;
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localparam ZICCLSM_SUPPORTED = 1;
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localparam ZICOND_SUPPORTED = 1;
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localparam SVPBMT_SUPPORTED = 1;
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localparam SVNAPOT_SUPPORTED = 1;
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localparam SVINVAL_SUPPORTED = 1;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 1;
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localparam DCACHE_SUPPORTED = 1;
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localparam ICACHE_SUPPORTED = 1;
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localparam VIRTMEM_SUPPORTED = 1;
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localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
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localparam BIGENDIAN_SUPPORTED = 1;
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// TLB configuration. Entries should be a power of 2
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localparam ITLB_ENTRIES = 32'd32;
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localparam DTLB_ENTRIES = 32'd32;
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
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localparam DCACHE_NUMWAYS = 32'd4;
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localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
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localparam DCACHE_LINELENINBITS = 32'd512;
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localparam ICACHE_NUMWAYS = 32'd4;
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localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
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localparam ICACHE_LINELENINBITS = 32'd512;
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localparam CACHE_SRAMLEN = 32'd128;
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// Integer Divider Configuration
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// IDIV_BITSPERCYCLE must be 1, 2, or 4
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localparam IDIV_BITSPERCYCLE = 32'd4;
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localparam IDIV_ON_FPU = 1;
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// Legal number of PMP entries are 0, 16, or 64
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localparam PMP_ENTRIES = 32'd16;
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// Address space
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localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000;
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// WFI Timeout Wait
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localparam WFI_TIMEOUT_BIT = 32'd16;
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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localparam DTIM_SUPPORTED = 1'b0;
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localparam logic [63:0] DTIM_BASE = 64'h80000000;
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localparam logic [63:0] DTIM_RANGE = 64'h00001FFF;
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localparam IROM_SUPPORTED = 1'b0;
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localparam logic [63:0] IROM_BASE = 64'h80000000;
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localparam logic [63:0] IROM_RANGE = 64'h00001FFF;
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localparam BOOTROM_SUPPORTED = 1'b1;
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localparam logic [63:0] BOOTROM_BASE = 64'h00001000 ;
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localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
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localparam BOOTROM_PRELOAD = 1'b1;
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localparam UNCORE_RAM_SUPPORTED = 1'b1;
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localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h0FFFFFFF;
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localparam UNCORE_RAM_PRELOAD = 1'b1;
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localparam EXT_MEM_SUPPORTED = 1'b0;
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localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
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localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
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localparam CLINT_SUPPORTED = 1'b1;
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localparam logic [63:0] CLINT_BASE = 64'h02000000;
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localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
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localparam GPIO_SUPPORTED = 1'b1;
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localparam logic [63:0] GPIO_BASE = 64'h10060000;
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localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
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localparam UART_SUPPORTED = 1'b1;
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localparam logic [63:0] UART_BASE = 64'h10000000;
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localparam logic [63:0] UART_RANGE = 64'h00000007;
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localparam PLIC_SUPPORTED = 1'b1;
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localparam logic [63:0] PLIC_BASE = 64'h0C000000;
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localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
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localparam SDC_SUPPORTED = 1'b0;
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localparam logic [63:0] SDC_BASE = 64'h00013000;
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localparam logic [63:0] SDC_RANGE = 64'h0000007F;
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localparam SPI_SUPPORTED = 1'b1;
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localparam logic [63:0] SPI_BASE = 64'h10040000;
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localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
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// Bus Interface width
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localparam AHBW = 32'd64;
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// AHB
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localparam RAM_LATENCY = 32'b0;
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localparam BURST_EN = 1;
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// Test modes
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// Tie GPIO outputs back to inputs
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localparam GPIO_LOOPBACK_TEST = 0;
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localparam SPI_LOOPBACK_TEST = 0;
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// Hardware configuration
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localparam UART_PRESCALE = 32'd0;
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// Interrupt configuration
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localparam PLIC_NUM_SRC = 32'd53;
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localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
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localparam PLIC_UART_ID = 32'd10;
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localparam PLIC_GPIO_ID = 32'd3;
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localparam PLIC_SPI_ID = 32'd6;
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localparam PLIC_SDC_ID = 32'd20;
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localparam BPRED_SUPPORTED = 1;
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localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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localparam BPRED_SIZE = 32'd10;
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localparam BPRED_NUM_LHR = 32'd6;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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localparam INSTR_CLASS_PRED = 1;
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localparam SVADU_SUPPORTED = 1;
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localparam ZMMUL_SUPPORTED = 0;
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// FPU division architecture
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localparam RADIX = 32'h4;
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localparam DIVCOPIES = 32'h4;
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// bit manipulation
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localparam ZBA_SUPPORTED = 1;
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localparam ZBB_SUPPORTED = 1;
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localparam ZBC_SUPPORTED = 1;
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localparam ZBS_SUPPORTED = 1;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 1;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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`include "config-shared.vh"
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@ -41,8 +41,8 @@ RESET_VECTOR 64'h1000
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UNCORE_RAM_RANGE 64'h0FFFFFFF
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UNCORE_RAM_PRELOAD 1
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GPIO_LOOPBACK_TEST 0
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SPI_LOOPBACK_TEST 0
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UART_PRESCALE 0
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SPI_LOOPBACK_TEST 0
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UART_PRESCALE 32'd0
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PLIC_NUM_SRC 32'd53
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# fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM)
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@ -119,26 +119,33 @@ MISA (32'h00000104 | 1 << 18 | 1 << 20)
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deriv div_2_1_rv32gc rv32gc
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RADIX 32'd2
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DIVCOPIES 32'd1
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IDIV_ON_FPU 0
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deriv div_2_2_rv32gc rv32gc
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RADIX 32'd2
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DIVCOPIES 32'd2
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IDIV_ON_FPU 0
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deriv div_2_4_rv32gc rv32gc
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RADIX 32'd2
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DIVCOPIES 32'd4
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IDIV_ON_FPU 0
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deriv div_4_1_rv32gc rv32gc
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RADIX 32'd4
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DIVCOPIES 32'd1
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IDIV_ON_FPU 0
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deriv div_4_2_rv32gc rv32gc
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RADIX 32'd4
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IDIV_ON_FPU 0
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DIVCOPIES 32'd2
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IDIV_ON_FPU 0
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deriv div_4_4_rv32gc rv32gc
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RADIX 32'd4
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DIVCOPIES 32'd4
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IDIV_ON_FPU 0
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deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc
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IDIV_ON_FPU 1
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@ -161,26 +168,32 @@ IDIV_ON_FPU 1
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deriv div_2_1_rv64gc rv64gc
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RADIX 32'd2
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DIVCOPIES 32'd1
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IDIV_ON_FPU 0
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deriv div_2_2_rv64gc rv64gc
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RADIX 32'd2
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DIVCOPIES 32'd2
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IDIV_ON_FPU 0
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deriv div_2_4_rv64gc rv64gc
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RADIX 32'd2
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DIVCOPIES 32'd4
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IDIV_ON_FPU 0
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deriv div_4_1_rv64gc rv64gc
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RADIX 32'd4
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DIVCOPIES 32'd1
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IDIV_ON_FPU 0
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deriv div_4_2_rv64gc rv64gc
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RADIX 32'd4
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DIVCOPIES 32'd2
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IDIV_ON_FPU 0
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deriv div_4_4_rv64gc rv64gc
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RADIX 32'd4
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DIVCOPIES 32'd4
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IDIV_ON_FPU 0
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deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc
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IDIV_ON_FPU 1
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@ -366,6 +379,7 @@ INSTR_CLASS_PRED 0
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deriv noicache_rv32gc rv32gc
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ICACHE_SUPPORTED 0
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VIRTMEM_SUPPORTED 0
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deriv nodcache_rv32gc rv32gc
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DCACHE_SUPPORTED 0
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@ -374,6 +388,31 @@ deriv nocache_rv32gc rv32gc
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ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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deriv noicache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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VIRTMEM_SUPPORTED 0
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SVPBMT_SUPPORTED 0
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SVNAPOT_SUPPORTED 0
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deriv nodcache_rv64gc rv64gc
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DCACHE_SUPPORTED 0
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VIRTMEM_SUPPORTED 0
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ZICBOM_SUPPORTED 0
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ZICBOZ_SUPPORTED 0
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SVPBMT_SUPPORTED 0
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SVNAPOT_SUPPORTED 0
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MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
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deriv nocache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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VIRTMEM_SUPPORTED 0
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ZICBOM_SUPPORTED 0
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ZICBOZ_SUPPORTED 0
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SVPBMT_SUPPORTED 0
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SVNAPOT_SUPPORTED 0
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MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
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deriv way_1_4096_512_rv32gc rv32gc
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DCACHE_NUMWAYS 32'd1
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DCACHE_WAYSIZEINBYTES 32'd4096
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@ -402,20 +441,6 @@ deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_LINELENINBITS 32'd256
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ICACHE_LINELENINBITS 32'd256
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deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_LINELENINBITS 32'd1024
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ICACHE_LINELENINBITS 32'd1024
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deriv noicache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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deriv nodcache_rv64gc rv64gc
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DCACHE_SUPPORTED 0
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deriv nocache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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deriv way_1_4096_512_rv64gc rv64gc
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DCACHE_NUMWAYS 32'd1
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DCACHE_WAYSIZEINBYTES 32'd4096
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@ -103,7 +103,7 @@ localparam RESBITS = DIVMINb + LOGR; // number of bits in a result: r intege
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localparam FPDUR = (RESBITS-1)/RK + 1 ; // ceiling((r+b)/rk)
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localparam DIVb = FPDUR*RK - LOGR; // divsqrt fractional bits, so total number of bits is a multiple of rk after r integer bits
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localparam DURLEN = $clog2(FPDUR); // enough bits to count the duration
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localparam DIVBLEN = $clog2(DIVb); // enough bits to count number of fractional bits
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localparam DIVBLEN = $clog2(DIVb+1); // enough bits to count number of fractional bits + 1 integer bit
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// largest length in IEU/FPU
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localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF)); // max(XLEN, NF)
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@ -6,26 +6,43 @@ export PATH=$PATH:/usr/local/bin/
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verilator=`which verilator`
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basepath=$(dirname $0)/..
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RED='\033[0;31m'
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GREEN='\033[0;32m'
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NC='\033[0m' # No Color
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fails=0
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if [ "$1" == "-nightly" ]; then
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
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derivconfigs=`ls $WALLY/config/deriv`
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for entry in $derivconfigs
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do
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configs[${#configs[@]}]=$entry
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if [[ $entry != *"syn_sram"* ]]; then # ignore syn_sram* configs that contain undefined module
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configs[${#configs[@]}]=$entry
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fi
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done
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else
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i div_2_1i_rv64gc ) # add fdqh_rv64gc when working
|
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fi
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|
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for config in ${configs[@]}; do
|
||||
echo "$config linting..."
|
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# echo "$config linting..."
|
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if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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||||
echo "Exiting after $config lint due to errors or warnings"
|
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exit 1
|
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if [ "$1" == "-nightly" ]; then
|
||||
echo -e "${RED}$config failed lint${NC}"
|
||||
fails=$((fails+1))
|
||||
else
|
||||
echo -e "${RED}$config fails with lint errors or warnings"
|
||||
exit 1
|
||||
fi
|
||||
else
|
||||
echo -e "${GREEN}$config passed lint${NC}"
|
||||
fi
|
||||
done
|
||||
echo "All lints run with no errors or warnings"
|
||||
if [ $fails > 0 ]; then
|
||||
echo -e "${RED}Linting failed for $fails of ${#configs[@]} configurations"
|
||||
exit 1
|
||||
fi
|
||||
echo -e "${GREEN}All ${#configs[@]} lints run with no errors or warnings"
|
||||
|
||||
# --lint-only just runs lint rather than trying to compile and simulate
|
||||
# -I points to the include directory where files such as `include config.vh are found
|
||||
|
||||
@ -85,7 +85,7 @@ for test in tests64i:
|
||||
configs.append(tc)
|
||||
|
||||
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
|
||||
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zfad",
|
||||
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zbc", "arch32zfad",
|
||||
#tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"]
|
||||
for test in tests32gc:
|
||||
tc = TestCase(
|
||||
@ -124,16 +124,7 @@ for test in tests32e:
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
ahbTests = [("0", "0"), ("0", "1"), ("1", "0"), ("1", "1"), ("2", "0"), ("2", "1")]
|
||||
for test in ahbTests:
|
||||
tc = TestCase(
|
||||
name="ram_latency_" + test[0] + "_burst_en_" + test[1],
|
||||
variant="ahb",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad",
|
||||
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad",
|
||||
"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working
|
||||
#tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||
# "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"]
|
||||
@ -141,7 +132,7 @@ if (coverage): # delete all but 64gc tests when running coverage
|
||||
configs = []
|
||||
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||
"arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv",
|
||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz"
|
||||
"arch64zba", "arch64zbb", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz"
|
||||
if (fp):
|
||||
tests64gc.append("arch64f")
|
||||
tests64gc.append("arch64d")
|
||||
@ -176,7 +167,6 @@ if (nightly):
|
||||
["way_8_4096_512_rv32gc", ["arch32i"]],
|
||||
["way_4_2048_512_rv32gc", ["arch32i"]],
|
||||
["way_4_4096_256_rv32gc", ["arch32i"]],
|
||||
["way_4_4096_1024_rv32gc", ["arch32i"]],
|
||||
["way_1_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_2_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_8_4096_512_rv64gc", ["arch64i"]],
|
||||
@ -184,12 +174,22 @@ if (nightly):
|
||||
["way_4_4096_256_rv64gc", ["arch64i"]],
|
||||
["way_4_4096_1024_rv64gc", ["arch64i"]],
|
||||
|
||||
["ram_0_0_rv64gc", ["ahb"]],
|
||||
["ram_1_0_rv64gc", ["ahb"]],
|
||||
["ram_1_1_rv64gc", ["ahb"]],
|
||||
["ram_2_0_rv64gc", ["ahb"]],
|
||||
["ram_2_1_rv64gc", ["ahb"]],
|
||||
["ram_0_0_rv64gc", ["ahb64"]],
|
||||
["ram_1_0_rv64gc", ["ahb64"]],
|
||||
["ram_1_1_rv64gc", ["ahb64"]],
|
||||
["ram_2_0_rv64gc", ["ahb64"]],
|
||||
["ram_2_1_rv64gc", ["ahb64"]],
|
||||
|
||||
["noicache_rv32gc", ["ahb32"]],
|
||||
# cacheless designs will not work until DTIM supports FLEN > XLEN
|
||||
# ["nodcache_rv32gc", ["ahb32"]],
|
||||
# ["nocache_rv32gc", ["ahb32"]],
|
||||
["noicache_rv64gc", ["ahb64"]],
|
||||
["nodcache_rv64gc", ["ahb64"]],
|
||||
["nocache_rv64gc", ["ahb64"]],
|
||||
|
||||
### add misaligned tests
|
||||
|
||||
["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
@ -215,6 +215,19 @@ if (nightly):
|
||||
["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
|
||||
# enable floating-point tests when lint is fixed
|
||||
# ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
|
||||
# ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
|
||||
# ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
|
||||
# ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
|
||||
# ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
|
||||
# ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
|
||||
# ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
|
||||
# ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
|
||||
# ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
|
||||
# ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
|
||||
|
||||
|
||||
]
|
||||
for test in derivconfigtests:
|
||||
config = test[0];
|
||||
|
||||
@ -21,14 +21,7 @@
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if {$2 eq "ahb"} {
|
||||
if [file exists wkdir/work_${1}_${2}_${3}_${4}] {
|
||||
vdel -lib wkdir/work_${1}_${2}_${3}_${4} -all
|
||||
}
|
||||
vlib wkdir/work_${1}_${2}_${3}_${4}
|
||||
|
||||
|
||||
} elseif {$2 eq "configOptions"} {
|
||||
if {$2 eq "configOptions"} {
|
||||
if [file exists wkdir/work_${1}_${3}_${4}] {
|
||||
vdel -lib wkdir/work_${1}_${3}_${4} -all
|
||||
}
|
||||
@ -86,22 +79,6 @@ if {$2 eq "buildroot"} {
|
||||
run -all
|
||||
run -all
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
|
||||
} elseif {$2 eq "ahb"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
|
||||
vsim -lib wkdir/work_${1}_${2}_${3}_${4} testbenchopt -fatal 7
|
||||
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
|
||||
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
|
||||
#vsim -coverage -lib work_$2 workopt_$2
|
||||
|
||||
# power add generates the logging necessary for said generation.
|
||||
# power add -r /dut/core/*
|
||||
run -all
|
||||
# power off -r /dut/core/*
|
||||
|
||||
} elseif {$2 eq "configOptions"} {
|
||||
# set arguments " "
|
||||
# for {set i 5} {$i <= $argc} {incr i} {
|
||||
|
||||
@ -77,12 +77,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
run 20 ms
|
||||
|
||||
} else {
|
||||
if {$2 eq "ahb"} {
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
} else {
|
||||
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
|
||||
}
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
|
||||
|
||||
vsim workopt +nowarn3829 -fatal 7
|
||||
|
||||
@ -278,9 +278,14 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||
end else assign FliResE = '0;
|
||||
|
||||
// fmv.*.x: NaN Box SrcA to extend integer to requested FP size
|
||||
if(P.FPSIZES == 1) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
|
||||
if(P.FPSIZES == 1)
|
||||
if (P.FLEN >= P.XLEN) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
|
||||
else assign PreIntSrcE = ForwardedSrcAE[P.FLEN-1:0];
|
||||
else if(P.FPSIZES == 2)
|
||||
mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE);
|
||||
if (P.FLEN >= P.XLEN)
|
||||
mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE);
|
||||
else
|
||||
mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, ForwardedSrcAE[P.FLEN-1:0], FmtE, PreIntSrcE);
|
||||
else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
|
||||
localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN
|
||||
mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]},
|
||||
|
||||
@ -406,7 +406,11 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
||||
end
|
||||
|
||||
if (P.F_SUPPORTED)
|
||||
mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
|
||||
if (P.FLEN >= P.XLEN)
|
||||
mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
|
||||
else
|
||||
mux2 #(P.LLEN) datamux(IMAWriteDataM, {{{P.XLEN-P.FLEN}{1'b0}}, FWriteDataM}, FpLoadStoreM, IMAFWriteDataM);
|
||||
|
||||
else assign IMAFWriteDataM = IMAWriteDataM;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@ -21,53 +21,52 @@
|
||||
|
||||
module riscvassertions import cvw::*; #(parameter cvw_t P);
|
||||
initial begin
|
||||
assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
|
||||
assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
|
||||
assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
|
||||
assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
|
||||
assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||
assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported");
|
||||
assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
|
||||
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support");
|
||||
assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");
|
||||
assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)");
|
||||
assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
|
||||
assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||
assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported");
|
||||
assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $fatal(1, "Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
|
||||
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2");
|
||||
assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF");
|
||||
assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
|
||||
assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
|
||||
assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
|
||||
assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported");
|
||||
assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||
assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
|
||||
assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
|
||||
assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
||||
assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally.");
|
||||
assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
|
||||
assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
|
||||
assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
|
||||
assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
|
||||
assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
|
||||
assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM requires DCACHE_SUPPORTED");
|
||||
assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ requires DCACHE_SUPPORTED");
|
||||
assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP requires DCACHE_SUPPORTED");
|
||||
assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVPBMT requires VIRTMEM_SUPPORTED and RV64");
|
||||
assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
|
||||
assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $error("ZCB requires M and ZBB (and also ZBA for RV64)");
|
||||
assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $error("C and ZCA/ZCD/ZCF cannot simultaneously be supported");
|
||||
assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $error("ZCF or ZCD requires ZCA");
|
||||
assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $error("ZCF requires F");
|
||||
assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $error("ZCD requires D");
|
||||
assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||
assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache");
|
||||
assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache");
|
||||
assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED.");
|
||||
assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16");
|
||||
assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
||||
assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally.");
|
||||
assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED");
|
||||
assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED");
|
||||
assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $fatal(1, "At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
|
||||
assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
|
||||
assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
|
||||
assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED");
|
||||
assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED");
|
||||
assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
|
||||
assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
|
||||
assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $fatal(1, "ZCB requires M and ZBB (and also ZBA for RV64)");
|
||||
assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $fatal(1, "C and ZCA/ZCD/ZCF cannot simultaneously be supported");
|
||||
assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA");
|
||||
assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
|
||||
assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -121,7 +121,7 @@ module testbench;
|
||||
"wally64periph": tests = wally64periph;
|
||||
"coremark": tests = coremark;
|
||||
"fpga": tests = fpga;
|
||||
"ahb" : tests = ahb;
|
||||
"ahb64" : tests = ahb64;
|
||||
"coverage64gc" : tests = coverage64gc;
|
||||
"arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba;
|
||||
"arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb;
|
||||
@ -162,6 +162,7 @@ module testbench;
|
||||
"wally32i": tests = wally32i;
|
||||
"wally32priv": tests = wally32priv;
|
||||
"wally32periph": tests = wally32periph;
|
||||
"ahb32" : tests = ahb32;
|
||||
"embench": tests = embench;
|
||||
"coremark": tests = coremark;
|
||||
"arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba;
|
||||
|
||||
@ -2472,7 +2472,12 @@ string arch64zbs[] = '{
|
||||
};
|
||||
|
||||
|
||||
string ahb[] = '{
|
||||
string ahb64[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/F/src/fadd_b11-01.S"
|
||||
};
|
||||
|
||||
string ahb32[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/F/src/fadd_b11-01.S"
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user