From 0abfe5cb5544f542531bbf15ed22d07a292655a9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 11:39:59 -0800 Subject: [PATCH 01/10] Fixed some lint errors in derived configs --- config/derivlist.txt | 156 ++++++++++++++++---------------- config/shared/parameter-defs.vh | 1 + sim/lint-wally | 18 +++- src/cache/cacheLRU.sv | 2 +- src/cvw.sv | 1 + src/fpu/fpu.sv | 14 +-- src/uncore/ram_ahb.sv | 2 +- 7 files changed, 105 insertions(+), 89 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index bcffb1ec5..53cb3b8f1 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -59,10 +59,10 @@ BPRED_SIZE 32'd12 # The syn configurations are trimmed down for faster synthesis. deriv syn_rv32e rv32e -DTIM_RANGE 32'h1FF -IROM_RANGE 32'h1FF -BOOTROM_RANGE 32'h1FF -UNCORE_RAM_RANGE 32'h1FF +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF +BOOTROM_RANGE 64'h1FF +UNCORE_RAM_RANGE 64'h1FF WAYSIZEINBYTES 32'd512 NUMWAYS 32'd1 BPRED_SIZE 32'd5 @@ -77,8 +77,8 @@ deriv syn_rv64gc rv64gc syn_rv32e # The syn_sram configurations use SRAM macros deriv syn_sram_rv32e rv32e -DTIM_RANGE 32'h1FF -IROM_RANGE 32'h1FF +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF USE_SRAM 1 # The other syn configurations have the same trimming @@ -90,9 +90,9 @@ deriv syn_sram_rv64gc rv64gc syn_sram_rv32e # The following syn configurations gradually turn off features deriv syn_pmp0_rv64gc rv64gc syn_rv64gc -PMP_ENTRIES 0 +PMP_ENTRIES 32'd0 deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc -PMP_ENTRIES 0 +PMP_ENTRIES 32'd0 deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc ZICSR_SUPPORTED 0 @@ -203,95 +203,95 @@ IDIV_ON_FPU 1 # RAM latency and Burst mode for bus stress testing deriv ram_0_0_rv64gc rv64gc -RAM_LATENCY 0 +RAM_LATENCY 32'd0 BURST_EN 0 deriv ram_1_0_rv64gc rv64gc -RAM_LATENCY 1 +RAM_LATENCY 32'd1 BURST_EN 0 deriv ram_2_0_rv64gc rv64gc -RAM_LATENCY 2 +RAM_LATENCY 32'd2 BURST_EN 0 deriv ram_1_1_rv64gc rv64gc -RAM_LATENCY 1 +RAM_LATENCY 32'd1 BURST_EN 1 deriv ram_2_1_rv64gc rv64gc -RAM_LATENCY 2 +RAM_LATENCY 32'd2 BURST_EN 1 # Branch predictor simulations deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc -BPRED_SIZE 6 +BPRED_SIZE 32'd6 deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc -BPRED_SIZE 8 +BPRED_SIZE 32'd8 deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc -BPRED_SIZE 10 +BPRED_SIZE 32'd10 deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc -BPRED_SIZE 12 +BPRED_SIZE 32'd12 deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc -BPRED_SIZE 14 +BPRED_SIZE 32'd14 deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc -BPRED_SIZE 16 +BPRED_SIZE 32'd16 deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc -RAS_SIZE 2 +RAS_SIZE 32'd2 deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc -RAS_SIZE 3 +RAS_SIZE 32'd3 deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc -RAS_SIZE 4 +RAS_SIZE 32'd4 deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc -RAS_SIZE 6 +RAS_SIZE 32'd6 deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc -RAS_SIZE 10 +RAS_SIZE 32'd10 deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc -RAS_SIZE 16 +RAS_SIZE 32'd16 deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc -BTB_SIZE 6 +BTB_SIZE 32'd6 deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc -BTB_SIZE 8 +BTB_SIZE 32'd8 deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc -BTB_SIZE 12 +BTB_SIZE 32'd12 deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc -BTB_SIZE 14 +BTB_SIZE 32'd14 deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc -BTB_SIZE 16 +BTB_SIZE 32'd16 deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc INSTR_CLASS_PRED 0 @@ -375,36 +375,36 @@ ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 deriv way_1_4096_512_rv32gc rv32gc -DCACHE_NUMWAYS 1 -DCACHE_WAYSIZEINBYTES 4096 -DCACHE_LINELENINBITS 512 -ICACHE_NUMWAYS 1 -ICACHE_WAYSIZEINBYTES 4096 -ICACHE_LINELENINBITS 512 +DCACHE_NUMWAYS 32'd1 +DCACHE_WAYSIZEINBYTES 32'd4096 +DCACHE_LINELENINBITS 32'd512 +ICACHE_NUMWAYS 32'd1 +ICACHE_WAYSIZEINBYTES 32'd4096 +ICACHE_LINELENINBITS 32'd512 deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 1 -ICACHE_NUMWAYS 1 +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 4 -ICACHE_NUMWAYS 4 +DCACHE_NUMWAYS 32'd4 +ICACHE_NUMWAYS 32'd4 deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 8 -ICACHE_NUMWAYS 8 +DCACHE_NUMWAYS 32'd8 +ICACHE_NUMWAYS 32'd8 deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_WAYSIZEINBYTES 2048 -ICACHE_WAYSIZEINBYTES 2048 +DCACHE_WAYSIZEINBYTES 32'd2048 +ICACHE_WAYSIZEINBYTES 32'd2048 deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_LINELENINBITS 256 -ICACHE_LINELENINBITS 256 +DCACHE_LINELENINBITS 32'd256 +ICACHE_LINELENINBITS 32'd256 deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_LINELENINBITS 1024 -ICACHE_LINELENINBITS 1024 +DCACHE_LINELENINBITS 32'd1024 +ICACHE_LINELENINBITS 32'd1024 deriv noicache_rv64gc rv64gc ICACHE_SUPPORTED 0 @@ -417,50 +417,50 @@ ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 deriv way_1_4096_512_rv64gc rv64gc -DCACHE_NUMWAYS 1 -DCACHE_WAYSIZEINBYTES 4096 -DCACHE_LINELENINBITS 512 -ICACHE_NUMWAYS 1 -ICACHE_WAYSIZEINBYTES 4096 -ICACHE_LINELENINBITS 512 +DCACHE_NUMWAYS 32'd1 +DCACHE_WAYSIZEINBYTES 32'd4096 +DCACHE_LINELENINBITS 32'd512 +ICACHE_NUMWAYS 32'd1 +ICACHE_WAYSIZEINBYTES 32'd4096 +ICACHE_LINELENINBITS 32'd512 deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc -DCACHE_NUMWAYS 1 -ICACHE_NUMWAYS 1 +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc -DCACHE_NUMWAYS 4 -ICACHE_NUMWAYS 4 +DCACHE_NUMWAYS 32'd4 +ICACHE_NUMWAYS 32'd4 deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_WAYSIZEINBYTES 2048 -ICACHE_WAYSIZEINBYTES 2048 +DCACHE_WAYSIZEINBYTES 32'd2048 +ICACHE_WAYSIZEINBYTES 32'd2048 deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_LINELENINBITS 256 -ICACHE_LINELENINBITS 256 +DCACHE_LINELENINBITS 32'd256 +ICACHE_LINELENINBITS 32'd256 deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_LINELENINBITS 1024 -ICACHE_LINELENINBITS 1024 +DCACHE_LINELENINBITS 32'd1024 +ICACHE_LINELENINBITS 32'd1024 # TLB Size variants deriv tlb2_rv32gc rv32gc -ITLB_ENTRIES 2 -DTLB_ENTRIES 2 +ITLB_ENTRIES 32'd2 +DTLB_ENTRIES 32'd2 deriv tlb16_rv32gc rv32gc -ITLB_ENTRIES 16 -DTLB_ENTRIES 16 +ITLB_ENTRIES 32'd16 +DTLB_ENTRIES 32'd16 deriv tlb2_rv64gc rv64gc -ITLB_ENTRIES 2 -DTLB_ENTRIES 2 +ITLB_ENTRIES 32'd2 +DTLB_ENTRIES 32'd2 deriv tlb16_rv64gc rv64gc -ITLB_ENTRIES 16 -DTLB_ENTRIES 16 +ITLB_ENTRIES 32'd16 +DTLB_ENTRIES 32'd16 # Feature variants diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index bf4c11198..464e3c0f9 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -102,6 +102,7 @@ localparam cvw_t P = '{ BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, RAS_SIZE : RAS_SIZE, + INSTR_CLASS_PRED : INSTR_CLASS_PRED, RADIX : RADIX, DIVCOPIES : DIVCOPIES, ZBA_SUPPORTED : ZBA_SUPPORTED, diff --git a/sim/lint-wally b/sim/lint-wally index 3125e79ea..3d28a62ec 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -1,14 +1,26 @@ #!/bin/bash # check for warnings in Verilog code # The verilator lint tool is faster and better than Questa so it is best to run this first. + export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do -#for config in rv64gc; do + +if [ "$1" == "-nightly" ]; then + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc + derivconfigs=`ls $WALLY/config/deriv` + for entry in $derivconfigs + do + configs[${#configs[@]}]=$entry + done +else + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc) +fi + +for config in ${configs[@]}; do echo "$config linting..." - if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 70f129d4b..870633405 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -143,7 +143,7 @@ module cacheLRU // This is a two port memory. // Every cycle must read from CacheSetData and each load/store must write the new LRU. always_ff @(posedge clk) begin - if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; + if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; if(CacheEn) begin if(ClearValid & ~FlushStage) LRUMemory[PAdr] <= '0; diff --git a/src/cvw.sv b/src/cvw.sv index c9d737d8f..75f83f68b 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -162,6 +162,7 @@ typedef struct packed { int BPRED_SIZE; int BTB_SIZE; int RAS_SIZE; + logic INSTR_CLASS_PRED; // is class predictor enabled // FPU division architecture int RADIX; diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 90ec10dee..85021d269 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -270,9 +270,11 @@ module fpu import cvw::*; #(parameter cvw_t P) ( // floating-point load immediate: fli if (P.ZFA_SUPPORTED) begin logic [4:0] Rs1E; + logic [1:0] Fmt2E; // Two-bit format field from instruction flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E); - fli #(P) fli(.Rs1(Rs1E), .Fmt(FmtE), .Imm(FliResE)); + flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E); + fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE)); end else assign FliResE = '0; // fmv.*.x: NaN Box SrcA to extend integer to requested FP size @@ -287,7 +289,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( FmtE, PreIntSrcE); // NaN boxing zeroes end // fmvp.*.x: Select pair of registers - if (P.ZFA_SUPPORTED & (P.XLEN==32 & P.D_SUPPORTED) | (P.XLEN==64 & P.Q_SUPPORTED)) + if (P.ZFA_SUPPORTED & (P.FLEN == 2*P.XLEN)) assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x else assign IntSrcE = PreIntSrcE; @@ -311,11 +313,11 @@ module fpu import cvw::*; #(parameter cvw_t P) ( end // sign extend to XLEN if necessary - if (P.FLEN>P.XLEN) - if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* - else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; + if (P.FLEN >= 2*P.XLEN) + if (P.ZFA_SUPPORTED & P.FLEN == 2*P.XLEN) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* + else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; else - assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; + assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE}; mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE); // E/M pipe registers diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index e14728513..98bdfcb09 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -99,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, endcase end - assign CycleFlag = Cycle == P.RAM_LATENCY; + assign CycleFlag = Cycle == P.RAM_LATENCY[7:0]; assign CntEn = NextState == DELAY; assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY; From 2af9282bbc598a55ffa320b274bd6292591cec6b Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 13:18:00 -0800 Subject: [PATCH 02/10] Starting to add nightly regression capability using derived configs --- config/derivlist.txt | 4 +++ sim/regression-wally | 65 +++++++++++++++++++++++++++++++++++--------- sim/wally-batch.do | 10 +++---- 3 files changed, 61 insertions(+), 18 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 53cb3b8f1..de10f7d52 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -432,6 +432,10 @@ deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc DCACHE_NUMWAYS 32'd4 ICACHE_NUMWAYS 32'd4 +deriv way_8_4096_512_rv64gc rv32gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 32'd8 +ICACHE_NUMWAYS 32'd8 + deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc DCACHE_WAYSIZEINBYTES 32'd2048 ICACHE_WAYSIZEINBYTES 32'd2048 diff --git a/sim/regression-wally b/sim/regression-wally index ea453d2c9..b1a50d1ab 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -29,6 +29,7 @@ os.chdir(regressionDir) coverage = '-coverage' in sys.argv fp = '-fp' in sys.argv +nightly = '-nightly' in sys.argv TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # name: the name of this test configuration (used in printing human-readable @@ -40,14 +41,19 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # be any pattern grep accepts, see `man 1 grep` for more info). # edit this list to add more test cases -configs = [ - TestCase( - name="lints", - variant="all", - cmd="./lint-wally | tee {}", - grepstr="All lints run with no errors or warnings" - ) -] +if (nightly): + nightMode = "-nightly"; +else: + nightMode = ""; + configs = [ + TestCase( + name="lints", + variant="all", + cmd="./lint-wally " + nightMode + " | tee {}", + grepstr="All lints run with no errors or warnings" + ) + ] + def getBuildrootTC(boot): INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. @@ -78,7 +84,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "arch32zfad", "wally32a", "wally32priv", "wally32periph"] #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( @@ -126,15 +132,15 @@ for test in ahbTests: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", +tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad", "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", # "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] if (coverage): # delete all but 64gc tests when running coverage configs = [] - tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", + tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zicboz", "arch64zcb", + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad"] # add when working: "arch64zcb", "arch64zicboz" if (fp): tests64gc.append("arch64f") tests64gc.append("arch64d") @@ -150,7 +156,40 @@ for test in tests64gc: cmd="vsim > {} -c < {} -c < {} -c <= 3} { # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32imc rv32imc if {$2 eq "buildroot"} { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation if { $coverage } { echo "wally-batch buildroot coverage" @@ -74,7 +74,7 @@ if {$2 eq "buildroot"} { run -all exec ./slack-notifier/slack-notifier.py } elseif {$2 eq "buildroot-no-trace"} { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 @@ -88,7 +88,7 @@ if {$2 eq "buildroot"} { exec ./slack-notifier/slack-notifier.py } elseif {$2 eq "ahb"} { - vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 + vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt @@ -112,7 +112,7 @@ if {$2 eq "buildroot"} { # **** fix this so we can pass any number of +defines. # only allows 3 right now - vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7 + vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt @@ -126,7 +126,7 @@ if {$2 eq "buildroot"} { # power off -r /dut/core/* } else { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals if {$coverage} { From d3c886abaf22678d90dfeb16995dc20ff7e705a0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 14:07:41 -0800 Subject: [PATCH 03/10] regression-wally initial -nightly support --- sim/regression-wally | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sim/regression-wally b/sim/regression-wally index b1a50d1ab..7b0175841 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -43,6 +43,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # edit this list to add more test cases if (nightly): nightMode = "-nightly"; + configs = [] else: nightMode = ""; configs = [ @@ -84,7 +85,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "arch32zfad", "wally32a", "wally32priv", "wally32periph"] +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zfad", #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( From 111f5926134a17fc5f248da2a9d1ef335687cdfb Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 14:52:15 -0800 Subject: [PATCH 04/10] factor divsqrt out of floating-point test cases to run on more derived configs --- config/derivlist.txt | 2 +- sim/regression-wally | 18 +++- testbench/testbench.sv | 8 ++ testbench/tests.vh | 238 +++++++++++++++++++---------------------- 4 files changed, 133 insertions(+), 133 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index de10f7d52..581922b9c 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -432,7 +432,7 @@ deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc DCACHE_NUMWAYS 32'd4 ICACHE_NUMWAYS 32'd4 -deriv way_8_4096_512_rv64gc rv32gc way_1_4096_512_rv64gc +deriv way_8_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc DCACHE_NUMWAYS 32'd8 ICACHE_NUMWAYS 32'd8 diff --git a/sim/regression-wally b/sim/regression-wally index 7b0175841..ef495df50 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -133,20 +133,26 @@ for test in ahbTests: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad", - "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] +tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad", + "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", # "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] if (coverage): # delete all but 64gc tests when running coverage configs = [] tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad"] # add when working: "arch64zcb", "arch64zicboz" + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz" if (fp): tests64gc.append("arch64f") tests64gc.append("arch64d") + tests64gc.append("arch64zfh") tests64gc.append("arch64f_fma") - tests64gc.append("arch64d_fma") + tests64gc.append("arch64d_fma") # *** add arch64zfh_fma when available(see riscv-arch-test pr 367) + tests64gc.append("arch64f_divsqrt") + tests64gc.append("arch64d_divsqrt") + tests64gc.append("arch64zfh_divsqrt") + tests64gc.append("arch64zfaf") + tests64gc.append("arch64zfad") coverStr = '-coverage' else: coverStr = '' @@ -167,7 +173,9 @@ if (nightly): ["tlb16_rv64gc", ["wally64priv"]], ["way_1_4096_512_rv64gc", ["arch64i", "arch64a"]], ["way_2_4096_512_rv64gc", ["arch64i"]], - ["way_8_4096_512_rv64gc", ["arch64i"]] + ["way_8_4096_512_rv64gc", ["arch64i"]], + ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ] for test in derivconfigtests: config = test[0]; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b20c6a993..893eb678b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -104,6 +104,8 @@ module testbench; "arch64d": if (P.D_SUPPORTED) tests = arch64d; "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; "arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma; + "arch64f_divsqrt": if (P.F_SUPPORTED) tests = arch64f_divsqrt; + "arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt; "arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei; "arch64zicond": if (P.ZICOND_SUPPORTED) tests = arch64zicond; "imperas64i": tests = imperas64i; @@ -128,6 +130,8 @@ module testbench; "arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz; "arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb; "arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh; +// "arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma; *** not yet in riscv-arch-tst PR367 + "arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; endcase @@ -145,6 +149,8 @@ module testbench; "arch32d": if (P.D_SUPPORTED) tests = arch32d; "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; "arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma; + "arch32f_divsqrt": if (P.F_SUPPORTED) tests = arch32f_divsqrt; + "arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt; "arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei; "arch32zicond": if (P.ZICOND_SUPPORTED) tests = arch32zicond; "imperas32i": tests = imperas32i; @@ -165,6 +171,8 @@ module testbench; "arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz; "arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb; "arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh; + // "arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma; *** not yet in riscv-arch-tst PR367 + "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; "arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad; endcase diff --git a/testbench/tests.vh b/testbench/tests.vh index efb0e6788..f5c9cc0ac 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1126,10 +1126,10 @@ string imperas32f[] = '{ // "rv64i_m/F/src/fnmsub_b15-01.S" }; - string arch64f[] = '{ + string arch64f_divsqrt[] = '{ `RISCVARCHTEST, - "rv64i_m/F/src/fdiv_b1-01.S", "rv64i_m/F/src/fdiv_b20-01.S", + "rv64i_m/F/src/fdiv_b1-01.S", "rv64i_m/F/src/fdiv_b2-01.S", "rv64i_m/F/src/fdiv_b21-01.S", "rv64i_m/F/src/fdiv_b3-01.S", @@ -1147,7 +1147,11 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsqrt_b5-01.S", "rv64i_m/F/src/fsqrt_b7-01.S", "rv64i_m/F/src/fsqrt_b8-01.S", - "rv64i_m/F/src/fsqrt_b9-01.S", + "rv64i_m/F/src/fsqrt_b9-01.S" + }; + + string arch64f[] = '{ + `RISCVARCHTEST, "rv64i_m/F/src/fadd_b10-01.S", "rv64i_m/F/src/fadd_b1-01.S", "rv64i_m/F/src/fadd_b11-01.S", @@ -1178,17 +1182,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fcvt.wu.s_b27-01.S", "rv64i_m/F/src/fcvt.wu.s_b28-01.S", "rv64i_m/F/src/fcvt.wu.s_b29-01.S", - "rv64i_m/F/src/fdiv_b1-01.S", - "rv64i_m/F/src/fdiv_b20-01.S", - "rv64i_m/F/src/fdiv_b2-01.S", - "rv64i_m/F/src/fdiv_b21-01.S", - "rv64i_m/F/src/fdiv_b3-01.S", - "rv64i_m/F/src/fdiv_b4-01.S", - "rv64i_m/F/src/fdiv_b5-01.S", - "rv64i_m/F/src/fdiv_b6-01.S", - "rv64i_m/F/src/fdiv_b7-01.S", - "rv64i_m/F/src/fdiv_b8-01.S", - "rv64i_m/F/src/fdiv_b9-01.S", "rv64i_m/F/src/feq_b1-01.S", "rv64i_m/F/src/feq_b19-01.S", "rv64i_m/F/src/fle_b1-01.S", @@ -1269,15 +1262,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsgnj_b1-01.S", "rv64i_m/F/src/fsgnjn_b1-01.S", "rv64i_m/F/src/fsgnjx_b1-01.S", - "rv64i_m/F/src/fsqrt_b1-01.S", - "rv64i_m/F/src/fsqrt_b20-01.S", - "rv64i_m/F/src/fsqrt_b2-01.S", - "rv64i_m/F/src/fsqrt_b3-01.S", - "rv64i_m/F/src/fsqrt_b4-01.S", - "rv64i_m/F/src/fsqrt_b5-01.S", - "rv64i_m/F/src/fsqrt_b7-01.S", - "rv64i_m/F/src/fsqrt_b8-01.S", - "rv64i_m/F/src/fsqrt_b9-01.S", "rv64i_m/F/src/fsub_b10-01.S", "rv64i_m/F/src/fsub_b1-01.S", "rv64i_m/F/src/fsub_b11-01.S", @@ -1292,6 +1276,30 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsw-align-01.S" }; + string arch64zfh_divsqrt[] = '{ + `RISCVARCHTEST, + "rv64i_m/Zfh/src/fdiv_b20-01.S", + "rv64i_m/Zfh/src/fdiv_b1-01.S", + "rv64i_m/Zfh/src/fdiv_b2-01.S", + "rv64i_m/Zfh/src/fdiv_b21-01.S", + "rv64i_m/Zfh/src/fdiv_b3-01.S", + "rv64i_m/Zfh/src/fdiv_b4-01.S", + "rv64i_m/Zfh/src/fdiv_b5-01.S", + "rv64i_m/Zfh/src/fdiv_b6-01.S", + "rv64i_m/Zfh/src/fdiv_b7-01.S", + "rv64i_m/Zfh/src/fdiv_b8-01.S", + "rv64i_m/Zfh/src/fdiv_b9-01.S", + "rv64i_m/Zfh/src/fsqrt_b1-01.S", + "rv64i_m/Zfh/src/fsqrt_b20-01.S", + "rv64i_m/Zfh/src/fsqrt_b2-01.S", + "rv64i_m/Zfh/src/fsqrt_b3-01.S", + "rv64i_m/Zfh/src/fsqrt_b4-01.S", + "rv64i_m/Zfh/src/fsqrt_b5-01.S", + "rv64i_m/Zfh/src/fsqrt_b7-01.S", + "rv64i_m/Zfh/src/fsqrt_b8-01.S", + "rv64i_m/Zfh/src/fsqrt_b9-01.S" + }; + string arch64zfh[] = '{ `RISCVARCHTEST, "rv64i_m/Zfh/src/fadd_b10-01.S", @@ -1342,17 +1350,6 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S", - "rv64i_m/Zfh/src/fdiv_b20-01.S", - "rv64i_m/Zfh/src/fdiv_b1-01.S", - "rv64i_m/Zfh/src/fdiv_b2-01.S", - "rv64i_m/Zfh/src/fdiv_b21-01.S", - "rv64i_m/Zfh/src/fdiv_b3-01.S", - "rv64i_m/Zfh/src/fdiv_b4-01.S", - "rv64i_m/Zfh/src/fdiv_b5-01.S", - "rv64i_m/Zfh/src/fdiv_b6-01.S", - "rv64i_m/Zfh/src/fdiv_b7-01.S", - "rv64i_m/Zfh/src/fdiv_b8-01.S", - "rv64i_m/Zfh/src/fdiv_b9-01.S", "rv64i_m/Zfh/src/feq_b1-01.S", "rv64i_m/Zfh/src/feq_b19-01.S", "rv64i_m/Zfh/src/fle_b1-01.S", @@ -1385,15 +1382,6 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fsgnj_b1-01.S", "rv64i_m/Zfh/src/fsgnjn_b1-01.S", "rv64i_m/Zfh/src/fsgnjx_b1-01.S", - "rv64i_m/Zfh/src/fsqrt_b1-01.S", - "rv64i_m/Zfh/src/fsqrt_b20-01.S", - "rv64i_m/Zfh/src/fsqrt_b2-01.S", - "rv64i_m/Zfh/src/fsqrt_b3-01.S", - "rv64i_m/Zfh/src/fsqrt_b4-01.S", - "rv64i_m/Zfh/src/fsqrt_b5-01.S", - "rv64i_m/Zfh/src/fsqrt_b7-01.S", - "rv64i_m/Zfh/src/fsqrt_b8-01.S", - "rv64i_m/Zfh/src/fsqrt_b9-01.S", "rv64i_m/Zfh/src/fsub_b10-01.S", "rv64i_m/Zfh/src/fsub_b1-01.S", "rv64i_m/Zfh/src/fsub_b11-01.S", @@ -1417,9 +1405,8 @@ string imperas32f[] = '{ // "rv64i_m/D/src/fnmsub.d_b15-01.S" }; - string arch64d[] = '{ + string arch64d_divsqrt[] = '{ `RISCVARCHTEST, - // for speed "rv64i_m/D/src/fdiv.d_b1-01.S", "rv64i_m/D/src/fdiv.d_b20-01.S", "rv64i_m/D/src/fdiv.d_b2-01.S", @@ -1439,8 +1426,13 @@ string imperas32f[] = '{ "rv64i_m/D/src/fsqrt.d_b5-01.S", "rv64i_m/D/src/fsqrt.d_b7-01.S", "rv64i_m/D/src/fsqrt.d_b8-01.S", - "rv64i_m/D/src/fsqrt.d_b9-01.S", - "rv64i_m/D/src/fadd.d_b10-01.S", + "rv64i_m/D/src/fsqrt.d_b9-01.S" + }; + + string arch64d[] = '{ + `RISCVARCHTEST, + // for speed + "rv64i_m/D/src/fadd.d_b10-01.S", "rv64i_m/D/src/fadd.d_b1-01.S", "rv64i_m/D/src/fadd.d_b11-01.S", "rv64i_m/D/src/fadd.d_b12-01.S", @@ -1502,17 +1494,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fcvt.wu.d_b27-01.S", "rv64i_m/D/src/fcvt.wu.d_b28-01.S", "rv64i_m/D/src/fcvt.wu.d_b29-01.S", - "rv64i_m/D/src/fdiv.d_b1-01.S", - "rv64i_m/D/src/fdiv.d_b20-01.S", - "rv64i_m/D/src/fdiv.d_b2-01.S", - "rv64i_m/D/src/fdiv.d_b21-01.S", - "rv64i_m/D/src/fdiv.d_b3-01.S", - "rv64i_m/D/src/fdiv.d_b4-01.S", - "rv64i_m/D/src/fdiv.d_b5-01.S", - "rv64i_m/D/src/fdiv.d_b6-01.S", - "rv64i_m/D/src/fdiv.d_b7-01.S", - "rv64i_m/D/src/fdiv.d_b8-01.S", - "rv64i_m/D/src/fdiv.d_b9-01.S", "rv64i_m/D/src/feq.d_b1-01.S", "rv64i_m/D/src/feq.d_b19-01.S", "rv64i_m/D/src/fle.d_b1-01.S", @@ -1590,15 +1571,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fsgnj.d_b1-01.S", "rv64i_m/D/src/fsgnjn.d_b1-01.S", "rv64i_m/D/src/fsgnjx.d_b1-01.S", - "rv64i_m/D/src/fsqrt.d_b1-01.S", - "rv64i_m/D/src/fsqrt.d_b20-01.S", - "rv64i_m/D/src/fsqrt.d_b2-01.S", - "rv64i_m/D/src/fsqrt.d_b3-01.S", - "rv64i_m/D/src/fsqrt.d_b4-01.S", - "rv64i_m/D/src/fsqrt.d_b5-01.S", - "rv64i_m/D/src/fsqrt.d_b7-01.S", - "rv64i_m/D/src/fsqrt.d_b8-01.S", - "rv64i_m/D/src/fsqrt.d_b9-01.S", "rv64i_m/D/src/fssub.d_b10-01.S", "rv64i_m/D/src/fssub.d_b1-01.S", "rv64i_m/D/src/fssub.d_b11-01.S", @@ -1754,6 +1726,30 @@ string arch64zbs[] = '{ // "rv32i_m/F/src/fnmsub_b15-01.S" }; + string arch32f_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/F/src/fdiv_b20-01.S", + "rv32i_m/F/src/fdiv_b1-01.S", + "rv32i_m/F/src/fdiv_b2-01.S", + "rv32i_m/F/src/fdiv_b21-01.S", + "rv32i_m/F/src/fdiv_b3-01.S", + "rv32i_m/F/src/fdiv_b4-01.S", + "rv32i_m/F/src/fdiv_b5-01.S", + "rv32i_m/F/src/fdiv_b6-01.S", + "rv32i_m/F/src/fdiv_b7-01.S", + "rv32i_m/F/src/fdiv_b8-01.S", + "rv32i_m/F/src/fdiv_b9-01.S", + "rv32i_m/F/src/fsqrt_b1-01.S", + "rv32i_m/F/src/fsqrt_b20-01.S", + "rv32i_m/F/src/fsqrt_b2-01.S", + "rv32i_m/F/src/fsqrt_b3-01.S", + "rv32i_m/F/src/fsqrt_b4-01.S", + "rv32i_m/F/src/fsqrt_b5-01.S", + "rv32i_m/F/src/fsqrt_b7-01.S", + "rv32i_m/F/src/fsqrt_b8-01.S", + "rv32i_m/F/src/fsqrt_b9-01.S" + }; + string arch32f[] = '{ `RISCVARCHTEST, "rv32i_m/F/src/fadd_b10-01.S", @@ -1786,17 +1782,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fcvt.wu.s_b27-01.S", "rv32i_m/F/src/fcvt.wu.s_b28-01.S", "rv32i_m/F/src/fcvt.wu.s_b29-01.S", - "rv32i_m/F/src/fdiv_b20-01.S", - "rv32i_m/F/src/fdiv_b1-01.S", - "rv32i_m/F/src/fdiv_b2-01.S", - "rv32i_m/F/src/fdiv_b21-01.S", - "rv32i_m/F/src/fdiv_b3-01.S", - "rv32i_m/F/src/fdiv_b4-01.S", - "rv32i_m/F/src/fdiv_b5-01.S", - "rv32i_m/F/src/fdiv_b6-01.S", - "rv32i_m/F/src/fdiv_b7-01.S", - "rv32i_m/F/src/fdiv_b8-01.S", - "rv32i_m/F/src/fdiv_b9-01.S", "rv32i_m/F/src/feq_b1-01.S", "rv32i_m/F/src/feq_b19-01.S", "rv32i_m/F/src/fle_b1-01.S", @@ -1877,15 +1862,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fsgnj_b1-01.S", "rv32i_m/F/src/fsgnjn_b1-01.S", "rv32i_m/F/src/fsgnjx_b1-01.S", - "rv32i_m/F/src/fsqrt_b1-01.S", - "rv32i_m/F/src/fsqrt_b20-01.S", - "rv32i_m/F/src/fsqrt_b2-01.S", - "rv32i_m/F/src/fsqrt_b3-01.S", - "rv32i_m/F/src/fsqrt_b4-01.S", - "rv32i_m/F/src/fsqrt_b5-01.S", - "rv32i_m/F/src/fsqrt_b7-01.S", - "rv32i_m/F/src/fsqrt_b8-01.S", - "rv32i_m/F/src/fsqrt_b9-01.S", "rv32i_m/F/src/fsub_b10-01.S", "rv32i_m/F/src/fsub_b1-01.S", "rv32i_m/F/src/fsub_b11-01.S", @@ -1900,6 +1876,30 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fsw-align-01.S" }; + string arch32zfh_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/Zfh/src/fdiv_b20-01.S", + "rv32i_m/Zfh/src/fdiv_b1-01.S", + "rv32i_m/Zfh/src/fdiv_b2-01.S", + "rv32i_m/Zfh/src/fdiv_b21-01.S", + "rv32i_m/Zfh/src/fdiv_b3-01.S", + "rv32i_m/Zfh/src/fdiv_b4-01.S", + "rv32i_m/Zfh/src/fdiv_b5-01.S", + "rv32i_m/Zfh/src/fdiv_b6-01.S", + "rv32i_m/Zfh/src/fdiv_b7-01.S", + "rv32i_m/Zfh/src/fdiv_b8-01.S", + "rv32i_m/Zfh/src/fdiv_b9-01.S", + "rv32i_m/Zfh/src/fsqrt_b1-01.S", + "rv32i_m/Zfh/src/fsqrt_b20-01.S", + "rv32i_m/Zfh/src/fsqrt_b2-01.S", + "rv32i_m/Zfh/src/fsqrt_b3-01.S", + "rv32i_m/Zfh/src/fsqrt_b4-01.S", + "rv32i_m/Zfh/src/fsqrt_b5-01.S", + "rv32i_m/Zfh/src/fsqrt_b7-01.S", + "rv32i_m/Zfh/src/fsqrt_b8-01.S", + "rv32i_m/Zfh/src/fsqrt_b9-01.S" + }; + string arch32zfh[] = '{ `RISCVARCHTEST, "rv32i_m/Zfh/src/fadd_b10-01.S", @@ -1932,17 +1932,6 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S", - "rv32i_m/Zfh/src/fdiv_b20-01.S", - "rv32i_m/Zfh/src/fdiv_b1-01.S", - "rv32i_m/Zfh/src/fdiv_b2-01.S", - "rv32i_m/Zfh/src/fdiv_b21-01.S", - "rv32i_m/Zfh/src/fdiv_b3-01.S", - "rv32i_m/Zfh/src/fdiv_b4-01.S", - "rv32i_m/Zfh/src/fdiv_b5-01.S", - "rv32i_m/Zfh/src/fdiv_b6-01.S", - "rv32i_m/Zfh/src/fdiv_b7-01.S", - "rv32i_m/Zfh/src/fdiv_b8-01.S", - "rv32i_m/Zfh/src/fdiv_b9-01.S", "rv32i_m/Zfh/src/feq_b1-01.S", "rv32i_m/Zfh/src/feq_b19-01.S", "rv32i_m/Zfh/src/fle_b1-01.S", @@ -1975,15 +1964,6 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fsgnj_b1-01.S", "rv32i_m/Zfh/src/fsgnjn_b1-01.S", "rv32i_m/Zfh/src/fsgnjx_b1-01.S", - "rv32i_m/Zfh/src/fsqrt_b1-01.S", - "rv32i_m/Zfh/src/fsqrt_b20-01.S", - "rv32i_m/Zfh/src/fsqrt_b2-01.S", - "rv32i_m/Zfh/src/fsqrt_b3-01.S", - "rv32i_m/Zfh/src/fsqrt_b4-01.S", - "rv32i_m/Zfh/src/fsqrt_b5-01.S", - "rv32i_m/Zfh/src/fsqrt_b7-01.S", - "rv32i_m/Zfh/src/fsqrt_b8-01.S", - "rv32i_m/Zfh/src/fsqrt_b9-01.S", "rv32i_m/Zfh/src/fsub_b10-01.S", "rv32i_m/Zfh/src/fsub_b1-01.S", "rv32i_m/Zfh/src/fsub_b11-01.S", @@ -2086,6 +2066,30 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fnmsub.d_b15-01.S" }; + string arch32d_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/D/src/fdiv.d_b1-01.S", + "rv32i_m/D/src/fdiv.d_b20-01.S", + "rv32i_m/D/src/fdiv.d_b2-01.S", + "rv32i_m/D/src/fdiv.d_b21-01.S", + "rv32i_m/D/src/fdiv.d_b3-01.S", + "rv32i_m/D/src/fdiv.d_b4-01.S", + "rv32i_m/D/src/fdiv.d_b5-01.S", + "rv32i_m/D/src/fdiv.d_b6-01.S", + "rv32i_m/D/src/fdiv.d_b7-01.S", + "rv32i_m/D/src/fdiv.d_b8-01.S", + "rv32i_m/D/src/fdiv.d_b9-01.S", + "rv32i_m/D/src/fsqrt.d_b1-01.S", + "rv32i_m/D/src/fsqrt.d_b20-01.S", + "rv32i_m/D/src/fsqrt.d_b2-01.S", + "rv32i_m/D/src/fsqrt.d_b3-01.S", + "rv32i_m/D/src/fsqrt.d_b4-01.S", + "rv32i_m/D/src/fsqrt.d_b5-01.S", + "rv32i_m/D/src/fsqrt.d_b7-01.S", + "rv32i_m/D/src/fsqrt.d_b8-01.S", + "rv32i_m/D/src/fsqrt.d_b9-01.S" + }; + string arch32d[] = '{ `RISCVARCHTEST, "rv32i_m/D/src/fadd.d_b10-01.S", @@ -2132,17 +2136,6 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fcvt.wu.d_b27-01.S", "rv32i_m/D/src/fcvt.wu.d_b28-01.S", "rv32i_m/D/src/fcvt.wu.d_b29-01.S", - "rv32i_m/D/src/fdiv.d_b1-01.S", - "rv32i_m/D/src/fdiv.d_b20-01.S", - "rv32i_m/D/src/fdiv.d_b2-01.S", - "rv32i_m/D/src/fdiv.d_b21-01.S", - "rv32i_m/D/src/fdiv.d_b3-01.S", - "rv32i_m/D/src/fdiv.d_b4-01.S", - "rv32i_m/D/src/fdiv.d_b5-01.S", - "rv32i_m/D/src/fdiv.d_b6-01.S", - "rv32i_m/D/src/fdiv.d_b7-01.S", - "rv32i_m/D/src/fdiv.d_b8-01.S", - "rv32i_m/D/src/fdiv.d_b9-01.S", "rv32i_m/D/src/feq.d_b1-01.S", "rv32i_m/D/src/feq.d_b19-01.S", "rv32i_m/D/src/fle.d_b1-01.S", @@ -2211,15 +2204,6 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fsgnj.d_b1-01.S", "rv32i_m/D/src/fsgnjn.d_b1-01.S", "rv32i_m/D/src/fsgnjx.d_b1-01.S", - "rv32i_m/D/src/fsqrt.d_b1-01.S", - "rv32i_m/D/src/fsqrt.d_b20-01.S", - "rv32i_m/D/src/fsqrt.d_b2-01.S", - "rv32i_m/D/src/fsqrt.d_b3-01.S", - "rv32i_m/D/src/fsqrt.d_b4-01.S", - "rv32i_m/D/src/fsqrt.d_b5-01.S", - "rv32i_m/D/src/fsqrt.d_b7-01.S", - "rv32i_m/D/src/fsqrt.d_b8-01.S", - "rv32i_m/D/src/fsqrt.d_b9-01.S", "rv32i_m/D/src/fssub.d_b10-01.S", "rv32i_m/D/src/fssub.d_b1-01.S", "rv32i_m/D/src/fssub.d_b11-01.S", From 03fc8e8ef6fca98d212d9cc18bc3073b630516d5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 15:00:50 -0800 Subject: [PATCH 05/10] More nightly regression cases; not all are passing --- sim/regression-wally | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/sim/regression-wally b/sim/regression-wally index ef495df50..07c3774ed 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -171,10 +171,49 @@ if (nightly): ["tlb16_rv32gc", ["wally32priv"]], ["tlb2_rv64gc", ["wally64priv"]], ["tlb16_rv64gc", ["wally64priv"]], - ["way_1_4096_512_rv64gc", ["arch64i", "arch64a"]], + ["way_1_4096_512_rv32gc", ["arch32i"]], + ["way_2_4096_512_rv32gc", ["arch32i"]], + ["way_8_4096_512_rv32gc", ["arch32i"]], + ["way_4_2048_512_rv32gc", ["arch32i"]], + ["way_4_4096_256_rv32gc", ["arch32i"]], + ["way_4_4096_1024_rv32gc", ["arch32i"]], + ["way_1_4096_512_rv64gc", ["arch64i"]], ["way_2_4096_512_rv64gc", ["arch64i"]], ["way_8_4096_512_rv64gc", ["arch64i"]], + ["way_4_2048_512_rv64gc", ["arch64i"]], + ["way_4_4096_256_rv64gc", ["arch64i"]], + ["way_4_4096_1024_rv64gc", ["arch64i"]], + + ["ram_0_0_rv64gc", ["ahb"]], + ["ram_1_0_rv64gc", ["ahb"]], + ["ram_1_1_rv64gc", ["ahb"]], + ["ram_2_0_rv64gc", ["ahb"]], + ["ram_2_1_rv64gc", ["ahb"]], + ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], ] for test in derivconfigtests: From a4ca024025c791a1822c00eb02bc3c2ff1810cd7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 20:03:14 -0800 Subject: [PATCH 06/10] Lint progress --- config/buildroot/config.vh | 184 --------------------------------- config/derivlist.txt | 17 ++- config/shared/config-shared.vh | 2 +- sim/lint-wally | 29 ++++-- 4 files changed, 39 insertions(+), 193 deletions(-) delete mode 100644 config/buildroot/config.vh diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh deleted file mode 100644 index 6629af297..000000000 --- a/config/buildroot/config.vh +++ /dev/null @@ -1,184 +0,0 @@ -////////////////////////////////////////// -// config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "BranchPredictorType.vh" - -// RV32 or RV64: XLEN = 32 or 64 -localparam XLEN = 32'd64; - -// IEEE 754 compliance -localparam IEEE754 = 0; - -localparam MISA = (32'h0014112D); -localparam ZICSR_SUPPORTED = 1; -localparam ZIFENCEI_SUPPORTED = 1; -localparam ZICNTR_SUPPORTED = 1; -localparam ZIHPM_SUPPORTED = 1; -localparam COUNTERS = 12'd32; -localparam ZFH_SUPPORTED = 1; -localparam ZFA_SUPPORTED = 0; -localparam SSTC_SUPPORTED = 1; -localparam ZICBOM_SUPPORTED = 1; -localparam ZICBOZ_SUPPORTED = 1; -localparam ZICBOP_SUPPORTED = 1; -localparam ZICCLSM_SUPPORTED = 1; -localparam ZICOND_SUPPORTED = 1; -localparam SVPBMT_SUPPORTED = 1; -localparam SVNAPOT_SUPPORTED = 1; -localparam SVINVAL_SUPPORTED = 1; - -// LSU microarchitectural Features -localparam BUS_SUPPORTED = 1; -localparam DCACHE_SUPPORTED = 1; -localparam ICACHE_SUPPORTED = 1; -localparam VIRTMEM_SUPPORTED = 1; -localparam VECTORED_INTERRUPTS_SUPPORTED = 1; -localparam BIGENDIAN_SUPPORTED = 1; - -// TLB configuration. Entries should be a power of 2 -localparam ITLB_ENTRIES = 32'd32; -localparam DTLB_ENTRIES = 32'd32; - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -localparam DCACHE_NUMWAYS = 32'd4; -localparam DCACHE_WAYSIZEINBYTES = 32'd4096; -localparam DCACHE_LINELENINBITS = 32'd512; -localparam ICACHE_NUMWAYS = 32'd4; -localparam ICACHE_WAYSIZEINBYTES = 32'd4096; -localparam ICACHE_LINELENINBITS = 32'd512; -localparam CACHE_SRAMLEN = 32'd128; - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 32'd4; -localparam IDIV_ON_FPU = 1; - -// Legal number of PMP entries are 0, 16, or 64 -localparam PMP_ENTRIES = 32'd16; - -// Address space -localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000; - -// WFI Timeout Wait -localparam WFI_TIMEOUT_BIT = 32'd16; - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -localparam DTIM_SUPPORTED = 1'b0; -localparam logic [63:0] DTIM_BASE = 64'h80000000; -localparam logic [63:0] DTIM_RANGE = 64'h00001FFF; -localparam IROM_SUPPORTED = 1'b0; -localparam logic [63:0] IROM_BASE = 64'h80000000; -localparam logic [63:0] IROM_RANGE = 64'h00001FFF; -localparam BOOTROM_SUPPORTED = 1'b1; -localparam logic [63:0] BOOTROM_BASE = 64'h00001000 ; -localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b1; -localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h0FFFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b1; -localparam EXT_MEM_SUPPORTED = 1'b0; -localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; -localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; -localparam CLINT_SUPPORTED = 1'b1; -localparam logic [63:0] CLINT_BASE = 64'h02000000; -localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; -localparam GPIO_SUPPORTED = 1'b1; -localparam logic [63:0] GPIO_BASE = 64'h10060000; -localparam logic [63:0] GPIO_RANGE = 64'h000000FF; -localparam UART_SUPPORTED = 1'b1; -localparam logic [63:0] UART_BASE = 64'h10000000; -localparam logic [63:0] UART_RANGE = 64'h00000007; -localparam PLIC_SUPPORTED = 1'b1; -localparam logic [63:0] PLIC_BASE = 64'h0C000000; -localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; -localparam SDC_SUPPORTED = 1'b0; -localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; -localparam SPI_SUPPORTED = 1'b1; -localparam logic [63:0] SPI_BASE = 64'h10040000; -localparam logic [63:0] SPI_RANGE = 64'h00000FFF; - -// Bus Interface width -localparam AHBW = 32'd64; - -// AHB -localparam RAM_LATENCY = 32'b0; -localparam BURST_EN = 1; - -// Test modes - -// Tie GPIO outputs back to inputs -localparam GPIO_LOOPBACK_TEST = 0; -localparam SPI_LOOPBACK_TEST = 0; - -// Hardware configuration -localparam UART_PRESCALE = 32'd0; - -// Interrupt configuration -localparam PLIC_NUM_SRC = 32'd53; -localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); -localparam PLIC_UART_ID = 32'd10; -localparam PLIC_GPIO_ID = 32'd3; -localparam PLIC_SPI_ID = 32'd6; -localparam PLIC_SDC_ID = 32'd20; - -localparam BPRED_SUPPORTED = 1; -localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 32'd10; -localparam BPRED_NUM_LHR = 32'd6; -localparam BTB_SIZE = 32'd10; -localparam RAS_SIZE = 32'd16; -localparam INSTR_CLASS_PRED = 1; - -localparam SVADU_SUPPORTED = 1; -localparam ZMMUL_SUPPORTED = 0; - -// FPU division architecture -localparam RADIX = 32'h4; -localparam DIVCOPIES = 32'h4; - -// bit manipulation -localparam ZBA_SUPPORTED = 1; -localparam ZBB_SUPPORTED = 1; -localparam ZBC_SUPPORTED = 1; -localparam ZBS_SUPPORTED = 1; - -// New compressed instructions -localparam ZCB_SUPPORTED = 1; -localparam ZCA_SUPPORTED = 0; -localparam ZCF_SUPPORTED = 0; -localparam ZCD_SUPPORTED = 0; - -// Memory synthesis configuration -localparam USE_SRAM = 0; - -`include "config-shared.vh" diff --git a/config/derivlist.txt b/config/derivlist.txt index 581922b9c..5496dd1db 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -41,8 +41,8 @@ RESET_VECTOR 64'h1000 UNCORE_RAM_RANGE 64'h0FFFFFFF UNCORE_RAM_PRELOAD 1 GPIO_LOOPBACK_TEST 0 -SPI_LOOPBACK_TEST 0 -UART_PRESCALE 0 +SPI_LOOPBACK_TEST 0 +UART_PRESCALE 32'd0 PLIC_NUM_SRC 32'd53 # fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM) @@ -119,26 +119,33 @@ MISA (32'h00000104 | 1 << 18 | 1 << 20) deriv div_2_1_rv32gc rv32gc RADIX 32'd2 DIVCOPIES 32'd1 +IDIV_ON_FPU 0 deriv div_2_2_rv32gc rv32gc RADIX 32'd2 DIVCOPIES 32'd2 +IDIV_ON_FPU 0 deriv div_2_4_rv32gc rv32gc RADIX 32'd2 DIVCOPIES 32'd4 +IDIV_ON_FPU 0 deriv div_4_1_rv32gc rv32gc RADIX 32'd4 DIVCOPIES 32'd1 +IDIV_ON_FPU 0 deriv div_4_2_rv32gc rv32gc RADIX 32'd4 +IDIV_ON_FPU 0 DIVCOPIES 32'd2 +IDIV_ON_FPU 0 deriv div_4_4_rv32gc rv32gc RADIX 32'd4 DIVCOPIES 32'd4 +IDIV_ON_FPU 0 deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc IDIV_ON_FPU 1 @@ -161,26 +168,32 @@ IDIV_ON_FPU 1 deriv div_2_1_rv64gc rv64gc RADIX 32'd2 DIVCOPIES 32'd1 +IDIV_ON_FPU 0 deriv div_2_2_rv64gc rv64gc RADIX 32'd2 DIVCOPIES 32'd2 +IDIV_ON_FPU 0 deriv div_2_4_rv64gc rv64gc RADIX 32'd2 DIVCOPIES 32'd4 +IDIV_ON_FPU 0 deriv div_4_1_rv64gc rv64gc RADIX 32'd4 DIVCOPIES 32'd1 +IDIV_ON_FPU 0 deriv div_4_2_rv64gc rv64gc RADIX 32'd4 DIVCOPIES 32'd2 +IDIV_ON_FPU 0 deriv div_4_4_rv64gc rv64gc RADIX 32'd4 DIVCOPIES 32'd4 +IDIV_ON_FPU 0 deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc IDIV_ON_FPU 1 diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index ba215785c..6f25b0cc5 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -103,7 +103,7 @@ localparam RESBITS = DIVMINb + LOGR; // number of bits in a result: r intege localparam FPDUR = (RESBITS-1)/RK + 1 ; // ceiling((r+b)/rk) localparam DIVb = FPDUR*RK - LOGR; // divsqrt fractional bits, so total number of bits is a multiple of rk after r integer bits localparam DURLEN = $clog2(FPDUR); // enough bits to count the duration -localparam DIVBLEN = $clog2(DIVb); // enough bits to count number of fractional bits +localparam DIVBLEN = $clog2(DIVb+1); // enough bits to count number of fractional bits + 1 integer bit // largest length in IEU/FPU localparam CVTLEN = ((NF 0 ); then + echo -e "${RED}Linting failed for $fails configurations" + exit 1 +fi +echo -e "${GREEN}All lints run with no errors or warnings" # --lint-only just runs lint rather than trying to compile and simulate # -I points to the include directory where files such as `include config.vh are found From 1c62c5e433908d68cb23558ac5fc92e42b985421 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 20:24:16 -0800 Subject: [PATCH 07/10] Fixed logic to work with FLEN < XLEN --- sim/lint-wally | 10 +++++----- src/fpu/fpu.sv | 9 +++++++-- src/lsu/lsu.sv | 6 +++++- 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/sim/lint-wally b/sim/lint-wally index 1ad1084be..0638681ce 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -21,7 +21,7 @@ if [ "$1" == "-nightly" ]; then fi done else - configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i div_2_1i_rv64gc fdqh_rv64gc) + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i div_2_1i_rv64gc ) # add fdqh_rv64gc when working fi for config in ${configs[@]}; do @@ -29,7 +29,7 @@ for config in ${configs[@]}; do if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then if [ "$1" == "-nightly" ]; then echo -e "${RED}$config failed lint${NC}" - fails=$fails+1 + fails=$((fails+1)) else echo -e "${RED}$config fails with lint errors or warnings" exit 1 @@ -38,11 +38,11 @@ for config in ${configs[@]}; do echo -e "${GREEN}$config passed lint${NC}" fi done -if ( $fails > 0 ); then - echo -e "${RED}Linting failed for $fails configurations" +if [ $fails > 0 ]; then + echo -e "${RED}Linting failed for $fails of ${#configs[@]} configurations" exit 1 fi -echo -e "${GREEN}All lints run with no errors or warnings" +echo -e "${GREEN}All ${#configs[@]} lints run with no errors or warnings" # --lint-only just runs lint rather than trying to compile and simulate # -I points to the include directory where files such as `include config.vh are found diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 85021d269..54957d530 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -278,9 +278,14 @@ module fpu import cvw::*; #(parameter cvw_t P) ( end else assign FliResE = '0; // fmv.*.x: NaN Box SrcA to extend integer to requested FP size - if(P.FPSIZES == 1) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}; + if(P.FPSIZES == 1) + if (P.FLEN >= P.XLEN) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}; + else assign PreIntSrcE = ForwardedSrcAE[P.FLEN-1:0]; else if(P.FPSIZES == 2) - mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE); + if (P.FLEN >= P.XLEN) + mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE); + else + mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, ForwardedSrcAE[P.FLEN-1:0], FmtE, PreIntSrcE); else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index c997d58ff..2d0fd101e 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -406,7 +406,11 @@ module lsu import cvw::*; #(parameter cvw_t P) ( end if (P.F_SUPPORTED) - mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM); + if (P.FLEN >= P.XLEN) + mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM); + else + mux2 #(P.LLEN) datamux(IMAWriteDataM, {{{P.XLEN-P.FLEN}{1'b0}}, FWriteDataM}, FpLoadStoreM, IMAFWriteDataM); + else assign IMAFWriteDataM = IMAWriteDataM; ///////////////////////////////////////////////////////////////////////////////////////////// From 9bd0027c942485ca7413fc938f8c3727ec6750d6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 20:35:34 -0800 Subject: [PATCH 08/10] Removed AHB-specific testing and replaced with ram configs --- sim/regression-wally | 29 ++++++++++++++++++----------- sim/wally-batch.do | 25 +------------------------ sim/wally.do | 7 +------ 3 files changed, 20 insertions(+), 41 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 07c3774ed..43c4220c4 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -85,7 +85,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zfad", +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zbc", "arch32zfad", #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( @@ -124,16 +124,16 @@ for test in tests32e: grepstr="All tests ran without failures") configs.append(tc) -ahbTests = [("0", "0"), ("0", "1"), ("1", "0"), ("1", "1"), ("2", "0"), ("2", "1")] -for test in ahbTests: - tc = TestCase( - name="ram_latency_" + test[0] + "_burst_en_" + test[1], - variant="ahb", - cmd="vsim > {} -c < {} -c < Date: Wed, 31 Jan 2024 21:39:18 -0800 Subject: [PATCH 09/10] Fixed assertions to throw fatal error, improved nightly regression to have passing cases --- config/derivlist.txt | 40 ++++++++----- sim/regression-wally | 48 +++++++++------- testbench/common/riscvassertions.sv | 89 ++++++++++++++--------------- testbench/testbench.sv | 3 +- testbench/tests.vh | 7 ++- 5 files changed, 105 insertions(+), 82 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 5496dd1db..558cedbe3 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -379,6 +379,7 @@ INSTR_CLASS_PRED 0 deriv noicache_rv32gc rv32gc ICACHE_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 deriv nodcache_rv32gc rv32gc DCACHE_SUPPORTED 0 @@ -387,6 +388,31 @@ deriv nocache_rv32gc rv32gc ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 +deriv noicache_rv64gc rv64gc +ICACHE_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 +SVPBMT_SUPPORTED 0 +SVNAPOT_SUPPORTED 0 + +deriv nodcache_rv64gc rv64gc +DCACHE_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 +ZICBOM_SUPPORTED 0 +ZICBOZ_SUPPORTED 0 +SVPBMT_SUPPORTED 0 +SVNAPOT_SUPPORTED 0 +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12) + +deriv nocache_rv64gc rv64gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 +ZICBOM_SUPPORTED 0 +ZICBOZ_SUPPORTED 0 +SVPBMT_SUPPORTED 0 +SVNAPOT_SUPPORTED 0 +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12) + deriv way_1_4096_512_rv32gc rv32gc DCACHE_NUMWAYS 32'd1 DCACHE_WAYSIZEINBYTES 32'd4096 @@ -415,20 +441,6 @@ deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc DCACHE_LINELENINBITS 32'd256 ICACHE_LINELENINBITS 32'd256 -deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_LINELENINBITS 32'd1024 -ICACHE_LINELENINBITS 32'd1024 - -deriv noicache_rv64gc rv64gc -ICACHE_SUPPORTED 0 - -deriv nodcache_rv64gc rv64gc -DCACHE_SUPPORTED 0 - -deriv nocache_rv64gc rv64gc -ICACHE_SUPPORTED 0 -DCACHE_SUPPORTED 0 - deriv way_1_4096_512_rv64gc rv64gc DCACHE_NUMWAYS 32'd1 DCACHE_WAYSIZEINBYTES 32'd4096 diff --git a/sim/regression-wally b/sim/regression-wally index 43c4220c4..5f4e68bf1 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -124,15 +124,6 @@ for test in tests32e: grepstr="All tests ran without failures") configs.append(tc) -#ahbTests = [("0", "0"), ("0", "1"), ("1", "0"), ("1", "1"), ("2", "0"), ("2", "1")] -#for test in ahbTests: -# tc = TestCase( -# name="ram_latency_" + test[0] + "_burst_en_" + test[1], -# variant="ahb", -# cmd="vsim > {} -c < XLEN +# ["nodcache_rv32gc", ["ahb32"]], +# ["nocache_rv32gc", ["ahb32"]], + ["noicache_rv64gc", ["ahb64"]], + ["nodcache_rv64gc", ["ahb64"]], + ["nocache_rv64gc", ["ahb64"]], + + ### add misaligned tests ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], @@ -222,6 +215,19 @@ if (nightly): ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], +# enable floating-point tests when lint is fixed +# ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], +# ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], +# ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], +# ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], +# ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], +# ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]], +# ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed +# ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], +# ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], +# ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], + + ] for test in derivconfigtests: config = test[0]; diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index dcbe7e32a..2fc7e06a8 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -21,53 +21,52 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); initial begin - assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); - assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); - assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); - assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); - assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); - assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); - assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); - assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); - assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); - assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); + assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support"); + assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); + assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)"); + assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)"); + assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)"); + assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); + assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported"); + assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $fatal(1, "Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); + assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size"); + assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size"); + assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2"); assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF"); - assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); + assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); + assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported"); assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); - assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); - assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally."); - assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); - assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); - assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); - assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); - assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); - assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM requires DCACHE_SUPPORTED"); - assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ requires DCACHE_SUPPORTED"); - assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP requires DCACHE_SUPPORTED"); - assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVPBMT requires VIRTMEM_SUPPORTED and RV64"); - assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVNAPOT requires VIRTMEM_SUPPORTED and RV64"); - assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $error("ZCB requires M and ZBB (and also ZBA for RV64)"); - assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $error("C and ZCA/ZCD/ZCF cannot simultaneously be supported"); - assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $error("ZCF or ZCD requires ZCA"); - assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $error("ZCF requires F"); - assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $error("ZCD requires D"); + assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); + assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache"); + assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache"); + assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED."); + assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16"); + assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); + assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally."); + assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED"); + assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED"); + assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $fatal(1, "At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); + assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); + assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); + assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED"); + assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED"); + assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64"); + assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64"); + assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $fatal(1, "ZCB requires M and ZBB (and also ZBA for RV64)"); + assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $fatal(1, "C and ZCA/ZCD/ZCF cannot simultaneously be supported"); + assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA"); + assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F"); + assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D"); end endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 893eb678b..eafcce2e6 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -121,7 +121,7 @@ module testbench; "wally64periph": tests = wally64periph; "coremark": tests = coremark; "fpga": tests = fpga; - "ahb" : tests = ahb; + "ahb64" : tests = ahb64; "coverage64gc" : tests = coverage64gc; "arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba; "arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb; @@ -162,6 +162,7 @@ module testbench; "wally32i": tests = wally32i; "wally32priv": tests = wally32priv; "wally32periph": tests = wally32periph; + "ahb32" : tests = ahb32; "embench": tests = embench; "coremark": tests = coremark; "arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba; diff --git a/testbench/tests.vh b/testbench/tests.vh index f5c9cc0ac..42f3d703a 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -2472,7 +2472,12 @@ string arch64zbs[] = '{ }; - string ahb[] = '{ + string ahb64[] = '{ `RISCVARCHTEST, "rv64i_m/F/src/fadd_b11-01.S" }; + + string ahb32[] = '{ + `RISCVARCHTEST, + "rv32i_m/F/src/fadd_b11-01.S" + }; From 4adc38deb59a7b4cc8323b1fc6239f625944c4fb Mon Sep 17 00:00:00 2001 From: Thomas Kidd <89825065+Thomas-J-Kidd@users.noreply.github.com> Date: Thu, 1 Feb 2024 10:44:36 -0600 Subject: [PATCH 10/10] Adding nightly regression into the bin directory (#607) * updated install tool chain file to use verilator v5.016 * updated gitignore file * adding nightly tests * reverted the verilator checkout to checkout master * Revert "reverted the verilator checkout to checkout master" This reverts commit 942a2804c33a28cf31171f4a203144a91f50fb15. * Revert "updated gitignore file" This reverts commit 981c3ccf6b4775505c6356ff3e9bd60f7f0ba5f4. * Revert "updated install tool chain file to use verilator v5.016" This reverts commit 3168859268dfa125d79f35cabb9c1b86feaa363f. * Revert "updated gitignore file" This reverts commit 981c3ccf6b4775505c6356ff3e9bd60f7f0ba5f4. --- bin/nightly_build/nightly_build_v13_beta.sh | 85 ++++++++++++++++ bin/nightly_build/src/error_detector.py | 37 +++++++ bin/nightly_build/src/parse_coverage.py | 95 ++++++++++++++++++ bin/nightly_build/src/parse_regression.py | 102 ++++++++++++++++++++ bin/nightly_build/src/send_mail_html.sh | 79 +++++++++++++++ 5 files changed, 398 insertions(+) create mode 100755 bin/nightly_build/nightly_build_v13_beta.sh create mode 100644 bin/nightly_build/src/error_detector.py create mode 100644 bin/nightly_build/src/parse_coverage.py create mode 100644 bin/nightly_build/src/parse_regression.py create mode 100755 bin/nightly_build/src/send_mail_html.sh diff --git a/bin/nightly_build/nightly_build_v13_beta.sh b/bin/nightly_build/nightly_build_v13_beta.sh new file mode 100755 index 000000000..2e0ca42d4 --- /dev/null +++ b/bin/nightly_build/nightly_build_v13_beta.sh @@ -0,0 +1,85 @@ +#!/bin/bash + +# set WALLY path +WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) +export WALLY=$(cd "$WALLY/../../" && pwd) +echo "WALLY is set to: $WALLY" + +# Going to nightly runs +cd $WALLY/../ + +# check if directories exist +if [ ! -d "build-results" ]; then + echo "Directory does not exist, creating it..." + mkdir -p "build-results" + if [ $? -eq 0 ]; then + echo "Directory created successfully." + else + echo "Failed to create directory." + exit 1 + fi +else + echo "Directory already exists." +fi + +if [ ! -d "logs" ]; then + echo "Directory does not exist, creating it..." + mkdir -p "logs" + if [ $? -eq 0 ]; then + echo "Directory created successfully." + else + echo "Failed to create directory." + exit 1 + fi +else + echo "Directory already exists." +fi + +# setup source okstate file +echo "Sourcing setup files" +source $WALLY/setup_host.sh +source $WALLY/../setup-files/setup_tools.sh + +# Navigate to the gir repo +cd $WALLY + +# pull the repository +echo "Pulling submodules" +#git pull --recurse-submodules origin main + +# build the regression tests +echo "Building the regression tests" +cd sim +#if make wally-riscv-arch-test; then +#if make all; then +# echo "Make successfull" +#else +# echo "Make failed" +# cd $WALLY/.. + # add the the regression result and the coverage result that there was an error in making the tests +# python $WALLY/bin/nightly_build/src/error_detector.py --tag make -o $WALLY/../build-results/regression_results.md +# python $WALLY/bin/nightly_build/src/error_detector.py --tag make -o $WALLY/../build-results/coverage_results.md + + # exit the program + #exit 1 +#fi + +# execute the simulation / regression tests and save output to a file +echo "running the regression test" +#./regression-wally > $WALLY/../logs/regression_output.log 2>&1 + +echo "running coverage tests" +#./coverage > $WALLY/../logs/coverage_output.log 2>&1 + + +# run the Python script to parse the output and generate the log file +echo "Parsing output data from the regression test" +cd $WALLY/../ + +python $WALLY/bin/nightly_build/src/parse_regression.py -i $WALLY/../logs/regression_output.log -o $WALLY/../build-results/regression_results.md + +python $WALLY/bin/nightly_build/src/parse_coverage.py -i $WALLY/../logs/coverage_output.log -o $WALLY/../build-results/coverage_results.md + +# email update +cd $WALLY/bin/nightly_build/src/ +./send_mail_html.sh diff --git a/bin/nightly_build/src/error_detector.py b/bin/nightly_build/src/error_detector.py new file mode 100644 index 000000000..c239032e9 --- /dev/null +++ b/bin/nightly_build/src/error_detector.py @@ -0,0 +1,37 @@ +import argparse +import datetime + +def add_failure_to_markdown(tag, output_file, input_file = None): + # Get the current date and time + current_datetime = datetime.datetime.now() + formatted_datetime = current_datetime.strftime("%Y-%m-%d %H:%M:%S") + + # Create the failure message based on the provided tag and input content + if tag == "make": + failure_message = f"# {tag.capitalize()} riscof comilation failure - {formatted_datetime}\n\n" + failure_message += f"The error was due to a problem in compiling the the riscof tests:\n\n" + if input_file != None: + failure_message += f"The particular error: {input_file}\n\n" + else: + failure_message = f"# {tag.capitalize()} Failure - {formatted_datetime}\n\n" + failure_message += f":\n\n" + + # Append the failure message to the specified output file + with open(output_file, "a") as file: + file.write(failure_message) + + print(f"Failure information added to {output_file}.") + +if __name__ == "__main__": + # Set up argparse + parser = argparse.ArgumentParser(description="Add failure information to Markdown file.") + parser.add_argument("--tag", required=True, help="Specify the tag for the failure type (e.g., 'make', 'custom').") + parser.add_argument("-i", required=False, help="Specify the input file containing failure details.") + parser.add_argument("-o", required=True, help="Specify the output file to write the failure information.") + + # Parse command-line arguments + args = parser.parse_args() + + # Call the function with the specified tag, input file, and output file + add_failure_to_markdown(args.tag, args.o) + diff --git a/bin/nightly_build/src/parse_coverage.py b/bin/nightly_build/src/parse_coverage.py new file mode 100644 index 000000000..33811b0a1 --- /dev/null +++ b/bin/nightly_build/src/parse_coverage.py @@ -0,0 +1,95 @@ +import os +import argparse +from datetime import datetime +import re +from colorama import init, Fore, Style + +def parse_regression_output(output): + passed_configs = [] + failed_configs = [] + + lines = output.split('\n') + index = 0 + + while index < len(lines): + # Remove ANSI escape codes + line = re.sub(r'\x1b\[[0-9;]*[mGK]', '', lines[index]) + if "Success" in line: + passed_configs.append(line.split(':')[0].strip()) + elif "Failures detected in output" in line: + try: + config_name = line.split(':')[0].strip() + log_file = os.path.abspath(config_name+".log") + failed_configs.append((config_name, log_file)) + except: + failed_configs.append((config_name, "Log file not found")) + + index += 1 + + # alphabetically sort the configurations + passed_configs.sort() + failed_configs.sort() + return passed_configs, failed_configs + +def write_to_markdown(passed_configs, failed_configs, output_file): + timestamp = datetime.now().strftime("%Y-%m-%d %H:%M:%S") + + with open(output_file, 'a') as md_file: + md_file.write(f"\n\n# Coverage Test Results - {timestamp}\n\n") + + md_file.write("\n## Failed Configurations\n") + for config, log_file in failed_configs: + md_file.write(f"- {config} ({log_file})\n") + if len(failed_configs) == 0: + md_file.write(" - no failures\n") + + md_file.write("\n## Passed Configurations\n") + for config in passed_configs: + md_file.write(f"- {config}\n") + + +def write_new_markdown(passed_configs, failed_configs): + timestamp = datetime.now().strftime("%Y-%m-%d") + output_file = f"/home/thkidd/nightly_runs/build-results/builds/coverage/wally_coverage_{timestamp}.md" + + with open(output_file, 'w') as md_file: + # Title + md_file.write(f"\n\n# Coverage Test Results - {timestamp}\n\n") + + ## File path + md_file.write(f"\n**File:** {output_file}\n") + + md_file.write("\n## Failed Configurations\n") + # add in if there were no failures + if len(failed_configs) == 0: + md_file.write(f"No Failures\n") + + for config, log_file in failed_configs: + md_file.write(f"- {config} ({log_file})\n") + + md_file.write("\n## Passed Configurations\n") + for config in passed_configs: + md_file.write(f"- {config}\n") + + + + +if __name__ == "__main__": + init(autoreset=True) # Initialize colorama + parser = argparse.ArgumentParser(description='Parse regression test output and append to a markdown file.') + parser.add_argument('-i', '--input', help='Input file containing regression test output', required=True) + parser.add_argument('-o', '--output', help='Output markdown file', default='regression_results.md') + args = parser.parse_args() + + with open(args.input, 'r') as input_file: + regression_output = input_file.read() + + passed_configs, failed_configs = parse_regression_output(regression_output) + write_to_markdown(passed_configs, failed_configs, args.output) + + print(f"Markdown file updated: {args.output}") + + write_new_markdown(passed_configs, failed_configs) + + print("New markdown file created") + diff --git a/bin/nightly_build/src/parse_regression.py b/bin/nightly_build/src/parse_regression.py new file mode 100644 index 000000000..0d8c9467d --- /dev/null +++ b/bin/nightly_build/src/parse_regression.py @@ -0,0 +1,102 @@ +import argparse +import os +from datetime import datetime +import re +from colorama import init, Fore, Style + +def parse_regression_output(output): + passed_configs = [] + failed_configs = [] + + lines = output.split('\n') + index = 0 + + while index < len(lines): + # Remove ANSI escape codes + line = re.sub(r'\x1b\[[0-9;]*[mGK]', '', lines[index]) + #print("The cleaned line: ", line) + if "Success" in line: + passed_configs.append(line.split(':')[0].strip()) + elif "Failures detected in output" in line: + try: + config_name = line.split(':')[0].strip() + log_file = os.path.abspath(config_name+".log") + failed_configs.append((config_name, log_file)) + except: + failed_configs.append((config_name, "Log file not found")) + elif "Timeout" in line: + try: + config_name = line.split(':')[0].strip() + log_file = os.path.abspath(config_name+".log") + failed_configs.append((config_name, log_file)) + except: + failed_configs.append((config_name, "Log file not found")) + index += 1 + + # alphabetically sort the configurations + passed_configs.sort() + failed_configs.sort() + return passed_configs, failed_configs + +def write_to_markdown(passed_configs, failed_configs, output_file): + timestamp = datetime.now().strftime("%Y-%m-%d %H:%M:%S") + with open(output_file, 'a') as md_file: + md_file.write(f"\n\n
\n# Regression Test Results - {timestamp}\n
\n\n") + #md_file.write(f"\n\n# Regression Test Results - {timestamp}\n\n") + + if failed_configs: + md_file.write("## Failed Configurations\n") + for config, log_file in failed_configs: + md_file.write(f"- {config} ({log_file})\n") + md_file.write("\n") + else: + md_file.write("## No Failed Configurations\n") + + md_file.write("\n## Passed Configurations\n") + for config in passed_configs: + md_file.write(f"- {config}\n") + +def write_new_markdown(passed_configs, failed_configs): + timestamp = datetime.now().strftime("%Y-%m-%d") + output_file = f"/home/thkidd/nightly_runs/build-results/builds/regression/wally_regression_{timestamp}.md" + with open(output_file, 'w') as md_file: + + # Title + md_file.write(f"\n\n# Regression Test Results - {timestamp}\n\n") + #md_file.write(f"\n\n
\n# Regression Test Results - {timestamp}\n
\n\n") + + # File Path + md_file.write(f"\n**File:** {output_file}\n\n") + + if failed_configs: + md_file.write("## Failed Configurations\n\n") + for config, log_file in failed_configs: + md_file.write(f"- {config} ({log_file})\n") + md_file.write("\n") + else: + md_file.write("## Failed Configurations\n") + md_file.write(f"No Failures\n") + + md_file.write("\n## Passed Configurations\n") + for config in passed_configs: + md_file.write(f"- {config}\n") + +if __name__ == "__main__": + init(autoreset=True) # Initialize colorama + parser = argparse.ArgumentParser(description='Parse regression test output and append to a markdown file.') + parser.add_argument('-i', '--input', help='Input file containing regression test output', required=True) + parser.add_argument('-o', '--output', help='Output markdown file containing formatted file', default='regression_results.md') + args = parser.parse_args() + + with open(args.input, 'r') as input_file: + regression_output = input_file.read() + + passed_configs, failed_configs = parse_regression_output(regression_output) + write_to_markdown(passed_configs, failed_configs, args.output) + + print(f"Markdown file updated: {args.output}") + + write_new_markdown(passed_configs, failed_configs) + + print("New markdown file created") + diff --git a/bin/nightly_build/src/send_mail_html.sh b/bin/nightly_build/src/send_mail_html.sh new file mode 100755 index 000000000..5c3735a3a --- /dev/null +++ b/bin/nightly_build/src/send_mail_html.sh @@ -0,0 +1,79 @@ +current_date=$(date "+%Y-%m-%d") +email_address="thomas.kidd@okstate.edu" +#email_address="WALLY-REGRESSION@LISTSERV.OKSTATE.EDU" +subject="WALLY regression and coverage test report" +attachments="" +html_body="" +host_name=$(hostname) +os_info=$(lsb_release -a 2>/dev/null) +script_location=$WALLY/bin/nightly_build/ + +html_body="
+

System Information

+

Server Name: $host_name@okstate.edu

+

Operating System: $os_info

+

Script Origin: $script_location

+
+ +

Testing sending HTML content through mutt

" + +# Iterate through the files and concatenate their content to the body +for file in $WALLY/../build-results/builds/*/wally_*_"$current_date"*.md; do + attachments+=" -a $file" + + # Convert Markdown to HTML using pandoc + html_content=$(pandoc "$file") + + # add the file full path + # html_body+="

File: $file

" + # Append the HTML content to the body + html_body+="$html_content" +done +echo "Sending email" + +# Get server hostname and OS information +host_name=$(hostname) +os_info=$(uname -a) + +# Define HTML body content + +# Use mutt to send the email with HTML body +#mutt -e "my_hdr From:James Stine " -s "$subject" $attachments \ +mutt -e "my_hdr From:Thomas Kidd " -s "$subject" \ + -e "set content_type=text/html" -- $email_address < + + + + Nightly Build Results - $current_date + + + +

Test Results - $current_date

+ + $html_body + + +EOF +