diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 373e354e9..c52ee485c 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -116,7 +116,7 @@ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
 # Wally needs Verilator 5.0 or later.
 # Verilator needs to be built from scratch to get the latest version
 # apt-get install verilator installs version 4.028 as of 6/8/23
-sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g 
+sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g 
 sudo apt-get install -y libfl2  libfl-dev  # Ubuntu only (ignore if gives error)
 cd $RISCV
 git clone https://github.com/verilator/verilator   # Only first time
@@ -127,7 +127,7 @@ git pull         # Make sure git repository is up-to-date
 git checkout master      # Use development branch (e.g. recent bug fixes)
 autoconf         # Create ./configure script
 ./configure      # Configure and create Makefile
-make -j NUM_THREADS  # Build Verilator itself (if error, try just 'make')
+make -j ${NUM_THREADS}  # Build Verilator itself (if error, try just 'make')
 sudo make install
 
 # Sail (https://github.com/riscv/sail-riscv)
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index cd4d6ff27..6a360a836 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -296,6 +296,12 @@ write_file -format ddc -hierarchy -o $filename
 set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"]
 write_sdf $filename
 
+# Write SPEF file in case need more precision power exploration for TSMC28psyn
+if {$tech != "tsmc28psyn"} {
+    set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".spef"]
+    redirect $filename { write_parasitics }
+}
+
 # QoR
 set filename [format "%s%s"  $outputDir "/reports/qor.rep"]
 redirect $filename { report_qor }
diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index 761c49d35..2f5dedaca 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -145,11 +145,9 @@ module testbenchfp;
    
    initial begin
       // Information displayed for user on what is simulating
-      //$display("\nThe start of simulation...");      
-      //$display("This simulation for TEST is %s", TEST);
-      //$display("This simulation for TEST is of the operand size of %s", TEST_SIZE);      
-
-      // $display("FPDUR %d %d DIVN %d LOGR %d RK %d RADIX %d DURLEN %d", FPDUR, DIVN, LOGR, RK, RADIX, DURLEN);
+      // $display("\nThe start of simulation...");      
+      // $display("This simulation for TEST is %s", TEST);
+      // $display("This simulation for TEST is of the operand size of %s", TEST_SIZE);      
 
       if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
 	 if (TEST === "cvtint" | TEST === "all") begin  // if testing integer conversion
@@ -967,14 +965,6 @@ module testbenchfp;
 
       // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but 
       // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
-
-      // Note: Went through and determined that this is not needed with new module additions
-      // Just needs to check flags against TestFloat (left just in case (remove after check one more time)) 
-      // else if ((UnitVal === `CVTINTUNIT) & 
-      //       ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) | 
-      //		  (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) | 
-      //	  (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | 
-      //	  (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
       else if ((UnitVal === `CVTINTUNIT) & 
 		  ~((ResFlg === AnsFlg | AnsFlg === 5'bx))) begin	 
 	 errors += 1;
@@ -1034,7 +1024,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		    );
 
    localparam Q_LEN = 32'd128;
-  //`include "parameter-defs.vh"   
    
    logic 					XEn;
    logic 					YEn;
@@ -1113,7 +1102,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
           if (OpCtrl[0])
             case (Fmt)
               2'b11: begin // quad
-		 #20;		 
 		 X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
 		 Ans = TestVector[8+(P.Q_LEN-1):8];
 		 if (~clk) #5;
@@ -1121,7 +1109,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		   DivStart = 1'b0;
               end
               2'b01: if (P.D_SUPPORTED) begin // double
-		 #20;		 
 		 X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
 		 Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
 		 if (~clk) #5;
@@ -1129,7 +1116,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		   DivStart = 1'b0;
               end
               2'b00: if (P.S_SUPPORTED) begin // single
-		 #20;		 
 		 X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
 		 Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
 		 if (~clk) #5;
@@ -1137,7 +1123,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		   DivStart = 1'b0;
               end
               2'b10: begin // half
-		 #20;		 
 		 X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
 		 Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
 		 if (~clk) #5;
@@ -1148,7 +1133,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
           else
             case (Fmt)
               2'b11: begin // quad
-		 #20;		 
 		 X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
 		 Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
 		 Ans = TestVector[8+(P.Q_LEN-1):8];
@@ -1157,7 +1141,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		   DivStart = 1'b0;
               end
               2'b01: if (P.D_SUPPORTED) begin // double
-		 #20;		 
 		 X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
 		 Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
 		 Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
@@ -1166,7 +1149,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		   DivStart = 1'b0;
               end
               2'b00: if (P.S_SUPPORTED) begin // single
-		 #20;		 
 		 X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
 		 Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
 		 Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
@@ -1175,7 +1157,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		   DivStart = 1'b0;
               end
               2'b10: begin // half
-		 #20;		 
 		 X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
 		 Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
 		 Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
@@ -1403,11 +1384,11 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
    assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
    assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
    assign ZEn = (Unit == `FMAUNIT);
-   // Will fix with better activation - for now, this works (jes)
    assign FPUActive = 1'b1;
    
    unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
                       .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
                       .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
                       .XEn, .YEn, .ZEn, .XExpMax, .XPostBox);
+
 endmodule