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cleanup, dont update Prv in DCSR

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Matthew 2024-06-15 22:54:10 -05:00
parent 3a2e8ae3cc
commit d6256d1647
4 changed files with 4 additions and 7 deletions
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4
bin/hw_debug_test.py
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@ -1,7 +1,7 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
######################################################################################### #########################################################################################
# hw_test.py # hw_debug_test.py
# #
# Written: matthew.n.otto@okstate.edu # Written: matthew.n.otto@okstate.edu
# Created: 19 April 2024 # Created: 19 April 2024
@ -45,7 +45,7 @@ def flow_control_test():
cvw.read_data("DCSR") cvw.read_data("DCSR")
for _ in range(50): for _ in range(50):
cvw.step() cvw.step()
cvw.read_data("PCM") print(cvw.read_data("PCM"))
cvw.resume() cvw.resume()

3
src/privileged/csrd.sv
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@ -82,9 +82,6 @@ module csrd import cvw::*; #(parameter cvw_t P) (
end else if (EnterDebugMode) begin end else if (EnterDebugMode) begin
Prv <= PrivilegeModeW; Prv <= PrivilegeModeW;
Cause <= DebugCause; Cause <= DebugCause;
end else if (WriteDCSRM) begin
Prv <= CSRWriteValM[`PRV]; // TODO: overwrite hart privilege mode
end
end end
flopenr #(4) DCSRreg (clk, reset, WriteDCSRM, flopenr #(4) DCSRreg (clk, reset, WriteDCSRM,