From d6256d1647ecc16072976fc16af1921b6f405e9e Mon Sep 17 00:00:00 2001
From: Matthew <106996253+Matthew-Otto@users.noreply.github.com>
Date: Sat, 15 Jun 2024 22:54:10 -0500
Subject: [PATCH] cleanup, dont update Prv in DCSR

---
 bin/hw_debug_test.py       | 4 ++--
 bin/openocd_tcl_wrapper.py | 2 +-
 src/debug/dmc.sv           | 2 +-
 src/privileged/csrd.sv     | 3 ---
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/bin/hw_debug_test.py b/bin/hw_debug_test.py
index 4a108fdf8..78e69a8e3 100755
--- a/bin/hw_debug_test.py
+++ b/bin/hw_debug_test.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 #########################################################################################
-# hw_test.py
+# hw_debug_test.py
 #
 # Written: matthew.n.otto@okstate.edu
 # Created: 19 April 2024
@@ -45,7 +45,7 @@ def flow_control_test():
         cvw.read_data("DCSR")
         for _ in range(50):
             cvw.step()
-            cvw.read_data("PCM")
+            print(cvw.read_data("PCM"))
         cvw.resume()
 
 
diff --git a/bin/openocd_tcl_wrapper.py b/bin/openocd_tcl_wrapper.py
index fad2ae5e2..b7cc1862d 100644
--- a/bin/openocd_tcl_wrapper.py
+++ b/bin/openocd_tcl_wrapper.py
@@ -98,7 +98,7 @@ class OpenOCD:
         dmstat = int(self.read_dmi("0x10"), 16)
         if not dmstat & 0x1:
             raise Exception("Error: failed to activate debug module")
-  
+
     def reset_dm(self):
         self.write_dmi("0x10", "0x0")
         dmstat = int(self.read_dmi("0x10"), 16)
diff --git a/src/debug/dmc.sv b/src/debug/dmc.sv
index f944afe71..4b0ac8d16 100644
--- a/src/debug/dmc.sv
+++ b/src/debug/dmc.sv
@@ -50,7 +50,7 @@ module dmc (
 );
   `include "debug.vh"
 
-enum logic [1:0] {RUNNING, FLUSH, HALTED, RESUME} State;
+  enum logic [1:0] {RUNNING, FLUSH, HALTED, RESUME} State;
 
   localparam NOP_CYCLE_DURATION = 0;
   logic [$clog2(NOP_CYCLE_DURATION+1)-1:0] Counter;
diff --git a/src/privileged/csrd.sv b/src/privileged/csrd.sv
index 8382ff804..b2b137dde 100644
--- a/src/privileged/csrd.sv
+++ b/src/privileged/csrd.sv
@@ -82,9 +82,6 @@ module csrd import cvw::*;  #(parameter cvw_t P) (
     end else if (EnterDebugMode) begin
       Prv <= PrivilegeModeW;
       Cause <= DebugCause;
-    end else if (WriteDCSRM) begin
-      Prv <= CSRWriteValM[`PRV]; // TODO: overwrite hart privilege mode
-    end
   end
 
   flopenr #(4) DCSRreg (clk, reset, WriteDCSRM,