From 3bed733301cd02baa62c49a3bf8099591bc56309 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 22 Apr 2024 10:42:01 -0500 Subject: [PATCH 1/4] Fixed fpga to work with the updated regression changes. --- fpga/generator/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index e6807a6a6..df4ed0e2a 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -57,7 +57,8 @@ PreProcessFiles: # modify config *** RT: eventually setup for variably defined sized memory #sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # This line allows the Bootloader to be loaded in a Block RAM on the FPGA - sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv + sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv + sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv $(dst)/%.log: %.tcl mkdir -p IP From 81236958319f11498c24418f2bb24d8ea12950d6 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 22 Apr 2024 10:48:34 -0500 Subject: [PATCH 2/4] Maded insert_debug_comment.sh compatible with cygwin. --- fpga/generator/insert_debug_comment.sh | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh index b9f8c86f8..5f8e3fce1 100755 --- a/fpga/generator/insert_debug_comment.sh +++ b/fpga/generator/insert_debug_comment.sh @@ -4,7 +4,7 @@ ## ## Written: Rose Thompson ross1728@gmail.com ## Created: 20 January 2023 -## Modified: 16 April 2024 +## Modified: 22 April 2024 ## ## A component of the CORE-V-WALLY configurable RISC-V project. ## https://github.com/openhwgroup/cvw @@ -29,21 +29,12 @@ # Then it processes them to add mark_debug on signals needed by the FPGA's ILA. copiedDir="../src/CopiedFiles_do_not_add_to_repo" while read line; do - # older versions of bash are incompatible with readarray -d :( - #readarray -d ":" -t StrArray <<< "$line" - #file="${copiedDir}/${StrArray[0]}" - #signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` - fileName=`echo $line | cut -d ":" -f 1` - file=${copiedDir}/$fileName - signal=`echo $line | cut -d ":" -f 2` - echo $file - echo $signal + readarray -d ":" -t StrArray <<< "$line" + file="${copiedDir}/${StrArray[0]}" + signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` readarray -d " " -t SigArray <<< $signal - sigType=`echo $signal | cut -d " " -f 1` - sigType=`echo $sigType | awk '{$1=$1};1'` - sigName=`echo $signal | cut -d " " -f 2` - sigName=`echo $sigName | awk '{$1=$1};1'` - #sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'` - #sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'` - find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" + sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'` + sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1' | tr -d "\015"` + filepath=`find $copiedDir -wholename $file` + sed -i "s/\(.*${sigType}.*${sigName}.*\)/(\* mark_debug = \"true\" \*)\1/g" $filepath done < ../constraints/marked_debug.txt From d4fa95910aac6b3109e4075903a52d6e0b85c93a Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Mon, 22 Apr 2024 10:49:02 -0700 Subject: [PATCH 3/4] Add some helper targets. --- docs/docker/Makefile | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/docs/docker/Makefile b/docs/docker/Makefile index 5493555c9..82560d8cb 100644 --- a/docs/docker/Makefile +++ b/docs/docker/Makefile @@ -3,16 +3,30 @@ CVW_GIT?="" commanline: podman run -it --rm \ - -v cvw_temp:/home/cad/cvw \ - -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \ - --privileged --network=host \ - wallysoc/regression_wally /bin/bash + -v cvw_temp:/home/cad/cvw \ + -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \ + --privileged --network=host \ + wallysoc/regression_wally /bin/bash regression_openhw_cvw: podman run \ -e CVW_GIT=$(CVW_GIT) \ - -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \ - -v cvw_temp:/home/cad/cvw \ - -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \ - --privileged --network=host \ - --rm wallysoc/regression_wally \ No newline at end of file + -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \ + -v cvw_temp:/home/cad/cvw \ + -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \ + --privileged --network=host \ + --rm wallysoc/regression_wally + +push_hub: + podman push wallysoc/ubuntu_wally:latest + podman push wallysoc/toolchains_wally:latest + podman push wallysoc/regression_wally:latest + +update_ubuntu: + podman build -t wallysoc/ubuntu_wally -f Dockerfile.ubuntu . + +update_toolchains: + podman build -t wallysoc/toolchains_wally -f Dockerfile.builds . + +update_regression: + podman build -t wallysoc/regression_wally -f Dockerfile.regression . \ No newline at end of file From c383bef1ad61c30492be05fe67cc4517faef712c Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Mon, 22 Apr 2024 11:32:46 -0700 Subject: [PATCH 4/4] Run verilator configurations and testsuites in different folders. --- sim/verilator/Makefile | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 4042326a8..542b09d1c 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -3,8 +3,7 @@ OPT= PARAMS?=-DVERILATOR=1 --no-trace-top NONPROF?=--stats -WORKING_DIR=${WALLY}/sim/verilator -TARGET=$(WORKING_DIR)/target +VERILATOR_DIR=${WALLY}/sim/verilator SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv WALLYCONF?=rv64gc @@ -13,42 +12,41 @@ TEST?=arch64i default: run profile: obj_dir_profiling/Vtestbench_$(WALLYCONF) - $(WORKING_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) + $(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) mv gmon.out gmon_$(WALLYCONF).out - gprof $(WORKING_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log + gprof $(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log verilator_profcfunc gmon_$(WALLYCONF).log > gmon_$(WALLYCONF).log2 - mkdir -p $(WORKING_DIR)/logs_profiling - mv gmon_$(WALLYCONF)* $(WORKING_DIR)/logs_profiling - echo "Please check $(WORKING_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files." + mkdir -p $(VERILATOR_DIR)/logs_profiling + mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling + echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files." -run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF) - mkdir -p $(WORKING_DIR)/logs - time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log - echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files." +run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench + mkdir -p $(VERILATOR_DIR)/logs + wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST) 2>&1 > $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log + echo "Please check $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files." -obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) - mkdir -p obj_dir_non_profiling - time verilator \ - --Mdir obj_dir_non_profiling -o Vtestbench_$(WALLYCONF) \ - -cc --binary \ +wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(SOURCE) + verilator \ + --Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \ + --binary \ $(OPT) $(PARAMS) $(NONPROF) \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \ - wrapper.c \ + ${WALLY}/sim/verilator/wrapper.c \ ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) mkdir -p obj_dir_profiling - time verilator \ + verilator \ --Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \ - -cc --binary \ + --binary \ --prof-cfuncs $(OPT) $(PARAMS) \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ wrapper.c \ "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv questa: - time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" + vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" clean: - rm -rf $(WORKING_DIR)/obj_dir_non_profiling $(WORKING_DIR)/obj_dir_profiling $(WORKING_DIR)/logs $(WORKING_DIR)/logs_profiling \ No newline at end of file + rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling \ No newline at end of file