diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv
index 5c4395a12..50617d3c5 100644
--- a/src/ifu/decompress.sv
+++ b/src/ifu/decompress.sv
@@ -165,14 +165,14 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
                     else // if (instr16[6:5] == 2'b11) 
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
-                  else if (instr16[12:10] == 3'b111) begin
+                  else begin // (instr16[12:10] == 3'b111)
                     if (instr16[6:5] == 2'b00 & P.XLEN > 32)
                       InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
                     else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
                     else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) 
                       InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
-                    else if (instr16[6:2] == 5'b10101 & P.ZCB_SUPPORTED) 
+                    else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED) 
                       InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
                     else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED) 
                       InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011};  // c.zext.h
@@ -188,9 +188,9 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                       IllegalCompInstrD = 1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end
-                  end else begin // illegal instruction
+                  /** end else begin // illegal instruction
                     IllegalCompInstrD = 1;
-                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap **/
                   end
         5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
         5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S
index cc24b50b0..f387774bf 100644
--- a/tests/coverage/ifu.S
+++ b/tests/coverage/ifu.S
@@ -40,12 +40,40 @@ main:
     .hword 0x2002      // c.fldsp fs0, 0
     .hword 0xA002      // c.fsdsp fs0, 0
     .hword 0x9C41      // line 134 Illegal compressed instruction
+
+    # Zcb coverage tests
     # could restore assembly language versions when GCC supports Zcb
-#    c.lbu s1, 0(s0)    // exercise c.lbu
     mv s0, sp
+    #c.lbu s1, 0(s0)   // exercise c.lbu
     .hword 0x8004      // c.lbu s1, 0(s0)
+    #c.lh s1, 0(s0)    // exercise c.lh
+    .hword 0x8444      // c.lh s1, 0(s0)
+    #c.lhu s1, 0(s0)   // exercise c.lhu
+    .hword 0x8404      // c.lhu s1, 0(s0)
+    #c.sb s1, 0(s0)    // exercise c.sb
+    .hword 0x8804      // c.sb s1, 0(s0)
+    #c.sh s1, 0(s0)    // exercise c.sh
+    .hword 0x8C04      // c.sh s1, 0(s0)
+
+    .hword 0x8C44      // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
+    .hword 0x9C00      // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction
+
+    li s0, 0xFF
+    # c.zext.b s0      // exercise c.zext.b
+    .hword 0x9C61      // c.zext.b s0
+    # c.sext.b s0      // exercise c.sext.b
+    .hword 0x9C65      // c.sext.b s0
+    # c.zext.h s0      // exercise c.zext.h
+    .hword 0x9C69      // c.zext.h s0
+    # c.sext.h s0      // exercise c.sext.h
+    .hword 0x9C6D      // c.sext.h s0
+    # c.zext.w s0      // exercise c.zext.w
+    .hword 0x9C71      // c.zext.w s0
+    # c.not s0         // exercise c.not
+    .hword 0x9C75      // c.not s0
+    
+    .hword 0x9C7D      // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
     
-    //.hword 0x9C01     //# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else