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https://github.com/openhwgroup/cvw
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Merge pull request #604 from davidharrishmc/dev
Nightly lint runs more cases
This commit is contained in:
Rose Thompson
GitHub
commit
c56f2a20fc
@ -130,6 +130,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
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// Bus Interface width
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localparam AHBW = 32'd64;
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// AHB
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localparam RAM_LATENCY = 32'b0;
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localparam BURST_EN = 1;
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// Test modes
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// Tie GPIO outputs back to inputs
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@ -153,7 +157,7 @@ localparam BPRED_SIZE = 32'd10;
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localparam BPRED_NUM_LHR = 32'd6;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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localparam ICLASSPRED = 1;
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localparam INSTR_CLASS_PRED = 1;
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localparam SVADU_SUPPORTED = 1;
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localparam ZMMUL_SUPPORTED = 0;
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@ -294,73 +294,73 @@ deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc
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BTB_SIZE 16
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deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc
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ICLASSPRED 0
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INSTR_CLASS_PRED 0
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# Cache configurations
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@ -390,6 +390,10 @@ deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 4
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ICACHE_NUMWAYS 4
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deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 8
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ICACHE_NUMWAYS 8
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deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_WAYSIZEINBYTES 2048
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ICACHE_WAYSIZEINBYTES 2048
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@ -513,3 +517,35 @@ ZFH_SUPPORTED 0
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deriv fdqh_rv64gc rv64gc
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MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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ZFH_SUPPORTED 1
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# IEEE compatible variants for TestFloat
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deriv f_ieee_rv32gc rv32gc f_rv32gc
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IEEE754 1
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deriv fh_ieee_v32gc rv32gc fh_rv32gc
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IEEE754 1
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deriv fdh_ieee_rv32gc rv32gc fdh_rv32gc
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IEEE754 1
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deriv fdq_ieee_rv32gc rv32gc fdq_rv32gc
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IEEE754 1
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deriv fdqh_ieee_rv32gc rv32gc fdqh_rv32gc
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IEEE754 1
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deriv f_ieee_rv64gc rv64gc f_rv64gc
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IEEE754 1
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deriv fh_ieee_rv64gc rv64gc fh_rv64gc
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IEEE754 1
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deriv fd_ieee_rv64gc rv64gc fd_rv64gc
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IEEE754 1
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deriv fdq_ieee_rv64gc rv64gc fdq_rv64gc
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IEEE754 1
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deriv fdqh_ieee_rv64gc rv64gc fdqh_rv64gc
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IEEE754 1
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@ -133,7 +133,7 @@ localparam AHBW = 32'd32;
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// Test modes
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// AHB
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localparam RAM_LATENCY = 0;
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localparam RAM_LATENCY = 32'b0;
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localparam BURST_EN = 1;
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// Tie GPIO outputs back to inputs
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@ -158,7 +158,7 @@ localparam BPRED_SIZE = 32'd10;
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localparam BPRED_NUM_LHR = 32'd6;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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localparam ICLASSPRED = 0;
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localparam INSTR_CLASS_PRED = 0;
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localparam SVADU_SUPPORTED = 0;
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localparam ZMMUL_SUPPORTED = 0;
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@ -134,7 +134,7 @@ localparam AHBW = 32'd32;
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// Test modes
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// AHB
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localparam RAM_LATENCY = 0;
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localparam RAM_LATENCY = 32'b0;
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localparam BURST_EN = 1;
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// Tie GPIO outputs back to inputs
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@ -170,7 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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`endif
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localparam ICLASSPRED = 1;
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localparam INSTR_CLASS_PRED = 1;
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localparam SVADU_SUPPORTED = 1;
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localparam ZMMUL_SUPPORTED = 0;
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@ -133,7 +133,7 @@ localparam AHBW = 32'd32;
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// Test modes
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// AHB
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localparam RAM_LATENCY = 0;
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localparam RAM_LATENCY = 32'b0;
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localparam BURST_EN = 1;
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// Tie GPIO outputs back to inputs
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@ -159,7 +159,7 @@ localparam BPRED_SIZE = 32'd10;
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localparam BPRED_NUM_LHR = 32'd6;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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localparam ICLASSPRED = 0;
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localparam INSTR_CLASS_PRED = 0;
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localparam SVADU_SUPPORTED = 0;
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localparam ZMMUL_SUPPORTED = 0;
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@ -132,7 +132,7 @@ localparam AHBW = 32'd32;
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// Test modes
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// AHB
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localparam RAM_LATENCY = 0;
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localparam RAM_LATENCY = 32'b0;
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localparam BURST_EN = 1;
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// Tie GPIO outputs back to inputs
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@ -157,7 +157,7 @@ localparam BPRED_SIZE = 32'd10;
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localparam BPRED_NUM_LHR = 32'd6;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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localparam ICLASSPRED = 0;
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localparam INSTR_CLASS_PRED = 0;
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localparam SVADU_SUPPORTED = 0;
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localparam ZMMUL_SUPPORTED = 0;
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@ -1,187 +0,0 @@
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//////////////////////////////////////////
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// config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "BranchPredictorType.vh"
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// RV32 or RV64: XLEN = 32 or 64
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localparam XLEN = 32'd64;
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// IEEE 754 compliance
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localparam IEEE754 = 1;
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// MISA RISC-V configuration per specification
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localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
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localparam ZICSR_SUPPORTED = 1;
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localparam ZIFENCEI_SUPPORTED = 1;
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localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 1;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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localparam ZICBOP_SUPPORTED = 0;
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localparam ZICCLSM_SUPPORTED = 0;
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localparam ZICOND_SUPPORTED = 0;
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localparam SVPBMT_SUPPORTED = 0;
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localparam SVNAPOT_SUPPORTED = 0;
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localparam SVINVAL_SUPPORTED = 1;
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// LSU microarchitectural Features
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localparam BUS_SUPPORTED = 1;
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localparam DCACHE_SUPPORTED = 1;
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localparam ICACHE_SUPPORTED = 1;
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localparam VIRTMEM_SUPPORTED = 1;
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localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ;
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localparam BIGENDIAN_SUPPORTED = 1;
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// TLB configuration. Entries should be a power of 2
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localparam ITLB_ENTRIES = 32'd32;
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localparam DTLB_ENTRIES = 32'd32;
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
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localparam DCACHE_NUMWAYS = 32'd4;
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localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
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localparam DCACHE_LINELENINBITS = 32'd512;
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localparam ICACHE_NUMWAYS = 32'd4;
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localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
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localparam ICACHE_LINELENINBITS = 32'd512;
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localparam CACHE_SRAMLEN = 32'd128;
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// Integer Divider Configuration
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// IDIV_BITSPERCYCLE must be 1, 2, or 4
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localparam IDIV_BITSPERCYCLE = 32'd4;
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localparam IDIV_ON_FPU = 1;
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// Legal number of PMP entries are 0, 16, or 64
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localparam PMP_ENTRIES = 32'd16;
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// Address space
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localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
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// Bus Interface width
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localparam AHBW = 32'd64;
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// WFI Timeout Wait
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localparam WFI_TIMEOUT_BIT = 32'd16;
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// Peripheral Physiccal Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
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localparam DTIM_SUPPORTED = 1'b0;
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localparam logic [63:0] DTIM_BASE = 64'h80000000;
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localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
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localparam IROM_SUPPORTED = 1'b0;
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localparam logic [63:0] IROM_BASE = 64'h80000000;
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localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
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localparam BOOTROM_SUPPORTED = 1'b1;
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localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
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localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
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localparam BOOTROM_PRELOAD = 1'b0;
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localparam UNCORE_RAM_SUPPORTED = 1'b1;
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localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
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localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
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localparam UNCORE_RAM_PRELOAD = 1'b0;
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localparam EXT_MEM_SUPPORTED = 1'b0;
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localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
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localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
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localparam CLINT_SUPPORTED = 1'b1;
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localparam logic [63:0] CLINT_BASE = 64'h02000000;
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localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
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localparam GPIO_SUPPORTED = 1'b1;
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localparam logic [63:0] GPIO_BASE = 64'h10060000;
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localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
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localparam UART_SUPPORTED = 1'b1;
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localparam logic [63:0] UART_BASE = 64'h10000000;
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localparam logic [63:0] UART_RANGE = 64'h00000007;
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localparam PLIC_SUPPORTED = 1'b1;
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localparam logic [63:0] PLIC_BASE = 64'h0C000000;
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localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
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localparam SDC_SUPPORTED = 1'b0;
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localparam logic [63:0] SDC_BASE = 64'h00013000;
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localparam logic [63:0] SDC_RANGE = 64'h0000007F;
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localparam SPI_SUPPORTED = 1'b1;
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localparam logic [63:0] SPI_BASE = 64'h10040000;
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localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
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// Test modes
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// AHB
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localparam RAM_LATENCY = 0;
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localparam BURST_EN = 1;
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// Tie GPIO outputs back to inputs
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localparam GPIO_LOOPBACK_TEST = 1;
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localparam SPI_LOOPBACK_TEST = 1;
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// Hardware configuration
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localparam UART_PRESCALE = 32'd1;
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// Interrupt configuration
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localparam PLIC_NUM_SRC = 32'd10;
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// comment out the following if >=32 sources
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localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
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localparam PLIC_GPIO_ID = 32'd3;
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localparam PLIC_UART_ID = 32'd10;
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localparam PLIC_SPI_ID = 32'd6;
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localparam PLIC_SDC_ID = 32'd9;
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localparam BPRED_SUPPORTED = 1;
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localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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localparam BPRED_SIZE = 32'd10;
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localparam BPRED_NUM_LHR = 32'd6;
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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localparam ICLASSPRED = 1;
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localparam SVADU_SUPPORTED = 0;
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localparam ZMMUL_SUPPORTED = 0;
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// FPU division architecture
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localparam RADIX = 32'h4;
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localparam DIVCOPIES = 32'h4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 0;
|
||||
localparam ZBB_SUPPORTED = 0;
|
||||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 0;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "config-shared.vh"
|
||||
@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam RAM_LATENCY = 32'b0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
@ -160,7 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
localparam ICLASSPRED = 1;
|
||||
localparam INSTR_CLASS_PRED = 1;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||
// Test modes
|
||||
|
||||
// AHB
|
||||
localparam RAM_LATENCY = 0;
|
||||
localparam RAM_LATENCY = 32'b0;
|
||||
localparam BURST_EN = 1;
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
@ -160,7 +160,7 @@ localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
localparam ICLASSPRED = 0;
|
||||
localparam INSTR_CLASS_PRED = 0;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -8,6 +8,8 @@ localparam cvw_t P = '{
|
||||
IEEE754 : IEEE754,
|
||||
MISA : MISA,
|
||||
AHBW : AHBW,
|
||||
RAM_LATENCY : RAM_LATENCY,
|
||||
BURST_EN : BURST_EN,
|
||||
ZICSR_SUPPORTED : ZICSR_SUPPORTED,
|
||||
ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED,
|
||||
COUNTERS : COUNTERS,
|
||||
|
||||
@ -9,4 +9,4 @@
|
||||
# sqrt - test square root
|
||||
# all - test everything
|
||||
|
||||
vsim -do "do testfloat.do rv64fpquad $1"
|
||||
vsim -do "do testfloat.do fdqh_ieee_rv64gc $1"
|
||||
|
||||
@ -10,4 +10,4 @@
|
||||
# sqrt - test square root
|
||||
# all - test everything
|
||||
|
||||
vsim -c -do "do testfloat.do rv64fpquad $1"
|
||||
vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
|
||||
|
||||
@ -25,7 +25,7 @@ vlib work
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
# $num = the added words after the call
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
|
||||
vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
|
||||
|
||||
# Change TEST_SIZE to only test certain FP width
|
||||
# values are QP, DP, SP, HP or all for all tests
|
||||
|
||||
@ -41,6 +41,8 @@ typedef struct packed {
|
||||
logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead)
|
||||
int MISA; // Machine Instruction Set Architecture
|
||||
int AHBW; // AHB bus width (usually = XLEN)
|
||||
int RAM_LATENCY; // Latency to stress AHB
|
||||
logic BURST_EN; // Support AHB Burst Mode
|
||||
|
||||
// RISC-V Features
|
||||
logic ZICSR_SUPPORTED;
|
||||
|
||||
@ -28,10 +28,8 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ahbcacheinterface #(
|
||||
parameter AHBW,
|
||||
parameter LLEN,
|
||||
parameter PA_BITS,
|
||||
module ahbcacheinterface import cvw::*; #(
|
||||
parameter cvw_t P,
|
||||
parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
|
||||
parameter AHBWLOGBWPL, // Log2 of ^
|
||||
parameter LINELEN, // Number of bits in cacheline
|
||||
@ -46,14 +44,14 @@ module ahbcacheinterface #(
|
||||
output logic [2:0] HSIZE, // AHB transaction width
|
||||
output logic [2:0] HBURST, // AHB burst length
|
||||
// bus interface buses
|
||||
input logic [AHBW-1:0] HRDATA, // AHB read data
|
||||
output logic [PA_BITS-1:0] HADDR, // AHB address
|
||||
output logic [AHBW-1:0] HWDATA, // AHB write data
|
||||
output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask
|
||||
input logic [P.AHBW-1:0] HRDATA, // AHB read data
|
||||
output logic [P.PA_BITS-1:0] HADDR, // AHB address
|
||||
output logic [P.AHBW-1:0] HWDATA, // AHB write data
|
||||
output logic [P.AHBW/8-1:0] HWSTRB, // AHB byte mask
|
||||
|
||||
// cache interface
|
||||
input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line
|
||||
input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
|
||||
input logic [P.PA_BITS-1:0] CacheBusAdr, // Address of cache line
|
||||
input logic [P.LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
|
||||
input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
|
||||
input logic Cacheable, // Memory operation is cachable
|
||||
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
|
||||
@ -63,8 +61,8 @@ module ahbcacheinterface #(
|
||||
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
|
||||
|
||||
// uncached interface
|
||||
input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
|
||||
input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store
|
||||
input logic [P.PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
|
||||
input logic [P.LLEN-1:0] WriteDataM, // IEU write data for uncached store
|
||||
input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
|
||||
input logic BusAtomic, // Uncache atomic memory operation
|
||||
input logic [2:0] Funct3, // Size of uncached memory operation
|
||||
@ -78,12 +76,12 @@ module ahbcacheinterface #(
|
||||
|
||||
|
||||
localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
|
||||
logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
|
||||
logic [P.PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
|
||||
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
|
||||
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
|
||||
logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
|
||||
logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data
|
||||
logic [PA_BITS-1:0] PAdrZero;
|
||||
logic [P.AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
|
||||
logic [P.AHBW-1:0] PreHWDATA; // AHB Address phase write data
|
||||
logic [P.PA_BITS-1:0] PAdrZero;
|
||||
|
||||
genvar index;
|
||||
|
||||
@ -91,38 +89,38 @@ module ahbcacheinterface #(
|
||||
for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
|
||||
logic [BEATSPERLINE-1:0] CaptureBeat;
|
||||
assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
|
||||
flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
|
||||
.q(FetchBuffer[(index+1)*AHBW-1:index*AHBW]));
|
||||
flopen #(P.AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
|
||||
.q(FetchBuffer[(index+1)*P.AHBW-1:index*P.AHBW]));
|
||||
end
|
||||
|
||||
assign PAdrZero = BusCMOZero ? {PAdr[PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr;
|
||||
mux2 #(PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR);
|
||||
assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR;
|
||||
assign PAdrZero = BusCMOZero ? {PAdr[P.PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr;
|
||||
mux2 #(P.PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR);
|
||||
assign HADDR = ({{P.PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(P.AHBW/8)) + LocalHADDR;
|
||||
|
||||
mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE));
|
||||
mux2 #(3) sizemux(.d0(Funct3), .d1(P.AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE));
|
||||
|
||||
// When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
|
||||
logic [AHBW-1:0] CacheReadDataWordAHB;
|
||||
logic [P.AHBW-1:0] CacheReadDataWordAHB;
|
||||
if(LLENPOVERAHBW > 1) begin
|
||||
logic [AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
|
||||
logic [P.AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
|
||||
genvar index;
|
||||
for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
|
||||
assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)];
|
||||
assign AHBWordSets[index] = CacheReadDataWordM[(index*P.AHBW)+P.AHBW-1: (index*P.AHBW)];
|
||||
end
|
||||
assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
|
||||
end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0];
|
||||
end else assign CacheReadDataWordAHB = CacheReadDataWordM[P.AHBW-1:0];
|
||||
|
||||
mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]),
|
||||
mux2 #(P.AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[P.AHBW-1:0]),
|
||||
.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
|
||||
flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
|
||||
flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
|
||||
|
||||
// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
|
||||
// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
|
||||
swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
|
||||
swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
|
||||
|
||||
flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB);
|
||||
flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB);
|
||||
|
||||
buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
|
||||
buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm(
|
||||
.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
|
||||
.CacheBusRW, .BusCMOZero, .CacheBusAck, .BeatCount, .BeatCountDelayed,
|
||||
.HREADY, .HTRANS, .HWRITE, .HBURST);
|
||||
|
||||
@ -28,13 +28,12 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance.
|
||||
|
||||
// HCLK and clk must be the same clock!
|
||||
module buscachefsm #(
|
||||
parameter BeatCountThreshold, // Largest beat index
|
||||
parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE
|
||||
parameter READ_ONLY_CACHE
|
||||
parameter READ_ONLY_CACHE, // 1 for read-only instruction cache
|
||||
parameter BURST_EN // burst mode supported
|
||||
)(
|
||||
input logic HCLK,
|
||||
input logic HRESETn,
|
||||
@ -142,11 +141,11 @@ module buscachefsm #(
|
||||
assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) |
|
||||
(CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) |
|
||||
(CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request
|
||||
(CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
|
||||
(CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
|
||||
|
||||
assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) |
|
||||
(CurrState == CACHE_WRITEBACK & |BeatCount);
|
||||
assign HBURST = `BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;
|
||||
assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;
|
||||
|
||||
always_comb begin
|
||||
case(BeatCountThreshold)
|
||||
|
||||
@ -32,31 +32,31 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ebu #(parameter XLEN, PA_BITS, AHBW)(
|
||||
module ebu import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk, reset,
|
||||
// Signals from IFU
|
||||
input logic [1:0] IFUHTRANS, // IFU AHB transaction request
|
||||
input logic [2:0] IFUHSIZE, // IFU AHB transaction size
|
||||
input logic [2:0] IFUHBURST, // IFU AHB burst length
|
||||
input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address
|
||||
input logic [P.PA_BITS-1:0] IFUHADDR, // IFU AHB address
|
||||
output logic IFUHREADY, // AHB peripheral ready gated by possible non-grant
|
||||
// Signals from LSU
|
||||
input logic [1:0] LSUHTRANS, // LSU AHB transaction request
|
||||
input logic LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read
|
||||
input logic [2:0] LSUHSIZE, // LSU AHB size
|
||||
input logic [2:0] LSUHBURST, // LSU AHB burst length
|
||||
input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address
|
||||
input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
|
||||
input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask
|
||||
input logic [P.PA_BITS-1:0] LSUHADDR, // LSU AHB address
|
||||
input logic [P.XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
|
||||
input logic [P.XLEN/8-1:0] LSUHWSTRB, // AHB byte mask
|
||||
output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
|
||||
|
||||
// AHB-Lite external signals
|
||||
output logic HCLK, HRESETn,
|
||||
input logic HREADY, // AHB peripheral ready
|
||||
input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored.
|
||||
output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
|
||||
output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration
|
||||
output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
|
||||
output logic [P.PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
|
||||
output logic [P.AHBW-1:0] HWDATA, // AHB Write data after arbitration
|
||||
output logic [P.XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
|
||||
output logic HWRITE, // AHB transaction direction after arbitration
|
||||
output logic [2:0] HSIZE, // AHB transaction size after arbitration
|
||||
output logic [2:0] HBURST, // AHB burst length after arbitration
|
||||
@ -72,13 +72,13 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)(
|
||||
logic IFUDisable;
|
||||
logic IFUSelect;
|
||||
|
||||
logic [PA_BITS-1:0] IFUHADDROut;
|
||||
logic [P.PA_BITS-1:0] IFUHADDROut;
|
||||
logic [1:0] IFUHTRANSOut;
|
||||
logic [2:0] IFUHBURSTOut;
|
||||
logic [2:0] IFUHSIZEOut;
|
||||
logic IFUHWRITEOut;
|
||||
|
||||
logic [PA_BITS-1:0] LSUHADDROut;
|
||||
logic [P.PA_BITS-1:0] LSUHADDROut;
|
||||
logic [1:0] LSUHTRANSOut;
|
||||
logic [2:0] LSUHBURSTOut;
|
||||
logic [2:0] LSUHSIZEOut;
|
||||
@ -97,14 +97,14 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)(
|
||||
// input stages and muxing for IFU and LSU
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
|
||||
controllerinput #(P.PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
|
||||
.Request(IFUReq),
|
||||
.HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR),
|
||||
.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
|
||||
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY));
|
||||
|
||||
// LSU always has priority so there should never be a need to save and restore the address phase inputs.
|
||||
controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
|
||||
controllerinput #(P.PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
|
||||
.Request(LSUReq),
|
||||
.HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY),
|
||||
.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
|
||||
|
||||
@ -255,7 +255,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
||||
.PAdr(PCPF),
|
||||
.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0));
|
||||
|
||||
ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1)
|
||||
ahbcacheinterface #(P, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1)
|
||||
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
|
||||
.HRDATA,
|
||||
.Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
|
||||
|
||||
@ -346,7 +346,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
||||
assign DCacheStallM = CacheStall & ~IgnoreRequestTLB;
|
||||
assign CacheBusRW = CacheBusRWTemp;
|
||||
|
||||
ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
|
||||
ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
|
||||
.HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB),
|
||||
.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
|
||||
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
|
||||
|
||||
@ -27,8 +27,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`define RAM_LATENCY 0
|
||||
|
||||
module ram_ahb import cvw::*; #(parameter cvw_t P,
|
||||
parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
|
||||
input logic HCLK, HRESETn,
|
||||
@ -76,7 +74,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
|
||||
.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
|
||||
|
||||
// use this to add arbitrary latency to ram. Helps test AHB controller correctness
|
||||
if(`RAM_LATENCY > 0) begin
|
||||
if(P.RAM_LATENCY > 0) begin
|
||||
logic [7:0] NextCycle, Cycle;
|
||||
logic CntEn, CntRst;
|
||||
logic CycleFlag;
|
||||
@ -101,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
|
||||
endcase
|
||||
end
|
||||
|
||||
assign CycleFlag = Cycle == `RAM_LATENCY;
|
||||
assign CycleFlag = Cycle == P.RAM_LATENCY;
|
||||
assign CntEn = NextState == DELAY;
|
||||
assign DelayReady = NextState == DELAY;
|
||||
assign CntRst = NextState == READY;
|
||||
|
||||
@ -252,7 +252,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
.LSUStallM);
|
||||
|
||||
if(P.BUS_SUPPORTED) begin : ebu
|
||||
ebu #(P.XLEN, P.PA_BITS, P.AHBW) ebu(// IFU connections
|
||||
ebu #(P) ebu(// IFU connections
|
||||
.clk, .reset,
|
||||
// IFU interface
|
||||
.IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE,
|
||||
|
||||
@ -35,6 +35,8 @@ module testbenchfp;
|
||||
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
parameter MAXVECTORS = 8388610;
|
||||
|
||||
// FIXME: needs cleaning of unused variables (jes)
|
||||
string Tests[]; // list of tests to be run
|
||||
logic [2:0] OpCtrl[]; // list of op controls
|
||||
@ -49,7 +51,7 @@ module testbenchfp;
|
||||
logic [31:0] errors=0; // how many errors
|
||||
logic [31:0] VectorNum=0; // index for test vector
|
||||
logic [31:0] FrmNum=0; // index for rounding mode
|
||||
logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors
|
||||
logic [P.FLEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors
|
||||
|
||||
logic [1:0] FmtVal; // value of the current Fmt
|
||||
logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
|
||||
@ -975,7 +977,7 @@ module testbenchfp;
|
||||
// increment the test
|
||||
TestNum += 1;
|
||||
// clear the vectors
|
||||
for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}};
|
||||
for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}};
|
||||
// read next files
|
||||
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
|
||||
// set the vector index back to 0
|
||||
|
||||
@ -36,11 +36,13 @@ rv32i_sc_tests = \
|
||||
WALLY-lrsc-01 \
|
||||
WALLY-status-mie-01 \
|
||||
WALLY-trap-sret-01 \
|
||||
|
||||
WALLY-status-fp-enabled-01 \
|
||||
WALLY-minfo-01 \
|
||||
WALLY-cboz-01 \
|
||||
WALLY-cbom-01 \
|
||||
|
||||
target_tests_nosim = \
|
||||
WALLY-pma-01 \
|
||||
WALLY-minfo-01 \
|
||||
WALLY-mtvec-01 \
|
||||
WALLY-stvec-01 \
|
||||
WALLY-mie-01 \
|
||||
@ -49,7 +51,6 @@ target_tests_nosim = \
|
||||
WALLY-trap-s-01 \
|
||||
WALLY-trap-u-01 \
|
||||
WALLY-wfi-01 \
|
||||
WALLY-status-fp-enabled-01 \
|
||||
WALLY-status-sie-01 \
|
||||
WALLY-status-tw-01 \
|
||||
WALLY-gpio-01 \
|
||||
@ -57,8 +58,6 @@ target_tests_nosim = \
|
||||
WALLY-plic-01 \
|
||||
WALLY-uart-01 \
|
||||
WALLY-spi-01 \
|
||||
WALLY-cbom-01 \
|
||||
WALLY-cboz-01 \
|
||||
|
||||
|
||||
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
|
||||
|
||||
@ -39,12 +39,16 @@ rv64i_sc_tests = \
|
||||
WALLY-status-mie-01 \
|
||||
WALLY-status-sie-01 \
|
||||
WALLY-status-tw-01 \
|
||||
WALLY-status-fp-enabled-01 \
|
||||
WALLY-misaligned-access-01 \
|
||||
WALLY-minfo-01 \
|
||||
WALLY-cboz-01 \
|
||||
WALLY-cbom-01 \
|
||||
|
||||
|
||||
# Don't simulate these because they rely on SoC features that Spike does not offer.
|
||||
target_tests_nosim = \
|
||||
WALLY-pma-01 \
|
||||
WALLY-minfo-01 \
|
||||
WALLY-periph-01 \
|
||||
WALLY-mtvec-01 \
|
||||
WALLY-stvec-01 \
|
||||
@ -53,14 +57,10 @@ target_tests_nosim = \
|
||||
WALLY-trap-01 \
|
||||
WALLY-trap-s-01 \
|
||||
WALLY-trap-u-01 \
|
||||
WALLY-status-fp-enabled-01 \
|
||||
WALLY-spi-01 \
|
||||
WALLY-gpio-01 \
|
||||
WALLY-uart-01 \
|
||||
WALLY-wfi-01 \
|
||||
WALLY-cbom-01 \
|
||||
WALLY-cboz-01 \
|
||||
WALLY-misaligned-access-01 \
|
||||
|
||||
|
||||
# unclear why status-fp-enabled and wfi aren't simulating ok
|
||||
|
||||
Loading…
Reference in New Issue
Block a user