From f37c7bb1f63c873fc23f6d4aa433f5b825bd4f23 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 30 Jan 2024 06:27:18 -0800 Subject: [PATCH 1/4] Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this --- config/buildroot/config.vh | 4 +++ config/rv32e/config.vh | 2 +- config/rv32gc/config.vh | 2 +- config/rv32i/config.vh | 2 +- config/rv32imc/config.vh | 2 +- config/rv64fpquad/config.vh | 2 +- config/rv64gc/config.vh | 2 +- config/rv64i/config.vh | 2 +- config/shared/parameter-defs.vh | 2 ++ src/cvw.sv | 2 ++ src/ebu/ahbcacheinterface.sv | 60 ++++++++++++++++----------------- src/ebu/buscachefsm.sv | 9 +++-- src/ebu/ebu.sv | 24 ++++++------- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- src/uncore/ram_ahb.sv | 6 ++-- src/wally/wallypipelinedcore.sv | 2 +- 17 files changed, 65 insertions(+), 62 deletions(-) diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index d334ab373..2730a9706 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -130,6 +130,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Bus Interface width localparam AHBW = 32'd64; +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Test modes // Tie GPIO outputs back to inputs diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 9abf11bf7..60153fdd2 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -133,7 +133,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 9a1ca7fea..eb021ab0e 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -134,7 +134,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index a6ebe0985..fe2aa9e51 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -133,7 +133,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 5d8a3690b..3714f0749 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -132,7 +132,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 9a3416524..941e11382 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index fa397471b..c4e54e346 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 9061da2a5..3067e9eab 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 7dc0a0bcf..bf4c11198 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -8,6 +8,8 @@ localparam cvw_t P = '{ IEEE754 : IEEE754, MISA : MISA, AHBW : AHBW, + RAM_LATENCY : RAM_LATENCY, + BURST_EN : BURST_EN, ZICSR_SUPPORTED : ZICSR_SUPPORTED, ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED, COUNTERS : COUNTERS, diff --git a/src/cvw.sv b/src/cvw.sv index a9ee9d093..c9d737d8f 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -41,6 +41,8 @@ typedef struct packed { logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead) int MISA; // Machine Instruction Set Architecture int AHBW; // AHB bus width (usually = XLEN) + int RAM_LATENCY; // Latency to stress AHB + logic BURST_EN; // Support AHB Burst Mode // RISC-V Features logic ZICSR_SUPPORTED; diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 89135966e..f033b40cc 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -28,10 +28,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ahbcacheinterface #( - parameter AHBW, - parameter LLEN, - parameter PA_BITS, +module ahbcacheinterface import cvw::*; #( + parameter cvw_t P, parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter AHBWLOGBWPL, // Log2 of ^ parameter LINELEN, // Number of bits in cacheline @@ -46,14 +44,14 @@ module ahbcacheinterface #( output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HBURST, // AHB burst length // bus interface buses - input logic [AHBW-1:0] HRDATA, // AHB read data - output logic [PA_BITS-1:0] HADDR, // AHB address - output logic [AHBW-1:0] HWDATA, // AHB write data - output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask + input logic [P.AHBW-1:0] HRDATA, // AHB read data + output logic [P.PA_BITS-1:0] HADDR, // AHB address + output logic [P.AHBW-1:0] HWDATA, // AHB write data + output logic [P.AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line - input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback + input logic [P.PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [P.LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic Cacheable, // Memory operation is cachable input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch @@ -63,8 +61,8 @@ module ahbcacheinterface #( output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface - input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation - input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store + input logic [P.PA_BITS-1:0] PAdr, // Physical address of uncached memory operation + input logic [P.LLEN-1:0] WriteDataM, // IEU write data for uncached store input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic BusAtomic, // Uncache atomic memory operation input logic [2:0] Funct3, // Size of uncached memory operation @@ -78,12 +76,12 @@ module ahbcacheinterface #( localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index - logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation + logic [P.PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s - logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data - logic [PA_BITS-1:0] PAdrZero; + logic [P.AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [P.AHBW-1:0] PreHWDATA; // AHB Address phase write data + logic [P.PA_BITS-1:0] PAdrZero; genvar index; @@ -91,38 +89,38 @@ module ahbcacheinterface #( for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer logic [BEATSPERLINE-1:0] CaptureBeat; assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); - flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), - .q(FetchBuffer[(index+1)*AHBW-1:index*AHBW])); + flopen #(P.AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*P.AHBW-1:index*P.AHBW])); end - assign PAdrZero = BusCMOZero ? {PAdr[PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; - mux2 #(PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR; + assign PAdrZero = BusCMOZero ? {PAdr[P.PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; + mux2 #(P.PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); + assign HADDR = ({{P.PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(P.AHBW/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); + mux2 #(3) sizemux(.d0(Funct3), .d1(P.AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. - logic [AHBW-1:0] CacheReadDataWordAHB; + logic [P.AHBW-1:0] CacheReadDataWordAHB; if(LLENPOVERAHBW > 1) begin - logic [AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; + logic [P.AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; genvar index; for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)]; + assign AHBWordSets[index] = CacheReadDataWordM[(index*P.AHBW)+P.AHBW-1: (index*P.AHBW)]; end assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; - end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0]; + end else assign CacheReadDataWordAHB = CacheReadDataWordM[P.AHBW-1:0]; - mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]), + mux2 #(P.AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[P.AHBW-1:0]), .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); - flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec + flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); + swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); - flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB); + flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); - buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( + buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .BusCMOZero, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index e9dadb515..75f444e4b 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -28,13 +28,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance. - // HCLK and clk must be the same clock! module buscachefsm #( parameter BeatCountThreshold, // Largest beat index parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE - parameter READ_ONLY_CACHE + parameter READ_ONLY_CACHE, // 1 for read-only instruction cache + parameter BURST_EN // burst mode supported )( input logic HCLK, input logic HRESETn, @@ -142,11 +141,11 @@ module buscachefsm #( assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request - (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; + (CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | (CurrState == CACHE_WRITEBACK & |BeatCount); - assign HBURST = `BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; + assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; always_comb begin case(BeatCountThreshold) diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index d9a95fc3d..b91eb75b0 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -32,31 +32,31 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ebu #(parameter XLEN, PA_BITS, AHBW)( +module ebu import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Signals from IFU input logic [1:0] IFUHTRANS, // IFU AHB transaction request input logic [2:0] IFUHSIZE, // IFU AHB transaction size input logic [2:0] IFUHBURST, // IFU AHB burst length - input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address + input logic [P.PA_BITS-1:0] IFUHADDR, // IFU AHB address output logic IFUHREADY, // AHB peripheral ready gated by possible non-grant // Signals from LSU input logic [1:0] LSUHTRANS, // LSU AHB transaction request input logic LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read input logic [2:0] LSUHSIZE, // LSU AHB size input logic [2:0] LSUHBURST, // LSU AHB burst length - input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address - input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN - input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask + input logic [P.PA_BITS-1:0] LSUHADDR, // LSU AHB address + input logic [P.XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN + input logic [P.XLEN/8-1:0] LSUHWSTRB, // AHB byte mask output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals output logic HCLK, HRESETn, input logic HREADY, // AHB peripheral ready input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored. - output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration - output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic [P.PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [P.AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [P.XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration output logic HWRITE, // AHB transaction direction after arbitration output logic [2:0] HSIZE, // AHB transaction size after arbitration output logic [2:0] HBURST, // AHB burst length after arbitration @@ -72,13 +72,13 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( logic IFUDisable; logic IFUSelect; - logic [PA_BITS-1:0] IFUHADDROut; + logic [P.PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; logic [2:0] IFUHBURSTOut; logic [2:0] IFUHSIZEOut; logic IFUHWRITEOut; - logic [PA_BITS-1:0] LSUHADDROut; + logic [P.PA_BITS-1:0] LSUHADDROut; logic [1:0] LSUHTRANSOut; logic [2:0] LSUHBURSTOut; logic [2:0] LSUHSIZEOut; @@ -97,14 +97,14 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( // input stages and muxing for IFU and LSU //////////////////////////////////////////////////////////////////////////////////////////////////// - controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), + controllerinput #(P.PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), .Request(IFUReq), .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY)); // LSU always has priority so there should never be a need to save and restore the address phase inputs. - controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), + controllerinput #(P.PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), .Request(LSUReq), .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index be2595ea6..4848b5ebb 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -255,7 +255,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0)); - ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) + ahbcacheinterface #(P, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index ca4e14f53..c997d58ff 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -346,7 +346,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; assign CacheBusRW = CacheBusRWTemp; - ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( + ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 0b15504c9..e14728513 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define RAM_LATENCY 0 - module ram_ahb import cvw::*; #(parameter cvw_t P, parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, @@ -76,7 +74,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); // use this to add arbitrary latency to ram. Helps test AHB controller correctness - if(`RAM_LATENCY > 0) begin + if(P.RAM_LATENCY > 0) begin logic [7:0] NextCycle, Cycle; logic CntEn, CntRst; logic CycleFlag; @@ -101,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, endcase end - assign CycleFlag = Cycle == `RAM_LATENCY; + assign CycleFlag = Cycle == P.RAM_LATENCY; assign CntEn = NextState == DELAY; assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY; diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index c0d08dd8c..ec0679f13 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -252,7 +252,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .LSUStallM); if(P.BUS_SUPPORTED) begin : ebu - ebu #(P.XLEN, P.PA_BITS, P.AHBW) ebu(// IFU connections + ebu #(P) ebu(// IFU connections .clk, .reset, // IFU interface .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE, From bf7e20e84650105fb3b6311273465c1d0ba52e54 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 30 Jan 2024 09:49:27 -0800 Subject: [PATCH 2/4] IEEE754 derivatives for testfloat --- config/buildroot/config.vh | 2 +- config/derivlist.txt | 82 ++++++++++++++++++++++++++----------- config/rv32e/config.vh | 2 +- config/rv32gc/config.vh | 2 +- config/rv32i/config.vh | 2 +- config/rv32imc/config.vh | 2 +- config/rv64fpquad/config.vh | 2 +- config/rv64gc/config.vh | 2 +- config/rv64i/config.vh | 2 +- sim/sim-testfloat | 2 +- sim/sim-testfloat-batch | 2 +- sim/testfloat.do | 2 +- testbench/testbench-fp.sv | 6 ++- 13 files changed, 74 insertions(+), 36 deletions(-) diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index 2730a9706..6629af297 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -157,7 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/derivlist.txt b/config/derivlist.txt index 8b6eaf1d8..bcffb1ec5 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -294,73 +294,73 @@ deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc BTB_SIZE 16 deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 # Cache configurations @@ -390,6 +390,10 @@ deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc DCACHE_NUMWAYS 4 ICACHE_NUMWAYS 4 +deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 8 +ICACHE_NUMWAYS 8 + deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc DCACHE_WAYSIZEINBYTES 2048 ICACHE_WAYSIZEINBYTES 2048 @@ -513,3 +517,35 @@ ZFH_SUPPORTED 0 deriv fdqh_rv64gc rv64gc MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 + +# IEEE compatible variants for TestFloat + +deriv f_ieee_rv32gc rv32gc f_rv32gc +IEEE754 1 + +deriv fh_ieee_v32gc rv32gc fh_rv32gc +IEEE754 1 + +deriv fdh_ieee_rv32gc rv32gc fdh_rv32gc +IEEE754 1 + +deriv fdq_ieee_rv32gc rv32gc fdq_rv32gc +IEEE754 1 + +deriv fdqh_ieee_rv32gc rv32gc fdqh_rv32gc +IEEE754 1 + +deriv f_ieee_rv64gc rv64gc f_rv64gc +IEEE754 1 + +deriv fh_ieee_rv64gc rv64gc fh_rv64gc +IEEE754 1 + +deriv fd_ieee_rv64gc rv64gc fd_rv64gc +IEEE754 1 + +deriv fdq_ieee_rv64gc rv64gc fdq_rv64gc +IEEE754 1 + +deriv fdqh_ieee_rv64gc rv64gc fdqh_rv64gc +IEEE754 1 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 60153fdd2..9f0056fad 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -158,7 +158,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index eb021ab0e..8b4b78a4f 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -170,7 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; `endif -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index fe2aa9e51..81b25bc2b 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -159,7 +159,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 3714f0749..931725cc4 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -157,7 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 941e11382..3f5c8683a 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -160,7 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index c4e54e346..7f038d87e 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -160,7 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6; localparam BPRED_SIZE = 32'd10; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 3067e9eab..4dd540a9f 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -160,7 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/sim/sim-testfloat b/sim/sim-testfloat index 7f22690c0..b7da7104a 100755 --- a/sim/sim-testfloat +++ b/sim/sim-testfloat @@ -9,4 +9,4 @@ # sqrt - test square root # all - test everything -vsim -do "do testfloat.do rv64fpquad $1" +vsim -do "do testfloat.do fdqh_ieee_rv64gc $1" diff --git a/sim/sim-testfloat-batch b/sim/sim-testfloat-batch index 073553e52..96fb0f345 100755 --- a/sim/sim-testfloat-batch +++ b/sim/sim-testfloat-batch @@ -10,4 +10,4 @@ # sqrt - test square root # all - test everything -vsim -c -do "do testfloat.do rv64fpquad $1" \ No newline at end of file +vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1" diff --git a/sim/testfloat.do b/sim/testfloat.do index f21975389..796b540f3 100644 --- a/sim/testfloat.do +++ b/sim/testfloat.do @@ -25,7 +25,7 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # $num = the added words after the call -vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 +vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 # Change TEST_SIZE to only test certain FP width # values are QP, DP, SP, HP or all for all tests diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 658107f56..5eab7c7ec 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -35,6 +35,8 @@ module testbenchfp; `include "parameter-defs.vh" + parameter MAXVECTORS = 8388610; + // FIXME: needs cleaning of unused variables (jes) string Tests[]; // list of tests to be run logic [2:0] OpCtrl[]; // list of op controls @@ -49,7 +51,7 @@ module testbenchfp; logic [31:0] errors=0; // how many errors logic [31:0] VectorNum=0; // index for test vector logic [31:0] FrmNum=0; // index for rounding mode - logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors + logic [P.FLEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal @@ -975,7 +977,7 @@ module testbenchfp; // increment the test TestNum += 1; // clear the vectors - for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; + for(int i=0; i Date: Tue, 30 Jan 2024 09:52:23 -0800 Subject: [PATCH 3/4] Removed unused rv64fpquad config --- config/rv64fpquad/config.vh | 187 ------------------------------------ 1 file changed, 187 deletions(-) delete mode 100644 config/rv64fpquad/config.vh diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh deleted file mode 100644 index 3f5c8683a..000000000 --- a/config/rv64fpquad/config.vh +++ /dev/null @@ -1,187 +0,0 @@ -////////////////////////////////////////// -// config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "BranchPredictorType.vh" - -// RV32 or RV64: XLEN = 32 or 64 -localparam XLEN = 32'd64; - -// IEEE 754 compliance -localparam IEEE754 = 1; - -// MISA RISC-V configuration per specification -localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ); -localparam ZICSR_SUPPORTED = 1; -localparam ZIFENCEI_SUPPORTED = 1; -localparam COUNTERS = 12'd32; -localparam ZICNTR_SUPPORTED = 1; -localparam ZIHPM_SUPPORTED = 1; -localparam ZFH_SUPPORTED = 1; -localparam ZFA_SUPPORTED = 0; -localparam SSTC_SUPPORTED = 0; -localparam ZICBOM_SUPPORTED = 0; -localparam ZICBOZ_SUPPORTED = 0; -localparam ZICBOP_SUPPORTED = 0; -localparam ZICCLSM_SUPPORTED = 0; -localparam ZICOND_SUPPORTED = 0; -localparam SVPBMT_SUPPORTED = 0; -localparam SVNAPOT_SUPPORTED = 0; -localparam SVINVAL_SUPPORTED = 1; - -// LSU microarchitectural Features -localparam BUS_SUPPORTED = 1; -localparam DCACHE_SUPPORTED = 1; -localparam ICACHE_SUPPORTED = 1; -localparam VIRTMEM_SUPPORTED = 1; -localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ; -localparam BIGENDIAN_SUPPORTED = 1; - -// TLB configuration. Entries should be a power of 2 -localparam ITLB_ENTRIES = 32'd32; -localparam DTLB_ENTRIES = 32'd32; - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -localparam DCACHE_NUMWAYS = 32'd4; -localparam DCACHE_WAYSIZEINBYTES = 32'd4096; -localparam DCACHE_LINELENINBITS = 32'd512; -localparam ICACHE_NUMWAYS = 32'd4; -localparam ICACHE_WAYSIZEINBYTES = 32'd4096; -localparam ICACHE_LINELENINBITS = 32'd512; -localparam CACHE_SRAMLEN = 32'd128; - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 32'd4; -localparam IDIV_ON_FPU = 1; - -// Legal number of PMP entries are 0, 16, or 64 -localparam PMP_ENTRIES = 32'd16; - -// Address space -localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; - -// Bus Interface width -localparam AHBW = 32'd64; - -// WFI Timeout Wait -localparam WFI_TIMEOUT_BIT = 32'd16; - -// Peripheral Physiccal Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -localparam DTIM_SUPPORTED = 1'b0; -localparam logic [63:0] DTIM_BASE = 64'h80000000; -localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; -localparam IROM_SUPPORTED = 1'b0; -localparam logic [63:0] IROM_BASE = 64'h80000000; -localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; -localparam BOOTROM_SUPPORTED = 1'b1; -localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; -localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; -localparam EXT_MEM_SUPPORTED = 1'b0; -localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; -localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; -localparam CLINT_SUPPORTED = 1'b1; -localparam logic [63:0] CLINT_BASE = 64'h02000000; -localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; -localparam GPIO_SUPPORTED = 1'b1; -localparam logic [63:0] GPIO_BASE = 64'h10060000; -localparam logic [63:0] GPIO_RANGE = 64'h000000FF; -localparam UART_SUPPORTED = 1'b1; -localparam logic [63:0] UART_BASE = 64'h10000000; -localparam logic [63:0] UART_RANGE = 64'h00000007; -localparam PLIC_SUPPORTED = 1'b1; -localparam logic [63:0] PLIC_BASE = 64'h0C000000; -localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; -localparam SDC_SUPPORTED = 1'b0; -localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; -localparam SPI_SUPPORTED = 1'b1; -localparam logic [63:0] SPI_BASE = 64'h10040000; -localparam logic [63:0] SPI_RANGE = 64'h00000FFF; - -// Test modes - -// AHB -localparam RAM_LATENCY = 32'b0; -localparam BURST_EN = 1; - -// Tie GPIO outputs back to inputs -localparam GPIO_LOOPBACK_TEST = 1; -localparam SPI_LOOPBACK_TEST = 1; - -// Hardware configuration -localparam UART_PRESCALE = 32'd1; - -// Interrupt configuration -localparam PLIC_NUM_SRC = 32'd10; -// comment out the following if >=32 sources -localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); -localparam PLIC_GPIO_ID = 32'd3; -localparam PLIC_UART_ID = 32'd10; -localparam PLIC_SPI_ID = 32'd6; -localparam PLIC_SDC_ID = 32'd9; - -localparam BPRED_SUPPORTED = 1; -localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 32'd10; -localparam BPRED_NUM_LHR = 32'd6; -localparam BTB_SIZE = 32'd10; -localparam RAS_SIZE = 32'd16; -localparam INSTR_CLASS_PRED = 1; - -localparam SVADU_SUPPORTED = 0; -localparam ZMMUL_SUPPORTED = 0; - -// FPU division architecture -localparam RADIX = 32'h4; -localparam DIVCOPIES = 32'h4; - -// bit manipulation -localparam ZBA_SUPPORTED = 0; -localparam ZBB_SUPPORTED = 0; -localparam ZBC_SUPPORTED = 0; -localparam ZBS_SUPPORTED = 0; - -// New compressed instructions -localparam ZCB_SUPPORTED = 0; -localparam ZCA_SUPPORTED = 0; -localparam ZCF_SUPPORTED = 0; -localparam ZCD_SUPPORTED = 0; - -// Memory synthesis configuration -localparam USE_SRAM = 0; - -`include "config-shared.vh" From d9003da8e0c2e404c2597f3c1bad5b40bd4a7ee1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 30 Jan 2024 10:28:51 -0800 Subject: [PATCH 4/4] Moved some tests to wally-riscv-arch-test list that are simulated --- .../riscv-test-suite/rv32i_m/privilege/Makefrag | 9 ++++----- .../riscv-test-suite/rv64i_m/privilege/Makefrag | 10 +++++----- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index 67f7c2f93..243d9011f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -36,11 +36,13 @@ rv32i_sc_tests = \ WALLY-lrsc-01 \ WALLY-status-mie-01 \ WALLY-trap-sret-01 \ - + WALLY-status-fp-enabled-01 \ + WALLY-minfo-01 \ + WALLY-cboz-01 \ + WALLY-cbom-01 \ target_tests_nosim = \ WALLY-pma-01 \ - WALLY-minfo-01 \ WALLY-mtvec-01 \ WALLY-stvec-01 \ WALLY-mie-01 \ @@ -49,7 +51,6 @@ target_tests_nosim = \ WALLY-trap-s-01 \ WALLY-trap-u-01 \ WALLY-wfi-01 \ - WALLY-status-fp-enabled-01 \ WALLY-status-sie-01 \ WALLY-status-tw-01 \ WALLY-gpio-01 \ @@ -57,8 +58,6 @@ target_tests_nosim = \ WALLY-plic-01 \ WALLY-uart-01 \ WALLY-spi-01 \ - WALLY-cbom-01 \ - WALLY-cboz-01 \ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index a640e0c06..a96fae3db 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -39,12 +39,16 @@ rv64i_sc_tests = \ WALLY-status-mie-01 \ WALLY-status-sie-01 \ WALLY-status-tw-01 \ + WALLY-status-fp-enabled-01 \ + WALLY-misaligned-access-01 \ + WALLY-minfo-01 \ + WALLY-cboz-01 \ + WALLY-cbom-01 \ # Don't simulate these because they rely on SoC features that Spike does not offer. target_tests_nosim = \ WALLY-pma-01 \ - WALLY-minfo-01 \ WALLY-periph-01 \ WALLY-mtvec-01 \ WALLY-stvec-01 \ @@ -53,14 +57,10 @@ target_tests_nosim = \ WALLY-trap-01 \ WALLY-trap-s-01 \ WALLY-trap-u-01 \ - WALLY-status-fp-enabled-01 \ WALLY-spi-01 \ WALLY-gpio-01 \ WALLY-uart-01 \ WALLY-wfi-01 \ - WALLY-cbom-01 \ - WALLY-cboz-01 \ - WALLY-misaligned-access-01 \ # unclear why status-fp-enabled and wfi aren't simulating ok