From bf07ec92b55d2e464604078d7e725a297f0b730b Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 25 Jan 2021 11:28:43 -0500 Subject: [PATCH] Added test configurations --- .../{src => config/busybear}/wally-config.vh | 0 wally-pipelined/config/rv32ic/wally-config.vh | 67 +++++++++++++++++++ wally-pipelined/config/rv64ic/wally-config.vh | 67 +++++++++++++++++++ .../regression/regression-wally.py | 35 ++++++++++ wally-pipelined/{ => regression}/sim-wally | 0 wally-pipelined/regression/sim-wally-batch | 3 + .../{ => regression}/wally-busybear.do | 0 .../{ => regression}/wally-pipelined-batch.do | 7 +- .../{ => regression}/wally-pipelined.do | 2 +- wally-pipelined/sim-wally-batch | 1 - wally-pipelined/src/uart.sv | 4 +- wally-pipelined/src/wally-macros.sv | 33 --------- .../{src => testbench}/testbench-busybear.sv | 0 .../testbench-imperas.sv} | 9 +-- 14 files changed, 184 insertions(+), 44 deletions(-) rename wally-pipelined/{src => config/busybear}/wally-config.vh (100%) create mode 100644 wally-pipelined/config/rv32ic/wally-config.vh create mode 100644 wally-pipelined/config/rv64ic/wally-config.vh create mode 100755 wally-pipelined/regression/regression-wally.py rename wally-pipelined/{ => regression}/sim-wally (100%) create mode 100755 wally-pipelined/regression/sim-wally-batch rename wally-pipelined/{ => regression}/wally-busybear.do (100%) rename wally-pipelined/{ => regression}/wally-pipelined-batch.do (75%) rename wally-pipelined/{ => regression}/wally-pipelined.do (93%) delete mode 100755 wally-pipelined/sim-wally-batch delete mode 100644 wally-pipelined/src/wally-macros.sv rename wally-pipelined/{src => testbench}/testbench-busybear.sv (100%) rename wally-pipelined/{src/testbench.sv => testbench/testbench-imperas.sv} (98%) diff --git a/wally-pipelined/src/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh similarity index 100% rename from wally-pipelined/src/wally-config.vh rename to wally-pipelined/config/busybear/wally-config.vh diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh new file mode 100644 index 000000000..c3d8faab4 --- /dev/null +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -0,0 +1,67 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 32 + +`define MISA (32'h00000104) +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +`define ZCSR_SUPPORTED 1 +`define ZCOUNTERS_SUPPORTED 1 +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define MEM_DCACHE 0 +`define MEM_DTIM 1 +`define MEM_ICACHE 0 +`define MEM_VIRTMEM 0 + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 0 + + +// Hardware configuration +`define UART_PRESCALE 1 + +/* verilator lint_off STMTDLY */ +/* verilator lint_off WIDTH */ diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh new file mode 100644 index 000000000..baa035bd2 --- /dev/null +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -0,0 +1,67 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 64 + +`define MISA (32'h00000104) +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +`define ZCSR_SUPPORTED 1 +`define ZCOUNTERS_SUPPORTED 1 +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define MEM_DCACHE 0 +`define MEM_DTIM 1 +`define MEM_ICACHE 0 +`define MEM_VIRTMEM 0 + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 0 + + +// Hardware configuration +`define UART_PRESCALE 1 + +/* verilator lint_off STMTDLY */ +/* verilator lint_off WIDTH */ diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py new file mode 100755 index 000000000..dc23232dc --- /dev/null +++ b/wally-pipelined/regression/regression-wally.py @@ -0,0 +1,35 @@ +#!/usr/bin/python3 +################################## +# +# regression-wally.py +# David_Harris@Hmc.edu 25 January 2021 +# +# Run a regression with multiple configurations and report any errors. +# +################################## + +# edit this line to add more configurations +confignames = ["rv32ic", "rv64ic"] + +import os + +fail = 0 + +for config in confignames: + logname = "wally_"+config+".log" + cmd = "vsim -c >" + logname +" < /dev/null" + grepval = os.system(cmd) + if (grepval): + fail = fail + 1 + print(logname+": failures detected") + else: + print(logname+": Success") + +if (fail): + print ("Regression failed with " +str(fail)+ " failed configurations") +else: + print ("SUCCESS! All tests ran without failures") diff --git a/wally-pipelined/sim-wally b/wally-pipelined/regression/sim-wally similarity index 100% rename from wally-pipelined/sim-wally rename to wally-pipelined/regression/sim-wally diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch new file mode 100755 index 000000000..5305cfc60 --- /dev/null +++ b/wally-pipelined/regression/sim-wally-batch @@ -0,0 +1,3 @@ +vsim -c <" prompt: -# do wally-pipelined.do +# do wally-pipelined.do ../config/rv64ic # or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c +# vsim -c -do wally-pipelined.do ../config/rv64ic # (omit the "-c" to see the GUI while running from the shell) onbreak {resume} @@ -27,7 +27,8 @@ vlib work # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog src/*.sv -suppress 2583 +#vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583 +vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals diff --git a/wally-pipelined/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do similarity index 93% rename from wally-pipelined/wally-pipelined.do rename to wally-pipelined/regression/wally-pipelined.do index 87fbf414a..2750cb174 100644 --- a/wally-pipelined/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -26,7 +26,7 @@ vlib work # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog src/*.sv -suppress 2583 +vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals diff --git a/wally-pipelined/sim-wally-batch b/wally-pipelined/sim-wally-batch deleted file mode 100755 index 27cd41d7d..000000000 --- a/wally-pipelined/sim-wally-batch +++ /dev/null @@ -1 +0,0 @@ -vsim -c -do wally-pipelined-batch.do diff --git a/wally-pipelined/src/uart.sv b/wally-pipelined/src/uart.sv index ed041c7e5..084a5c435 100644 --- a/wally-pipelined/src/uart.sv +++ b/wally-pipelined/src/uart.sv @@ -52,7 +52,7 @@ module uart ( generate if (`XLEN == 64) begin always_comb begin -/* RdUARTM = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; + RdUARTM = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; case (AdrM[2:0]) 3'b000: Din = MaskedWriteDataM[7:0]; 3'b001: Din = MaskedWriteDataM[15:8]; @@ -62,7 +62,7 @@ module uart ( 3'b101: Din = MaskedWriteDataM[47:40]; 3'b110: Din = MaskedWriteDataM[55:48]; 3'b111: Din = MaskedWriteDataM[63:56]; - endcase */ + endcase end end else begin // 32-bit always_comb begin diff --git a/wally-pipelined/src/wally-macros.sv b/wally-pipelined/src/wally-macros.sv deleted file mode 100644 index c52e206d9..000000000 --- a/wally-pipelined/src/wally-macros.sv +++ /dev/null @@ -1,33 +0,0 @@ -// wally-macros.sv -// David_Harris@hmc.edu 5 January 2021 - -// Macros to determine which mode is supported based on MISA - -`define A_SUPPORTED ((MISA >> 0) % 2 == 1) -`define C_SUPPORTED ((MISA >> 2) % 2 == 1) -`define D_SUPPORTED ((MISA >> 3) % 2 == 1) -`define F_SUPPORTED ((MISA >> 5) % 2 == 1) -`define M_SUPPORTED ((MISA >> 12) % 2 == 1) -`define S_SUPPORTED ((MISA >> 18) % 2 == 1) -`define U_SUPPORTED ((MISA >> 20) % 2 == 1) -`define ZCSR_SUPPORTED (ZCSR != 0) -`define ZCOUNTERS_SUPPORTED (ZCOUNTERS != 0) -// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 -//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) -`define N_SUPPORTED 0 - -`define M_MODE (2'b11) -`define S_MODE (2'b01) -`define U_MODE (2'b00) - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 - - -// Hardware configuration -`define UART_PRESCALE 1 - -/* verilator lint_off STMTDLY */ -/* verilator lint_off WIDTH */ diff --git a/wally-pipelined/src/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv similarity index 100% rename from wally-pipelined/src/testbench-busybear.sv rename to wally-pipelined/testbench/testbench-busybear.sv diff --git a/wally-pipelined/src/testbench.sv b/wally-pipelined/testbench/testbench-imperas.sv similarity index 98% rename from wally-pipelined/src/testbench.sv rename to wally-pipelined/testbench/testbench-imperas.sv index 2ec3d0878..f447d12d8 100644 --- a/wally-pipelined/src/testbench.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -1,10 +1,11 @@ /////////////////////////////////////////// -// testbench.sv +// testbench-imperas.sv // // Written: David_Harris@hmc.edu 9 January 2021 // Modified: // // Purpose: Wally Testbench and helper modules +// Applies test programs from the Imperas suite // // A component of the Wally configurable RISC-V project. // @@ -265,7 +266,7 @@ string tests32i[] = { // dut.dmem.RAM[i] = meminit; end // read test vectors into memory - memfilename = {"../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; + memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.dmem.dtim.RAM); reset = 1; # 22; reset = 0; @@ -290,7 +291,7 @@ string tests32i[] = { end // read signature, reformat in 64 bits if necessary - signame = {"../imperas-riscv-tests/work/", tests[test], ".signature.output"}; + signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"}; $readmemh(signame, sig32); i = 0; while (i < 10000) begin @@ -337,7 +338,7 @@ string tests32i[] = { $stop; end else begin - memfilename = {"../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; + memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.dmem.dtim.RAM); $display("Read memfile %s", memfilename);