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Reverted logic to bit change.

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This commit is contained in:
Rose Thompson 2023-12-20 13:16:32 -06:00
parent f52ad13a65
commit b68dd74f89
3 changed files with 3 additions and 3 deletions
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2
src/mmu/hptw.sv
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@ -155,7 +155,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] AccessedPTE; logic [P.XLEN-1:0] AccessedPTE;
assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
assign ReadDataNoXM = (ReadDataM === 'x) ? '0 : ReadDataM; // Hack to ensure the TLBs are never written with x's because they will propagate and hang the simulation. assign ReadDataNoXM = (ReadDataM[0] === 'x) ? '0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation.
mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0 mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0
flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);

2
testbench/common/DCacheFlushFSM.sv
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@ -35,7 +35,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
genvar adr; genvar adr;
bit [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)];
logic startD; logic startD;
if(P.DCACHE_SUPPORTED) begin if(P.DCACHE_SUPPORTED) begin

2
testbench/testbench.sv
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@ -187,7 +187,7 @@ module testbench;
logic LoadMem; logic LoadMem;
logic ResetCntEn; logic ResetCntEn;
logic ResetCntRst; logic ResetCntRst;
logic CopyRAM;
string signame, memfilename, pathname; string signame, memfilename, pathname;
integer begin_signature_addr; integer begin_signature_addr;