From b68dd74f89692f4c5c37d3745b502b56269807c5 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 20 Dec 2023 13:16:32 -0600
Subject: [PATCH] Reverted logic to bit change.

---
 src/mmu/hptw.sv                    | 2 +-
 testbench/common/DCacheFlushFSM.sv | 2 +-
 testbench/testbench.sv             | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index 80e4fc9f0..322a730dd 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -155,7 +155,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
     logic [P.XLEN-1:0]    AccessedPTE;
 
     assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
-    assign ReadDataNoXM = (ReadDataM === 'x) ? '0 : ReadDataM; // Hack to ensure the TLBs are never written with x's because they will propagate and hang the simulation.
+    assign ReadDataNoXM = (ReadDataM[0] === 'x) ? '0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation.
     mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0
     flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
     
diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv
index 1f41968c3..152aaa173 100644
--- a/testbench/common/DCacheFlushFSM.sv
+++ b/testbench/common/DCacheFlushFSM.sv
@@ -35,7 +35,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
 
   genvar adr;
 
-  bit [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)];
+  logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)];
   logic         startD;
   
   if(P.DCACHE_SUPPORTED) begin
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 3607a5f06..3166383dc 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -187,7 +187,7 @@ module testbench;
   logic        LoadMem;
   logic        ResetCntEn;
   logic        ResetCntRst;
-  
+  logic        CopyRAM;
 
   string  signame, memfilename, pathname;
   integer begin_signature_addr;