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Merge pull request #400 from kipmacsaigoren/synth_wrapper_gen

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configurability for synthesis wrapper generation
This commit is contained in:
David Harris 2023-08-29 12:41:41 -07:00 committed by GitHub
commit a329fcd998
4 changed files with 19 additions and 30 deletions
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8
synthDC/Makefile
View File

@ -3,7 +3,6 @@
# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022
# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023
NAME := synth
# defaults
export DESIGN ?= wallypipelinedcore
export FREQ ?= 10000
@ -18,9 +17,12 @@ export TECH ?= sky90
export MAXCORES ?= 1
# MAXOPT turns on flattening, boundary optimization, and retiming
# The output netlist is hard to interpret, but significantly better PPA
# WRAPPER turns on wrapper generation
export MAXOPT ?= 0
export DRIVE ?= FLOP
export USESRAM ?= 0
export WRAPPER ?= 0
time := $(shell date +%F-%H-%M)
hash := $(shell git rev-parse --short HEAD)
@ -120,7 +122,9 @@ endif
mkwrapper:
ifeq ($(WRAPPER),1)
python3 $(WALLY)/synthDC/scripts/wrapperGen.py $(DESIGN)
endif
mkdirecs:
@echo "DC Synthesis"
@mkdir -p $(OUTPUTDIR)
@ -150,4 +154,4 @@ clean:
rm -f power.saif
rm -f Synopsys_stack_trace_*.txt
rm -f crte_*.txt
rm $(WALLY)/synthDC/wrappers/*
rm $(WALLY)/synthDC/wrappers/*

15
synthDC/scripts/synth.tcl
View File

@ -16,6 +16,7 @@ suppress_message {VER-173}
# Enable Multicore
set_host_options -max_cores $::env(MAXCORES)
# get outputDir and configDir from environment (Makefile)
set outputDir $::env(OUTPUTDIR)
set cfg $::env(CONFIGDIR)
@ -23,13 +24,17 @@ set hdl_src "../src"
set saifpower $::env(SAIFPOWER)
set maxopt $::env(MAXOPT)
set drive $::env(DRIVE)
set wrapper $::env(WRAPPER)
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
if {$wrapper ==1 } {
eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
}
# Only for FMA class project; comment out when done
# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
@ -43,7 +48,11 @@ if { $saifpower == 1 } {
set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
# Set toplevel
set my_toplevel $::env(DESIGN)wrapper
if { $wrapper == 1 } {
set my_toplevel $::env(DESIGN)wrapper
} else {
set my_toplevel $::env(DESIGN)
}
# Set number of significant digits
set report_default_significant_digits 6
@ -404,4 +413,4 @@ set t2 [clock seconds]
set t [expr $t2 - $t1]
echo [expr $t/60]
quit
quit

2
synthDC/scripts/wrapperGen.py
View File

@ -63,7 +63,7 @@ buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv"
# clear wrappers directory
os.system(f"rm {os.getenv('WALLY')}/src/wrappers/*")
os.system(f"rm {os.getenv('WALLY')}/synthDC/wrappers/*")
fout = open(wrapperPath, "w")

24
synthDC/wrappers/wallypipelinedcorewrapper.sv
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@ -1,24 +0,0 @@
import cvw::*;
`include "config.vh"
`include "parameter-defs.vh"
module wallypipelinedcorewrapper (
input logic clk, reset,
// Privileged
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
// Bus Interface
input logic [P.AHBW-1:0] HRDATA,
input logic HREADY, HRESP,
output logic HCLK, HRESETn,
output logic [P.PA_BITS-1:0] HADDR,
output logic [P.AHBW-1:0] HWDATA,
output logic [P.XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK
);
wallypipelinedcore #(P) dut(.*);
endmodule