From 6d0c247926f7dfb0a5d64da37360e13c9c1b208d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 28 Aug 2023 09:32:59 -0700 Subject: [PATCH 1/4] added configurability for wrapper --- synthDC/Makefile | 12 +- synthDC/scripts/synth.tcl | 5 +- synthDC/scripts/synthWrapper.tcl | 407 +++++++++++++++++++++++++++++++ 3 files changed, 420 insertions(+), 4 deletions(-) create mode 100755 synthDC/scripts/synthWrapper.tcl diff --git a/synthDC/Makefile b/synthDC/Makefile index 881abd406..58f54cb88 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -2,7 +2,6 @@ # Makefile for synthesis # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 # Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 -NAME := synth # defaults export DESIGN ?= wallypipelinedcore @@ -18,9 +17,18 @@ export TECH ?= sky90 export MAXCORES ?= 1 # MAXOPT turns on flattening, boundary optimization, and retiming # The output netlist is hard to interpret, but significantly better PPA +# WRAPPER turns on wrapper generation export MAXOPT ?= 0 export DRIVE ?= FLOP export USESRAM ?= 0 +export WRAPPER ?= 0 + +ifeq ($(WRAPPER),1) + rm $(WALLY)/synthDC/wrappers/* + NAME := synthWrapper +else + NAME := synth +endif time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) @@ -120,7 +128,9 @@ endif mkwrapper: +ifeq ($(WRAPPER),1) python3 $(WALLY)/synthDC/scripts/wrapperGen.py $(DESIGN) +endif mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index bcf07902f..7de696da2 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -29,7 +29,6 @@ eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} #eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/} # Only for FMA class project; comment out when done # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} @@ -43,7 +42,7 @@ if { $saifpower == 1 } { set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv] # Set toplevel -set my_toplevel $::env(DESIGN)wrapper +set my_toplevel $::env(DESIGN) # Set number of significant digits set report_default_significant_digits 6 @@ -404,4 +403,4 @@ set t2 [clock seconds] set t [expr $t2 - $t1] echo [expr $t/60] -quit +quit \ No newline at end of file diff --git a/synthDC/scripts/synthWrapper.tcl b/synthDC/scripts/synthWrapper.tcl new file mode 100755 index 000000000..d15234692 --- /dev/null +++ b/synthDC/scripts/synthWrapper.tcl @@ -0,0 +1,407 @@ +# +# Synthesis Synopsys Flow +# james.stine@okstate.edu 27 Sep 2015 +# kekim@hmc.edu + +# start run clock +set t1 [clock seconds] + +# Ignore unnecessary warnings: +# intraassignment delays for nonblocking assignments are ignored +suppress_message {VER-130} +# statements in initial blocks are ignored +suppress_message {VER-281} +suppress_message {VER-173} + +# Enable Multicore +set_host_options -max_cores $::env(MAXCORES) + +# get outputDir and configDir from environment (Makefile) +set outputDir $::env(OUTPUTDIR) +set cfg $::env(CONFIGDIR) +set hdl_src "../src" +set saifpower $::env(SAIFPOWER) +set maxopt $::env(MAXOPT) +set drive $::env(DRIVE) + +eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} +#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/} + +# Only for FMA class project; comment out when done +# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} + +# Enables name mapping +if { $saifpower == 1 } { + saif_map -start +} + +# Verilog files +set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv] + +# Set toplevel +set my_toplevel $::env(DESIGN)wrapper + +# Set number of significant digits +set report_default_significant_digits 6 + +# V(HDL) Unconnectoed Pins Output +set verilogout_show_unconnected_pins "true" +set vhdlout_show_unconnected_pins "true" + +# Set up MW List +set MY_LIB_NAME $my_toplevel +# Create MW +if { [shell_is_in_topographical_mode] } { + echo "In Topographical Mode...processing\n" + create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ + -mw_reference_library $mw_reference_library $outputDir/$MY_LIB_NAME + # Open MW + open_mw_lib $outputDir/$MY_LIB_NAME + + # TLU+ + set_tlu_plus_files -max_tluplus $MAX_TLU_FILE -min_tluplus $MIN_TLU_FILE \ + -tech2itf_map $PRS_MAP_FILE + +} else { + echo "In normal DC mode...processing\n" +} + +# Due to parameterized Verilog must use analyze/elaborate and not +# read_verilog/vhdl (change to pull in Verilog and/or VHDL) +# +#set alib_library_analysis_path ./$outputDir +define_design_lib WORK -path ./$outputDir/WORK +analyze -f sverilog -lib WORK $my_verilog_files +elaborate $my_toplevel -lib WORK + +# Set the current_design +current_design $my_toplevel +link + +# Reset all constraints +reset_design + +# Power Dissipation Analysis +######### OPTIONAL !!!!!!!!!!!!!!!! +if { $saifpower == 1 } { + read_saif -input power.saif -instance_name testbench/dut/core -auto_map_names -verbose +} + +# Set reset false path +if {$drive != "INV"} { + set_false_path -from [get_ports reset] +} +if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} { + set_false_path -from {s} +} + +# Set Frequency in [MHz] or period in [ns] +set my_clock_pin clk +set my_uncertainty 0.0 +set my_clk_freq_MHz $::env(FREQ) +set my_period [expr 1000.0 / $my_clk_freq_MHz] + +# Create clock object +set find_clock [ find port [list $my_clock_pin] ] +if { $find_clock != [list] } { + echo "Found clock!" + set my_clk $my_clock_pin + create_clock -period $my_period $my_clk + set_clock_uncertainty $my_uncertainty [get_clocks $my_clk] +} else { + echo "Did not find clock! Design is probably combinational!" + set my_clk vclk + create_clock -period $my_period -name $my_clk +} + +# Optimize paths that are close to critical +set_critical_range 0.05 $current_design + +# Partitioning - flatten or hierarchically synthesize +if { $maxopt == 1 } { + ungroup -all -simple_names -flatten +} + +# Set input pins except clock +set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] + +# Specifies delays be propagated through the clock network +# This is getting optimized poorly in the current flow, causing a lot of clock skew +# and unrealistic bad timing results. +# set_propagated_clock [get_clocks $my_clk] + +# Setting constraints on input ports +if {$tech == "sky130"} { + set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk +} elseif {$tech == "sky90"} { + if {$drive == "INV"} { + set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk + } elseif {$drive == "FLOP"} { + set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk + } +} elseif {$tech == "tsmc28" || $tech=="tsmc28psyn"} { + if {$drive == "INV"} { + set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk + } elseif {$drive == "FLOP"} { + set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk + } +} + +# Set input/output delay +if {$drive == "FLOP"} { + set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk + set_output_delay 0.0 -max -clock $my_clk [all_outputs] +} else { + set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk + set_output_delay 0.0 -max -clock $my_clk [all_outputs] +} + +# Setting load constraint on output ports +if {$tech == "sky130"} { + set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] +} elseif {$tech == "sky90"} { + if {$drive == "INV"} { + set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs] + } elseif {$drive == "FLOP"} { + set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] + } +} elseif {$tech == "tsmc28" || $tech == "tsmc28psyn"} { + if {$drive == "INV"} { + set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] + } elseif {$drive == "FLOP"} { + set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs] + } +} + +if {$tech != "tsmc28psyn"} { + # Set the wire load model + set_wire_load_mode "top" +} + +# Set switching activities +# default activity factors are 1 for clocks, 0.1 for others +# static probability of 0.5 is used for leakage + +# Attempt Area Recovery - if looking for minimal area +# set_max_area 2000 + +# Set fanout +set_max_fanout 6 $all_in_ex_clk + +# Fix hold time violations (DH: this doesn't seem to be working right now) +#set_fix_hold [all_clocks] + +# Deal with constants and buffers to isolate ports +set_fix_multiple_port_nets -all -buffer_constants + +# setting up the group paths to find out the required timings +# group_path -name OUTPUTS -to [all_outputs] +# group_path -name INPUTS -from [all_inputs] +# group_path -name COMBO -from [all_inputs] -to [all_outputs] + +# Save Unmapped Design +# set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] +# write_file -format ddc -hierarchy -o $filename + +# Compile statements +if { $maxopt == 1 } { + compile_ultra -retime + optimize_registers +} else { + compile_ultra -no_seq_output_inversion -no_boundary_optimization +} + +# Eliminate need for assign statements (yuck!) +set verilogout_no_tri true +set verilogout_equation false + +# setting to generate output files +set write_v 1 ;# generates structual netlist +set write_sdc 1 ;# generates synopsys design constraint file for p&r +set write_ddc 1 ;# compiler file in ddc format +set write_sdf 1 ;# sdf file for backannotated timing sim +set write_pow 1 ;# genrates estimated power report +set write_rep 1 ;# generates estimated area and timing report +set write_cst 1 ;# generate report of constraints +set write_hier 1 ;# generate hierarchy report + +# Report Constraint Violators +set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"] +redirect $filename {report_constraint -all_violators} + +# Check design +redirect $outputDir/reports/check_design.rpt { check_design } + +# Report Final Netlist (Hierarchical) +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"] +write_file -f verilog -hierarchy -output $filename + +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"] +write_sdc $filename + +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"] +write_file -format ddc -hierarchy -o $filename + +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"] +write_sdf $filename + +# QoR +set filename [format "%s%s" $outputDir "/reports/qor.rep"] +redirect $filename { report_qor } + +# Report Timing +set filename [format "%s%s" $outputDir "/reports/reportpath.rep"] +#redirect $filename { report_path_group } + +set filename [format "%s%s" $outputDir "/reports/report_clock.rep"] +# redirect $filename { report_clock } + +set filename [format "%s%s" $outputDir "/reports/timing.rep"] +redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 } + +set filename [format "%s%s" $outputDir "/reports/mindelay.rep"] +redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 } + +set filename [format "%s%s" $outputDir "/reports/per_module_timing.rep"] +redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through lsu ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through ebu (ahblite) ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ebu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through mdu ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through hzu ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {hzu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through priv ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through fpu ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 } + +set filename [format "%s%s" $outputDir "/reports/mdu_timing.rep"] +redirect -append $filename { echo "\n\n\n//// Critical paths through entire mdu ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through multiply unit ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through redundant multiplier ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/bigmul/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through ProdM (mul output) ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.ProdM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through PP0E (mul partial product) ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/PP0E} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through divide unit ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through QuotM (div output) ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.QuotM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through RemM (div output) ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.RemM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through div/WNextE ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/WNextE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through div/XQNextE ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/XQNextE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through div/DAbsBE ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 } + +# set filename [format "%s%s%s%s" $outputDir "/reports/fpu_timing.rep"] +# redirect $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 } + +# set filename [format "%s%s%s%s" $outputDir "/reports/ifu_timing.rep"] +# redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 } + +# set filename [format "%s%s%s%s" $outputDir "/reports/stall_flush_timing.rep"] +# redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 } + +# set filename [format "%s%s%s%s" $outputDir "/reports/ieu_timing.rep"] +# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 } + +# set filename [format "%s%s%s%s" $outputDir "/reports/fpu_timing.rep"] +# redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 } + +# set filename [format "%s%s%s%s" $outputDir "/reports/mmu_timing.rep"] +# redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 } + +# set filename [format "%s%s%s%s" $outputDir "/reports/priv_timing.rep"] +# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 } + +set filename [format "%s%s" $outputDir "/reports/area.rep"] +redirect $filename { report_area -hierarchy -nosplit -physical -designware} + +set filename [format "%s%s" $outputDir "/reports/cell.rep"] +#redirect $filename { report_cell [get_cells -hier *] } # not too useful + +set filename [format "%s%s" $outputDir "/reports/power.rep"] +redirect $filename { report_power -hierarchy -levels 1 } + +set filename [format "%s%s" $outputDir "/reports/constraint.rep"] +redirect $filename { report_constraint } + +set filename [format "%s%s" $outputDir "/reports/hier.rep"] +# redirect $filename { report_hierarchy } + +# end run clock and echo run time in minutes +set t2 [clock seconds] +set t [expr $t2 - $t1] +echo [expr $t/60] + +quit From 098111ea8506b12d73de4d18befd8d6a301ac080 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 28 Aug 2023 09:43:04 -0700 Subject: [PATCH 2/4] makefile bug fix --- synthDC/Makefile | 3 +-- synthDC/scripts/wrapperGen.py | 2 +- synthDC/wrappers/wallypipelinedcorewrapper.sv | 24 ------------------- 3 files changed, 2 insertions(+), 27 deletions(-) delete mode 100644 synthDC/wrappers/wallypipelinedcorewrapper.sv diff --git a/synthDC/Makefile b/synthDC/Makefile index 58f54cb88..44b938d34 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -24,7 +24,6 @@ export USESRAM ?= 0 export WRAPPER ?= 0 ifeq ($(WRAPPER),1) - rm $(WALLY)/synthDC/wrappers/* NAME := synthWrapper else NAME := synth @@ -160,4 +159,4 @@ clean: rm -f power.saif rm -f Synopsys_stack_trace_*.txt rm -f crte_*.txt - rm $(WALLY)/synthDC/wrappers/* + rm $(WALLY)/synthDC/wrappers/* \ No newline at end of file diff --git a/synthDC/scripts/wrapperGen.py b/synthDC/scripts/wrapperGen.py index d406dd6d3..aacdb0634 100755 --- a/synthDC/scripts/wrapperGen.py +++ b/synthDC/scripts/wrapperGen.py @@ -63,7 +63,7 @@ buf += f"\t{moduleName} #(P) dut(.*);\nendmodule" wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv" # clear wrappers directory -os.system(f"rm {os.getenv('WALLY')}/src/wrappers/*") +os.system(f"rm {os.getenv('WALLY')}/synthDC/wrappers/*") fout = open(wrapperPath, "w") diff --git a/synthDC/wrappers/wallypipelinedcorewrapper.sv b/synthDC/wrappers/wallypipelinedcorewrapper.sv deleted file mode 100644 index 9b44d7377..000000000 --- a/synthDC/wrappers/wallypipelinedcorewrapper.sv +++ /dev/null @@ -1,24 +0,0 @@ -import cvw::*; -`include "config.vh" -`include "parameter-defs.vh" -module wallypipelinedcorewrapper ( - input logic clk, reset, - // Privileged - input logic MTimerInt, MExtInt, SExtInt, MSwInt, - input logic [63:0] MTIME_CLINT, - // Bus Interface - input logic [P.AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [P.PA_BITS-1:0] HADDR, - output logic [P.AHBW-1:0] HWDATA, - output logic [P.XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK -); - wallypipelinedcore #(P) dut(.*); -endmodule \ No newline at end of file From 53fc6e1ca7a69f90b4618518c6f9193ef1763c44 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 29 Aug 2023 08:25:31 -0700 Subject: [PATCH 3/4] removed duplicate synth scripts --- synthDC/Makefile | 7 +------ synthDC/scripts/synth.tcl | 12 +++++++++++- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 44b938d34..57b478795 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -2,7 +2,7 @@ # Makefile for synthesis # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 # Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 - +NAME := synth # defaults export DESIGN ?= wallypipelinedcore export FREQ ?= 10000 @@ -23,11 +23,6 @@ export DRIVE ?= FLOP export USESRAM ?= 0 export WRAPPER ?= 0 -ifeq ($(WRAPPER),1) - NAME := synthWrapper -else - NAME := synth -endif time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 7de696da2..075bb5db9 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -16,6 +16,7 @@ suppress_message {VER-173} # Enable Multicore set_host_options -max_cores $::env(MAXCORES) + # get outputDir and configDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) set cfg $::env(CONFIGDIR) @@ -23,12 +24,17 @@ set hdl_src "../src" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) +set wrapper $::env(WRAPPER) eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} #eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} +if {$wrapper ==1 } { + eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/} +} + # Only for FMA class project; comment out when done # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} @@ -42,7 +48,11 @@ if { $saifpower == 1 } { set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv] # Set toplevel -set my_toplevel $::env(DESIGN) +if { $wrapper == 1 } { + set my_toplevel $::env(DESIGN)wrapper +} else { + set my_toplevel $::env(DESIGN) +} # Set number of significant digits set report_default_significant_digits 6 From b45c8efad3476d2f21f4a0524d2f2da99bbc338e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 29 Aug 2023 08:31:23 -0700 Subject: [PATCH 4/4] del old --- synthDC/scripts/synthWrapper.tcl | 407 ------------------------------- 1 file changed, 407 deletions(-) delete mode 100755 synthDC/scripts/synthWrapper.tcl diff --git a/synthDC/scripts/synthWrapper.tcl b/synthDC/scripts/synthWrapper.tcl deleted file mode 100755 index d15234692..000000000 --- a/synthDC/scripts/synthWrapper.tcl +++ /dev/null @@ -1,407 +0,0 @@ -# -# Synthesis Synopsys Flow -# james.stine@okstate.edu 27 Sep 2015 -# kekim@hmc.edu - -# start run clock -set t1 [clock seconds] - -# Ignore unnecessary warnings: -# intraassignment delays for nonblocking assignments are ignored -suppress_message {VER-130} -# statements in initial blocks are ignored -suppress_message {VER-281} -suppress_message {VER-173} - -# Enable Multicore -set_host_options -max_cores $::env(MAXCORES) - -# get outputDir and configDir from environment (Makefile) -set outputDir $::env(OUTPUTDIR) -set cfg $::env(CONFIGDIR) -set hdl_src "../src" -set saifpower $::env(SAIFPOWER) -set maxopt $::env(MAXOPT) -set drive $::env(DRIVE) - -eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} -#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/} - -# Only for FMA class project; comment out when done -# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} - -# Enables name mapping -if { $saifpower == 1 } { - saif_map -start -} - -# Verilog files -set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv] - -# Set toplevel -set my_toplevel $::env(DESIGN)wrapper - -# Set number of significant digits -set report_default_significant_digits 6 - -# V(HDL) Unconnectoed Pins Output -set verilogout_show_unconnected_pins "true" -set vhdlout_show_unconnected_pins "true" - -# Set up MW List -set MY_LIB_NAME $my_toplevel -# Create MW -if { [shell_is_in_topographical_mode] } { - echo "In Topographical Mode...processing\n" - create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ - -mw_reference_library $mw_reference_library $outputDir/$MY_LIB_NAME - # Open MW - open_mw_lib $outputDir/$MY_LIB_NAME - - # TLU+ - set_tlu_plus_files -max_tluplus $MAX_TLU_FILE -min_tluplus $MIN_TLU_FILE \ - -tech2itf_map $PRS_MAP_FILE - -} else { - echo "In normal DC mode...processing\n" -} - -# Due to parameterized Verilog must use analyze/elaborate and not -# read_verilog/vhdl (change to pull in Verilog and/or VHDL) -# -#set alib_library_analysis_path ./$outputDir -define_design_lib WORK -path ./$outputDir/WORK -analyze -f sverilog -lib WORK $my_verilog_files -elaborate $my_toplevel -lib WORK - -# Set the current_design -current_design $my_toplevel -link - -# Reset all constraints -reset_design - -# Power Dissipation Analysis -######### OPTIONAL !!!!!!!!!!!!!!!! -if { $saifpower == 1 } { - read_saif -input power.saif -instance_name testbench/dut/core -auto_map_names -verbose -} - -# Set reset false path -if {$drive != "INV"} { - set_false_path -from [get_ports reset] -} -if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} { - set_false_path -from {s} -} - -# Set Frequency in [MHz] or period in [ns] -set my_clock_pin clk -set my_uncertainty 0.0 -set my_clk_freq_MHz $::env(FREQ) -set my_period [expr 1000.0 / $my_clk_freq_MHz] - -# Create clock object -set find_clock [ find port [list $my_clock_pin] ] -if { $find_clock != [list] } { - echo "Found clock!" - set my_clk $my_clock_pin - create_clock -period $my_period $my_clk - set_clock_uncertainty $my_uncertainty [get_clocks $my_clk] -} else { - echo "Did not find clock! Design is probably combinational!" - set my_clk vclk - create_clock -period $my_period -name $my_clk -} - -# Optimize paths that are close to critical -set_critical_range 0.05 $current_design - -# Partitioning - flatten or hierarchically synthesize -if { $maxopt == 1 } { - ungroup -all -simple_names -flatten -} - -# Set input pins except clock -set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] - -# Specifies delays be propagated through the clock network -# This is getting optimized poorly in the current flow, causing a lot of clock skew -# and unrealistic bad timing results. -# set_propagated_clock [get_clocks $my_clk] - -# Setting constraints on input ports -if {$tech == "sky130"} { - set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk -} elseif {$tech == "sky90"} { - if {$drive == "INV"} { - set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk - } elseif {$drive == "FLOP"} { - set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk - } -} elseif {$tech == "tsmc28" || $tech=="tsmc28psyn"} { - if {$drive == "INV"} { - set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk - } elseif {$drive == "FLOP"} { - set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk - } -} - -# Set input/output delay -if {$drive == "FLOP"} { - set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk - set_output_delay 0.0 -max -clock $my_clk [all_outputs] -} else { - set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk - set_output_delay 0.0 -max -clock $my_clk [all_outputs] -} - -# Setting load constraint on output ports -if {$tech == "sky130"} { - set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] -} elseif {$tech == "sky90"} { - if {$drive == "INV"} { - set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs] - } elseif {$drive == "FLOP"} { - set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] - } -} elseif {$tech == "tsmc28" || $tech == "tsmc28psyn"} { - if {$drive == "INV"} { - set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] - } elseif {$drive == "FLOP"} { - set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs] - } -} - -if {$tech != "tsmc28psyn"} { - # Set the wire load model - set_wire_load_mode "top" -} - -# Set switching activities -# default activity factors are 1 for clocks, 0.1 for others -# static probability of 0.5 is used for leakage - -# Attempt Area Recovery - if looking for minimal area -# set_max_area 2000 - -# Set fanout -set_max_fanout 6 $all_in_ex_clk - -# Fix hold time violations (DH: this doesn't seem to be working right now) -#set_fix_hold [all_clocks] - -# Deal with constants and buffers to isolate ports -set_fix_multiple_port_nets -all -buffer_constants - -# setting up the group paths to find out the required timings -# group_path -name OUTPUTS -to [all_outputs] -# group_path -name INPUTS -from [all_inputs] -# group_path -name COMBO -from [all_inputs] -to [all_outputs] - -# Save Unmapped Design -# set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] -# write_file -format ddc -hierarchy -o $filename - -# Compile statements -if { $maxopt == 1 } { - compile_ultra -retime - optimize_registers -} else { - compile_ultra -no_seq_output_inversion -no_boundary_optimization -} - -# Eliminate need for assign statements (yuck!) -set verilogout_no_tri true -set verilogout_equation false - -# setting to generate output files -set write_v 1 ;# generates structual netlist -set write_sdc 1 ;# generates synopsys design constraint file for p&r -set write_ddc 1 ;# compiler file in ddc format -set write_sdf 1 ;# sdf file for backannotated timing sim -set write_pow 1 ;# genrates estimated power report -set write_rep 1 ;# generates estimated area and timing report -set write_cst 1 ;# generate report of constraints -set write_hier 1 ;# generate hierarchy report - -# Report Constraint Violators -set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"] -redirect $filename {report_constraint -all_violators} - -# Check design -redirect $outputDir/reports/check_design.rpt { check_design } - -# Report Final Netlist (Hierarchical) -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"] -write_file -f verilog -hierarchy -output $filename - -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"] -write_sdc $filename - -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"] -write_file -format ddc -hierarchy -o $filename - -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"] -write_sdf $filename - -# QoR -set filename [format "%s%s" $outputDir "/reports/qor.rep"] -redirect $filename { report_qor } - -# Report Timing -set filename [format "%s%s" $outputDir "/reports/reportpath.rep"] -#redirect $filename { report_path_group } - -set filename [format "%s%s" $outputDir "/reports/report_clock.rep"] -# redirect $filename { report_clock } - -set filename [format "%s%s" $outputDir "/reports/timing.rep"] -redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 } - -set filename [format "%s%s" $outputDir "/reports/mindelay.rep"] -redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 } - -set filename [format "%s%s" $outputDir "/reports/per_module_timing.rep"] -redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through lsu ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through ebu (ahblite) ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ebu/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through mdu ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through hzu ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {hzu/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through priv ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through fpu ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 } - -set filename [format "%s%s" $outputDir "/reports/mdu_timing.rep"] -redirect -append $filename { echo "\n\n\n//// Critical paths through entire mdu ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through multiply unit ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through redundant multiplier ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/bigmul/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through ProdM (mul output) ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.ProdM} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through PP0E (mul partial product) ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/PP0E} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through divide unit ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through QuotM (div output) ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.QuotM} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through RemM (div output) ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.RemM} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through div/WNextE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/WNextE} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through div/XQNextE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/XQNextE} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through div/DAbsBE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 } - -# set filename [format "%s%s%s%s" $outputDir "/reports/fpu_timing.rep"] -# redirect $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 } - -# set filename [format "%s%s%s%s" $outputDir "/reports/ifu_timing.rep"] -# redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 } - -# set filename [format "%s%s%s%s" $outputDir "/reports/stall_flush_timing.rep"] -# redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 } - -# set filename [format "%s%s%s%s" $outputDir "/reports/ieu_timing.rep"] -# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 } - -# set filename [format "%s%s%s%s" $outputDir "/reports/fpu_timing.rep"] -# redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 } - -# set filename [format "%s%s%s%s" $outputDir "/reports/mmu_timing.rep"] -# redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 } - -# set filename [format "%s%s%s%s" $outputDir "/reports/priv_timing.rep"] -# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 } -# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" } -# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 } - -set filename [format "%s%s" $outputDir "/reports/area.rep"] -redirect $filename { report_area -hierarchy -nosplit -physical -designware} - -set filename [format "%s%s" $outputDir "/reports/cell.rep"] -#redirect $filename { report_cell [get_cells -hier *] } # not too useful - -set filename [format "%s%s" $outputDir "/reports/power.rep"] -redirect $filename { report_power -hierarchy -levels 1 } - -set filename [format "%s%s" $outputDir "/reports/constraint.rep"] -redirect $filename { report_constraint } - -set filename [format "%s%s" $outputDir "/reports/hier.rep"] -# redirect $filename { report_hierarchy } - -# end run clock and echo run time in minutes -set t2 [clock seconds] -set t [expr $t2 - $t1] -echo [expr $t/60] - -quit