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Merge pull request #401 from ross144/main

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Fix Imperas testbench
This commit is contained in:
David Harris 2023-08-29 07:15:46 -07:00 committed by GitHub
commit 79b28a3e3c
5 changed files with 22 additions and 24 deletions
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4
fpga/constraints/constraints-vcu118.xdc
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@ -117,10 +117,10 @@ set_property PULLUP true [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 14.000 [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {SDCCmd}]

2
fpga/generator/xlnx_ddr4-vcu118.tcl
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@ -38,7 +38,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

4
linux/buildroot-packages/package-source/fpga-axi-sdc.c
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@ -272,6 +272,8 @@ static void sdc_reset(struct mmc_host * mmc) {
struct sdc_host * host = mmc_priv(mmc);
uint32_t card_detect = 0;
spin_lock_init(&host->lock);
spin_lock_irq(&host->lock);
sdc_set_clock(host, 400000);
@ -462,7 +464,7 @@ static int axi_sdc_probe(struct platform_device * pdev) {
return ret;
}
spin_lock_init(&host->lock);
//spin_lock_init(&host->lock);
platform_set_drvdata(pdev, host);
return 0;

16
linux/devicetree/wally-vcu118.dts
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@ -9,20 +9,20 @@
chosen {
linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>;
bootargs = "root=/dev/vda ro";
bootargs = "root=/dev/vda ro console=ttyS0,115200";
stdout-path = "/soc/uart@10000000";
};
memory@80000000 {
device_type = "memory";
reg = <0x00 0x80000000 0x00 0x08000000>;
reg = <0x00 0x80000000 0x00 0x10000000>;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-frequency = <0x2FAF080>;
timebase-frequency = <0x2FAF080>;
clock-frequency = <0x43B5FC0>;
timebase-frequency = <0x43B5FC0>;
cpu@0 {
phandle = <0x01>;
@ -51,7 +51,7 @@
uart@10000000 {
interrupts = <0x0a>;
interrupt-parent = <0x03>;
clock-frequency = <0x2FAF080>;
clock-frequency = <0x43B5FC0>;
reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a";
};
@ -74,10 +74,8 @@
fifo-depth = <256>;
bus-width = <4>;
interrupt-parent = <0x03>;
clock = <0x2FAF080>;
max-frequency = <0x989680>;
cap-sd-highspeed;
cap-mmc-highspeed;
clock = <0x43B5FC0>;
max-frequency = <0xF4240>;
no-sdio;
};

20
testbench/testbench_imperas.sv
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@ -60,6 +60,7 @@ module testbench;
logic [P.AHBW-1:0] HRDATAEXT;
logic HREADYEXT, HRESPEXT;
logic HSELEXTSDC;
logic [P.PA_BITS-1:0] HADDR;
logic [P.AHBW-1:0] HWDATA;
logic [P.XLEN/8-1:0] HWSTRB;
@ -81,13 +82,7 @@ module testbench;
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
logic UARTSin, UARTSout;
logic SDCCLK;
logic SDCCmdIn;
logic SDCCmdOut;
logic SDCCmdOE;
logic [3:0] SDCDatIn;
tri1 [3:0] SDCDat;
tri1 SDCCmd;
logic SDCIntr;
logic HREADY;
logic HSELEXT;
@ -239,6 +234,8 @@ module testbench;
end
if(P.FPGA) begin : sdcard
// *** fix later
/* -----\/----- EXCLUDED -----\/-----
sdModel sdcard
(.sdClk(SDCCLK),
.cmd(SDCCmd),
@ -247,15 +244,16 @@ module testbench;
assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
assign SDCCmdIn = SDCCmd;
assign SDCDatIn = SDCDat;
-----/\----- EXCLUDED -----/\----- */
assign SDCIntr = '0;
end else begin
assign SDCCmd = '0;
assign SDCDat = '0;
assign SDCIntr = '0;
end
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
.UARTSin, .UARTSout, .SDCIntr);
// Track names of instructions
instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,