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Merge pull request #755 from ross144/main
Bug fix: correct record the number of cache misses in the performance counters.
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src/cache/cachefsm.sv
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src/cache/cachefsm.sv
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@ -102,7 +102,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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// outputs for the performance counters.
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// outputs for the performance counters.
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assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
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assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
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assign CacheMiss = CacheAccess & ~Hit;
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assign CacheMiss = CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage;
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// special case on reset. When the fsm first exists reset twayhe
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// special case on reset. When the fsm first exists reset twayhe
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// PCNextF will no longer be pointing to the correct address.
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// PCNextF will no longer be pointing to the correct address.
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