diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index b3dc17024..d3cff2e96 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -102,7 +102,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
 
   // outputs for the performance counters.
   assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
-  assign CacheMiss = CacheAccess & ~Hit;
+  assign CacheMiss = CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage;
 
   // special case on reset. When the fsm first exists reset twayhe
   // PCNextF will no longer be pointing to the correct address.