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Reduced duplicated logic in fdivsqrtcycles

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This commit is contained in:
David Harris 2023-11-10 11:25:54 -08:00
parent 255873a50c
commit 8f87860146
1 changed files with 7 additions and 2 deletions
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9
src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -33,7 +33,10 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
input logic [P.DIVBLEN:0] nE,
output logic [P.DURLEN-1:0] CyclesE
);
logic [P.DURLEN+1:0] Nf, fbits; // number of fractional bits
logic [P.DURLEN-1:0] fpcycles; // number of cycles for floating-point operation
// DIVN = P.NF+3
// NS = NF + 1
// N = NS or NS+2 for div/sqrt.
@ -68,8 +71,10 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
if (SqrtE) fbits = Nf + 2 + 1; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1; is it related to DIVCOPIES logic below?
// if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
else fbits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : (fbits -1)/(P.RK) + 1;
else CyclesE = (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
assign fpcycles = (fbits-1)/(P.RK) + 1;
if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : fpcycles;
else CyclesE = fpcycles;
end
/* verilator lint_on WIDTH */