From 8f87860146fa2f58cc6d3cc42020d4199d0334b2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 10 Nov 2023 11:25:54 -0800 Subject: [PATCH] Reduced duplicated logic in fdivsqrtcycles --- src/fpu/fdivsqrt/fdivsqrtcycles.sv | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index 2122317fe..e9fbc6042 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -33,7 +33,10 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) ( input logic [P.DIVBLEN:0] nE, output logic [P.DURLEN-1:0] CyclesE ); + logic [P.DURLEN+1:0] Nf, fbits; // number of fractional bits + logic [P.DURLEN-1:0] fpcycles; // number of cycles for floating-point operation + // DIVN = P.NF+3 // NS = NF + 1 // N = NS or NS+2 for div/sqrt. @@ -68,8 +71,10 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) ( if (SqrtE) fbits = Nf + 2 + 1; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1; is it related to DIVCOPIES logic below? // if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : (fbits -1)/(P.RK) + 1; - else CyclesE = (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES); + assign fpcycles = (fbits-1)/(P.RK) + 1; + + if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : fpcycles; + else CyclesE = fpcycles; end /* verilator lint_on WIDTH */