Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

fixed sticky bit logic bug

Browse Source
This commit is contained in:
Kevin Kim 2023-07-06 19:48:25 -07:00
parent 654f6dee3f
commit 8d898b16c7
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/fpu/divremsqrt/divremsqrtround.sv
View File

@ -167,7 +167,7 @@ module divremsqrtround import cvw::*; #(parameter cvw_t P) (
// only add the Addend sticky if doing an FMA opperation
// - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
assign Sticky = DivSticky&DivOp;
assign Sticky = DivSticky&DivOp | NormSticky;